Order this document MC100EP222/D Voltage ECL/PECL 1:15 Clock Driv
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Order this document MC100EP222/D
Voltage ECL/PECL 1:15 Clock Driver
MC100EP222 voltage, skew 1:15 differential ECL/PECL clock distribution buffer. MC100EP222 been designed optimized 2.5V 3.3V systems. Target applications this clock driver high performance clock distribution systems computer, networking telecommunication systems. Features: differential outputs output banks)
MC100EP222
selectable differential inputs Selectable frequency outputs Operates from -2.5, -3.3V (ECL) 2.5, 3.3V (PECL) power supply
VOLTAGE 3.3V/2.5V 1:15 DIFFERENTIAL ECL/PECL CLOCK DRIVER
Extended temperature operating range MC100EP222 device characteristics allows low-skew clock distribution differential single-ended LVECL/LVPECL signals. Typical applications MC100EP222 primary clock distribution systems backplanes high-performance computer, networking telecommunication systems. MC100EP222 operated from 3.3V 2.5V positive supply (PECL mode) without requirement negative supply line. Each four output banks two, three, four differential clock SUFFIX output pairs independently configured distribute input 52-LEAD LQFP PACKAGE frequency input frequency. FSELA, FSELB, FSELC, EXPOSED FSELD CLK_SEL asychronous control inputs. changes CASE 1336 control inputs require pulse resynchronization outputs. functionality control input, "Timing Diagram" page Each CLK0, CLK1 inputs used differential single-ended. single-ended signals, connect bypassed output reference unused input pair. MC100EP222 guarantees output-to-output skew (70) device-to-device skew max. ensure skew clock signals application, both sides differential output pair need terminated identically, even only side used. When fewer than fifteen pairs used, identical termination output pairs same package side recommended. outputs side used, recommended leave these outputs open unterminated. This will maintain minimum output skew.
08/01
Motorola, Inc. 2001
MC100EP222
FSELA
CLK0
CLK0
CLK1
CLK1
CLK_SEL
FSELB
FSELC
FSELD
Figure MC100EP222 Logic Diagram
Figure MC100EP222 Function Diagram
TIMING SOLUTIONS
MC100EP222
Figure Lead Package Pinout (Top View)
VCCO VCCO VCCO VCCO FSELC FSELD
VCCO VCCO VCCO
MC100EP222
CLK_SEL
CLK0
CLK0
FSELA
FSELB
CLK1
CLK1
Table FUNCTION TABLE
Control FSELA (asynchronous) FSELB (asynchronous) FSELC (asynchronous) FSELD (asynchronous) CLK_SEL (asynchronous) (asynchronous)
CLK0 Active
CLK1 Reset
TIMING SOLUTIONS
MC100EP222
Table CONFIGURATION
CLK0, CLK0 CLK1, CLK1 CLK_SEL QAn, QBn, QCn, QDn, FSELA FSELB FSELC FSELD VEEa VCC, VCCO Input Input Input Output Output Output Output Input Input Input Input Input Output Supply Supply Type ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL Description Differential reference clock signal input Alternative differential reference clock signal input Clock input select Bank differential outputs Bank differential outputs Bank differential outputs Bank differential outputs Selection bank output frequency Selection bank output frequency Selection bank output frequency Selection bank output frequency Reset bias output single ended input operation Negative power supply Positive power supply. VCCO pins must connected positive power supply correct operation
mode (negative power supply mode), either -3.3V -2.5V connected (0V). PECL mode (positive power supply mode), connected (0V) either +3.3V +2.5V both modes, input output levels referrenced most positive supply.
Table ABSOLUTE MAXIMUM RATINGSa
Symbol VOUT IOUT Supply Voltage Input Voltage Output Voltage Input Current Output Current Storage temperature Characteristics -0.3 -0.3 -0.3 VCC+0.3 VCC+0.3 Unit Condition
Absolute maximum continuos ratings those maximum values beyond which damage device occur. Exposure these conditions conditions beyond those indicated adversely affect device reliability. Functional operation absolute-maximum-rated conditions implied.
Table GENERAL SPECIFICATIONS
Symbol Thermal resistance junction ambient Thermal resistance junction case Characteristics Output termination voltage Protection (Machine model) Protection (Human body model) Protection (Charged device model Latch-up immunity 1500 application informationb application information Unit Inputs Condition
Output termination voltage VCC=2.5V operation supported power consumption device will increase Proper thermal management critical reliable system operation. This especially true high-fanout high drive capability products. Thermal package information exposed land pattern design recommendations available applications section this datasheet. addition, means calculating power consumption, corresponding temperature relationsship long-term reliability addressed Motorola application note AN1545. Thermal modeling recommended MC100EP222.
TIMING SOLUTIONS
MC100EP222
Table PECL Characteristics (VCCO 2.375V 3.8V, GND)
Symbol Characteristics -40°C 25°C 85°C Unit Condition
Clock input pairs CLK0, CLK0, CLK1, CLK1 (LVPECL differential signals) Differential input voltagea VCC=3.3V VCC=2.5V Differential cross point voltageb CLK0,CLK1 Input Current 0.10 0.15 VCC-0.4 0.10 0.15 VCC-0.4 0.10 0.15 VCC-0.4
VCMR
Control inputs (LVPECL single ended) Input high voltage Input voltage Input Current VCC-1.165 VCC-0.880 VCC-1.165 VCC-0.880 VCC-1.165 VCC-0.880 VCC-1.810 VCC-1.480 VCC-1.810 VCC-1.480 VCC-1.810 VCC-1.480 IOH= -30mAc IOL= -5mAc pins
LVPECL clock outputs (QAn, QAn, QBn, QBn, QCn, QCn, QDn, QDn) Output High Voltage Output Voltage VCC-1.20 VCC-1.90 VCC-0.82 VCC-1.40 VCC-1.15 VCC-1.90 VCC-0.82 VCC-1.40 VCC-1.15 VCC-1.9 VCC-0.82 VCC-1.40
Supply current Max. Supply Current Max. Supply Currentd Output reference voltagee VCC=3.3V VCC=2.5V
VCC-1.35 VCC-1.24 VCC-1.35 VCC-1.24 VCC-1.35 VCC-1.24 VCC-1.35 VCC-1.24 VCC-1.35 VCC-1.22 VCC-1.35 VCC-1.22 minimum differential input voltage swing required maintain device functionality. VCMR (DC) crosspoint differential input signal. Functional operation obtained when crosspoint within VCMR (DC) range input swing lies within (DC) specification. Equivalent output termination VTT. includes current through output resistors (all outputs terminated VTT). output used bias complementary input when device used with single ended clock signals. sink max. current.
TIMING SOLUTIONS
MC100EP222
Table Characteristics (VCC VCCO GND, -3.8V -2.375V)
Symbol Characteristics -40°C 25°C 85°C Unit Condition
Clock input pairs CLK0, CLK0, CLK1, CLK1 (ECL differential signals) Differential input voltagea VEE=-3.3V VEE=-2.5V Differential cross point voltageb CLK0,CLK1 Input Current 0.10 0.15 VEE+1.0 -0.4 0.10 0.15 VEE+1.0 -0.4 0.10 0.15 VEE+1.0 -0.4
VCMR
inputs single ended signals Input high voltage Input voltage Input Current -1.165 -1.810 -0.880 -1.480 -1.165 -1.810 -0.880 -1.480 -1.165 -1.810 -0.880 -1.480 IOH= IOL= Pins
LVPECL clock outputs (Q0-19, Q0-19) Output High Voltage Output Voltage -1.20 -1.90 -0.82 -1.40 -1.20 -1.90 -0.82 -1.40 -1.20 -1.90 -0.82 -1.40
Supply current Max. Supply Current Max. Supply Currentd Output reference voltagee VEE=-3.3V VEE=-2.5V -1.35 -1.35 -1.24 -1.24 -1.35 -1.35 -1.24 -1.22 -1.35 -1.35 -1.24 -1.22
minimum differential input voltage swing required maintain device functionality. VCMR (DC) crosspoint differential input signal. Functional operation obtained when crosspoint within VCMR (DC) range input swing lies within (DC) specification. Equivalent output termination VTT. includes current through output resistors (all outputs terminated VTT). output used bias complementary input when device used with single ended clock signals. sink max. current.
TIMING SOLUTIONS
MC100EP222
Table Characteristicsa (VCC VCCO 2.375V 3.8V, GND) (VEE -3.8V -2.375V, VCCO GND)
Symbol Characteristics
Differential input voltageb (peak-to-peak) CLK0, CLK1
-40°C
25°C
85°C
Unit
Condition
Clock input pair CLK0, CLK0, CLK1, CLK1 (PECL/ECL differential signals)
VCMR
Differential cross point voltagec PECL mode CLK0, CLK1 VEE+1.0 mode CLK0, CLK1 Input Frequency
fCLK
-0.4 VEE+1.0 VCC-0.4
-0.4 VEE+1.0 VCC-0.4
-0.4 VCC-0.4
PECL/ECL clock outputs (QAn, QAn, QBn, QBn, QCn, QCn, QDn, QDn)
VO(P-P) Propagation Delay CLKN
1040
Diff.
Differential output voltage (peak-to-peak) Output-to-output skew (within device) Output-to-output skew within QA[0:1] QB[0:2] QC[0:3] QD[0:5] QAN, QBN, (single freq.) outputs (single freq.) QAN, QBN, (multiple freq.) outputs (multiple freq.)
49.5 50.5
49.5 50.5
49.5 50.5
tsk(O) tsk(O)
Diff. Diff.
tsk(PP) tJIT(CC)
Output-to-output skew (part-to-part) Output cycle-to-cycle jitter (RMS) Output duty cycle Output Rise/Fall Time
Diff.
DCfref=
characteristics apply parallel output termination VTT. minimum differential input voltage swing required maintain characteristics including device-to-device skew. VCMR (AC) crosspoint differential input signal. operation obtained when crosspoint within VCMR range input swing lies within (AC) specification. Violation VCMR (AC) (AC) impacts device propagation delay part-to-part skew.
TIMING SOLUTIONS
MC100EP222
Differential Pulse Generator
MC100EP222
Figure MC100EP222 test reference
CLKN CLKN
VPP=0.8V
VCMR=VCC-1.3V
(CLK
Figure MC100EP222 reference measurement waveform
TIMING SOLUTIONS
MC100EP222
APPLICATIONS INFORMATION
Using thermally enhanced package MC100EP222 MC100EP222 uses thermally enhanced exposed (EP) lead LQFP package. package molded that leadframe exposed surface package bottom side. exposed metal will provide thermal impedance that supports power consumption MC100EP222 high-speed bipolar integrated circuit eases power management task system design. thermal land pattern printed circuit board thermal vias recommended order take advantage enhanced thermal capabilities MC100EP222. Direct soldering exposed thermal land will provide efficient thermal path. multilayer board designs, thermal vias thermally connect exposed internal copper planes. Number vias, spacing, diameters land pattern design depend application amount heat removed from package. nine thermal array, arranged array using pitch center thermal land absolute minimum requirement MC100EP222 applications multi-layer boards. recommended thermal land design comprises "Recommended thermal land pattern", providing efficient heat removal path.
units
recommended thermal array. Because large solder mask opening result poor release, opening should subdivided shown Figure nominal package standoff stencil thickness mils should considered.
units
Thermal array (5x5), pitch, diameter
Figure Recommended solder mask openings thermal system analysis junction temperature calculation thermal resistance parameters package provided. thermal system analysis junction temperature calculation thermal resistance parameters package provided: Table Thermal Resistancea
ConvectionLFPM Natural RTHJAb °C/W 57.1 50.0 46.9 43.4 38.6 RTHJAc °C/W 24.9 21.3 20.0 18.7 16.9 15.8 RTHJCd °C/W RTHJBe °C/W
Thermal array (5x5), pitch, diameter
Exposed land pattern
Figure Recommended thermal land pattern diameter should approx. with copper barrel plating. Solder wicking inside resulting voids during solder process must avoided. copper plating does plug vias, stencil print solder paste onto printed circuit pad. This will supply enough solder paste fill those vias starve solder joints. attachment process exposed package equivalent standard surface mount packages. Figure "Recommended solder mask openings" shows recommend solder mask opening with respect
Thermal data pattern with thermal array 2S2P boards (based empirical results) Junction ambient, single layer test board, JESD51-6 Junction ambient, four conductor layer test board (2S2P), JES51-6 Junction case, MIL-SPEC 883E, method 1012.1 Junction board, four conductor layer test board (2S2P) JESD 51-8 recommended that users employ thermal modeling analysis assist applying general recommendations their particular application. exposed MC100EP222 package does have electrical impedance path substrate integrated circuit terminals. thermal land should connected through connection internal board layers.
TIMING SOLUTIONS
Exposed land pattern
MC100EP222
OUTLINE DIMENSIONS
SUFFIX PLASTIC LQFP PACKAGE CASE 1336-01 ISSUE
0.20
TIPS
X=A,
0.20
VIEW
PLATING
VIEW
BASE METAL
E1/2
D1/2
ROTATED CLOCKWISE NOTES: DIMENSIONS MILLIMETERS. INTERPRET DIMENSIONS TOLERANCES ASME Y14.5M, 1994. DATUMS DETERMINED DATUM PLANE DIMENSIONS DETERMINED SEATING PLANE DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL CAUSE LEAD WIDTH EXCEED MAXIMUM DIMENSION MORE THAN 0.08 DAMBAR CANNOT LOCATED LOWER RADIUS FOOT. MINIMUM SPACE BETWEEN PROTRUSION ADJACENT LEAD PROTRUSION 0.07 DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25mm SIDE. MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. EXACT SHAPE EACH CORNER OPTIONAL. THESE DIMENSIONS APPLY FLAT SECTION LEAD BETWEEN 0.25 FROM LEAD TIP. MILLIMETERS 1.70 0.05 0.20 1.30 1.50 0.271 0.334 0.27 0.33 0.123 0.136 0.122 0.132 12.00 10.00 0.65 12.00 10.00 0.45 0.75 1.00 0.08 0.08 0.20 0.20 6.50 7.50 6.50 7.50
0.08
SEATING PLANE
0.08
VIEW
VIEW
EXPOSED
VIEW
SECTION AB-AB
TIMING SOLUTIONS
MC100EP222
NOTES
TIMING SOLUTIONS
MC100EP222
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. MOTOROLA Stylized Logo registered Patent Trademark Office. other product service names property their respective owners. Motorola, Inc. 2001.
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TIMING SOLUTIONS MC100EP222/D
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