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Order this document MC100EP195/D Programmable Delay Chip MC1
Top Searches for this datasheetOrder this document MC100EP195/D Programmable Delay Chip MC100EP195 programmable delay chip (PDC) designed primarily clock de-skewing timing adjustment. provides variable delay differential input transition. delay section consists chain gates organized shown logic symbol. first delay elements feature gates that have been modified have delays 1.25 times basic gate delay approximately These elements provide EP195 with digitally-selectable resolution approximately required device delay selected seven address inputs D[0:8], which latched chip high signal latch enable (LEN) control. Because delay programmability EP195 achieved purely differential gate delays device will operate frequencies >1.0 while maintaining over output swing. EP195 thus offers very fine resolution, very high frequencies, that selectable entirely from digital input allowing very accurate system clock timing. tenth latched input, provided cascading multiple PDC's increased programmable range. cascade logic allows full control multiple PDC's, expense only single added line data each additional PDC, without need external gating. MC100EP195 PROGRAMMABLE DELAY CHIP Lead TQFP PLASTIC PACKAGE CASE 10ns Maximum Case Delay Range 20ps/Delay Step Resolution >1.0GHz Bandwidth Chip Cascade Circuitry 3.3V Supply Voltage Input Pulldown Resistors Pinout: 32-Lead (TBD) Function NAMES IN/IN D[0:9] CASCADE Signal Input Input Enable Select Inputs Signal Output Latch Enable Delay Delay Cascade Signal LOGIC DIAGRAM SIMPLIFIED 1.25 LATCH LATCH CASCADE CASCADE CASCADE DELAYS LONGER THAN STANDARD (STANDARD GATES GATES GATES GATES GATES 10/98 Motorola, Inc. 1998 MC100EP195 CHARACTERISTICS (VEE VEE(min) VEE(max); VCCO GND) Symbol Characteristic Input HIGH Current Power Supply Current 25°C 85°C Unit Condition CHARACTERISTICS (VEE VEE(min) VEE(max); VCCO GND) Symbol tPLH tPHL Characteristic Propagation Delay CASCADE Programmable Range (max) (min) Step Delay High High High High High High High High High Linearity Duty Cycle Skew tPHL-tPLH Setup Time Hold Time Release Time Jitter Output Rise/Fall Time 20-80% 20-80% (CASCADE) <5.0 <5.0 <5.0 1920 3840 25°C 85°C Unit Notes tRANGE tSKEW tjit Duty cycle skew guaranteed only differential operation measured from cross point input cross point output. This setup time defines amount time prior input signal delay device must set. This setup time minimum time that must asserted prior next transition IN/IN prevent output response greater than that IN/IN transition. This hold time minimum time that must remain asserted after negative going positive going prevent output response greater than that IN/IN transition. This release time minimum time that must deasserted prior next IN/IN transition ensure output response that meets specified propagation delay transition times. Specification limits represent amount delay added with assertion each individual delay control pin. various combinations asserted delay control inputs will typically realize resolution steps across specified programmable range. linearity specification guarantees which delay control input programmable steps will monotonic (i.e. increasing delay steps increasing binary counts control inputs Dn). Typically device will monotonic input, however under worst case conditions process variation, delays could decrease slightly with increasing binary counts when input LSB. With input device guaranteed monotonic over specified environmental conditions process variation. jitter device less than what measured without resorting very tedious specialized measurement techniques. ECLinPS ECLinPS Lite DL140 MC100EP195 OUTLINE DIMENSIONS SUFFIX PLASTIC PACKAGE CASE ECLinPS ECLinPS Lite DL140 MC100EP195 Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. 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