SYNCHRONOUS DRAM MODULE PC100- PC133-compliant JEDEC-standard, 16
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512MB (x64) 168-PIN SDRAM DIMMs
SYNCHRONOUS DRAM MODULE
PC100- PC133-compliant JEDEC-standard, 168-pin, dual in-line memory module (DIMM) Unbuffered 512MB 64), (128 Single +3.3V power supply Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal SDRAM banks hiding access/precharge Programmable burst lengths: full page Auto Precharge, including Concurrent Auto Precharge, Auto Refresh Modes 64ms, 8,192 cycle Auto Refresh cycle Self Refresh Mode LVTTL-compatible inputs outputs Serial Presence-Detect (SPD)
MT8LSDT6464A 512MB MT16LSDT12864A
latest data sheet, please refer site: www.micron.com/moduleds
Figure 168-Pin DIMM (MO-161)
Standard
Profile
Table
MODULE MARKINGS -13E -133 -10E
Timing parameters
PC100 tRCD 2-2-2 2-2-2 2-2-2 PC133 tRCD 2-2-2 3-3-3
OPTIONS
Package 168-pin DIMM (gold) Memory Clock/CAS Latency (133 MHz)/CL (133 MHz)/CL (100 MHz)/CL
MARKING
-13E -133 -10E
Table
PARTNUMBER
Part Numbers
Table
Address Table
CONFIGURATION 512MB MODULE MODULE (BA0, BA1) (A0-A12) (A0-A9, A11) (S0,S2; S1,S3)
MT8LSDT6464AG-13E_ MT8LSDT6464AG-133_ MT8LSDT6464AG-10E_ MT16LSDT12864AG-13E_ MT16LSDT12864AG-133_ MT16LSDT12864AG-10E_
NOTE:
SYSTEM SPEED
Refresh Count Device Banks Device Configuration Addressing Column Addressing Module Banks
(BA0, BA1) (A0-A12) (A0-A9, A11) (S0,S2)
designators component revision last characters each part number. Consult factory current revision codes. Example: MT8LSDT6464AG-133B1.
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
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PRODUCTS
SPECIFICATIONS DISCUSSED HEREIN EVALUATION REFERENCE PURPOSES ONLY SUBJECT CHANGE MICRON WITHOUT NOTICE. PRODUCTS ONLY WARRANTED MICRON MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
512MB (x64) 168-PIN SDRAM DIMMs
Table Assignment, Standard (168-Pin DIMM Front)
DQMB2 DQMB3 DQMB0 DQMB1 DQ16 DQ17 DQ18 DQ19 DQ20 CKE1 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Table
Assignment, Standard (168-Pin DIMM Back)
CKE0 DQMB6 DQMB7 CAS# DQMB4 DQMB5 RAS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SYMBOL SYMBOL SYMBOL SYMBOL DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
SYMBOL SYMBOL SYMBOL SYMBOL DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
Figure Locations (168-Pin DIMM)
Front View
Back View (Populated only module)
Indicates
PIN125 Indicates
Figure page Figure page module dimensions.
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512MB (x64) 168-PIN SDRAM DIMMs
Table Descriptions
SYMBOL RAS#, CAS#, CK0-CK3 TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS#, (along with define command being entered. Clock: driven system clock. SDRAM input signals sampled positive edge also increments internal burst counter controls output registers. Clock Enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides PRECHARGE POWER-DOWN SELF REFRESH operation (all device banks idle) CLOCK SUSPEND OPERATION (burst access progress). synchronous except after device enters power- down self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including disabled during power-down self refresh modes, providing standby power. Chip Select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Input/Output Mask: DQMB input mask signal write accesses output enable signal read accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (twoclock latency) when DQMB sampled HIGH during READ cycle. Bank Address: define which device bank ACTIVE, READ, WRITE, PRECHARGE command being applied. Address Inputs: Provide address ACTIVE commands, column address auto prcharge (A10) READ/WRITE commands, select location memory arrary respective device bank. sampled during PRECHARGE command determines whether PRECHARGE applies device bank (A10 LOW, device bank selected BA0, BA1) device banks (A10 HIGH). address inputs also provide op-code during MODE REGISTER command. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Presence-Detect Address Inputs: These pins used configure presence-detect device. Data I/O: Data bus. numbers correlate with symbols. Refer Assignment table number symbol information NUMBERS 111, 125,
CKE0, CKE1
Input
45,114,
-S3#
Input
112, 113, 130,
DQMB0-DQMB7
Input
BA0,
Input
121, 123,
A0-A12
Input
165-167 2-5, 7-11, 13-17, 19-20, 55-58, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156,158-161
SA0-SA2 DQ0-DQ63
Input Input Input/ Output
Input/ Serial Presence-Detect Data: bidirectional used Output transfer addresses data into presencedetect portion module.
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512MB (x64) 168-PIN SDRAM DIMMs
Table Descriptions
SYMBOL TYPE Supply DESCRIPTION Power Supply: +3.3V ±0.3V. numbers correlate with symbols. Refer Assignment table number symbol information NUMBERS 102, 110, 124, 133, 143, 157, 107, 116, 127, 138, 148, 152, 21-22, 24-25, 50-53, 61-62, 105-106, 108-109, 132, 134-137, 145-147,
Supply
Ground.
Connected: These pins connected these modules.
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512MB (x64) 168-PIN SDRAM DIMMs
Figure Functional Block Diagram Single Bank Modules
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 RAS# CAS# CKE0 A0-A11 RAS#: SDRAMs CAS#: SDRAMs CKE0: SDRAMs WE#: SDRAMs A0-A11: SDRAMs BA0: SDRAMs BA1: SDRAMs SDRAMs SDRAMs
3.3pF
DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
CK1,
10pF
NOTE:
resistor values unless otherwise specified. industry standard, Micron modules various component speed grades referenced module part numbering guide www.micron.com/numberguide.
SDRAMs MT48LC64M8A2TG
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
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512MB (x64) 168-PIN SDRAM DIMMs
Figure Functional Block Diagram Dual Bank Modules
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CKE1 CKE0 CAS# RAS# A0-A11
DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
CKE: SDRAMs U11-U19 CKE: SDRAMs U1-U9 CAS#: SDRAMs RAS#: SDRAMs WE#: SDRAMs A0-A11: SDRAMs BA0: SDRAMs BA1: SDRAMs SDRAMs SDRAMs
3.3pF
3.3pF
NOTE:
resistor values unless otherwise specified. industry standard, Micron modules various component speed grades referenced module part numbering guide www.micron.com/numberguide.
SDRAMs MT48LC64M8A2TG
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
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512MB (x64) 168-PIN SDRAM DIMMs
General Description
MT8LSDT6464A MT16LSDT12864A high-speed CMOS, dynamic random-access, 512MB memory modules organized configurations. These modules internally configured quadbank SDRAMS with synchronous interface (all signals registered positive edge clock signal CK). Read write accesses SDRAM modules burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank; A0-A12 select device row). address bits registered coincident with READ WRITE command used select starting column location burst access. These modules provide programmable READ WRITE burst length locations, full page, with burst terminate option. AUTO PRECHARGE function enabled provide selftimed precharge that initiateda burst sequence. These modules internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve highspeed, fully random access. Precharging device bank while accessing other three device banks will hide precharge cycles provide seamless, high-speed, random-access operation. These modules designed operate 3.3V, lowpower memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs outputs LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability syncronously burst data high data rate with automatic column-address generation, ability interleave between intenal banks order hide precharge time capability randomly change column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 512Mb SDRAM component data sheet.
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals, together with (2:0), which provide eight unique DIMM/EEPROM addresses.
SDRAM Functional Description
general, 512Mb SDRAMs quad-bank DRAMs that operate 3.3V include synchronous interface (all signals registered positive edge clock signal, CK). four banks configured devices used these modules configured 8,192 bit-rows 2,048 bit-columns, input/output bits. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with active command used select device bank accessed; select device bank, A0-A12 select device row. address bits A0-A9 registered coincident with READ WRITE command used select starting device column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation.
Initialization
SDRAMS must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constrants specified clock pin), SDRAM requires 100µs delay prior issuing command other than COM-
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512MB (x64) 168-PIN SDRAM DIMMs
MAND INHIBIT Starting some point during this 100µs period continuing least through this period, COMMAND INHIBIT commands should applied. Once 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device banks idle state. Once idle state, AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, should loaded prior applying operational command. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached, shown Burst Definition Table. block uniquely selected when burst length two; A2-A9, when burst length four; A3-A9, when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached, shown Table Burst Definition Table, page
Mode Register Definition
mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode write burst mode, shown Figure Mode Register Definition Diagram, page mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write burst mode, reserved future use. mode register must loaded when device banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation.
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type, starting column adress, shown Table Burst Definition Table, page
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable, shown Figure page burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths.
Figure Mode Register Definition
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512MB (x64) 168-PIN SDRAM DIMMs
Diagram Table
BURST LENGTH
Burst Definition Table
STARTING COLUMN ADDRESS ORDER ACCESSES WITHIN BURST TYPE SEQUENTIAL TYPE INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Supported
Full Page
NOTE:
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 n=A0-A9, Cn+1, Cn+2 (location 0-y) Cn+3, Cn+4. .Cn-1,
full-page accesses: 2,048 burst length two, A1-A9, select block burst; selects starting column within block. burst length four, A2-A9, select block four burst; A0-A1 select starting column within block. burst length eight, A3-A9, select block eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-A9, select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-A9, select unique column accessed, Mode Register ignored.
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
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512MB (x64) 168-PIN SDRAM DIMMs
Latency
latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Figure Latency Diagram. Table Latency Table, indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
Operating Mode
normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both READ WRITE bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result.
Write Burst Mode
When burst length programmed M0M2 applies both READ WRITE bursts; when programmed burst length applies READ bursts, write accesses single-location (nonburst) accesses.
Table
Latency Table
ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ)
Figure Latency Diagram
COMMAND
SPEED -13E -133 -10E
LATENCY
LATENCY
READ
DOUT
Latency
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
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512MB (x64) 168-PIN SDRAM DIMMs
Commands
Truth Table provides quick reference available commands. This followed written description each command. more detailed description commands operations, refer 512Mb SDRAM component data sheet.
Table
Truth Table SDRAM Commands DQMB Operation
RAS# CAS# DQMB ADDR Bank/Row Bank/Col Bank/Col Code Op-code Valid Active Active High-Z NOTES
HIGH commands shown except SELF REFRESH; notes appear following Truth Table NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z
NOTE:
A0-A12 provide address; BA0-BA1 determine which device bank made active. A0-A9, provide column address; HIGH enables auto-precharge feature (nonpersistent), while disables auto-precharge feature; BA0-BA1 determine which device bank being read from written LOW: BA0-BA1 determine which device bank being precharged. HIGH: device banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. A0-A11 define op-code written mode register should driven LOW. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
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512MB (x64) 168-PIN SDRAM DIMMs
Absolute Maximum Ratings
Stresses greater than those listed cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Voltage VDD, VDDQ Supply Relative +4.6V Voltage Inputs Pins Relative +4.6V Operating Temperature (Commercial) +70°C
Storage Temperature (plastic) -55°C +150°C Power Dissipation, 512MB Power Dissipation,
Table Electrical Characteristics Operating Conditions 512MB Module
Notes: notes appear page VDDQ +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: Command Address input Inputs, (All other pins under test DQMB OUTPUT LEAKAGE CURRENT: pins disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA) SYMBOL VDD, VDDQ -0.3 UNITS NOTES
Table Electrical Characteristics Operating Conditions Module
Notes: notes appear page VDDQ +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: Command Address input Inputs, (All other pins under test DQMB OUTPUT LEAKAGE CURRENT: pins disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA) SYMBOL VDD, VDDQ -0.3 UNITS NOTES
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512MB (x64) 168-PIN SDRAM DIMMs
Table Specifications Conditions 512MB Module
Notes: notes appear page VDD, VDDQ +3.3v ±0.3v; SDRAM component values only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device device banks idle; STANDBY CURRENT: Active Mode;CKE HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN) HIGH; HIGH SELF REFRESH CURRENT: 0.2V
SYMBOL IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7
-13E
-133
-10E
UNITS
NOTES 18,19,
1,720 1,600 1,600
1,440 1,440 1,440 3,200 2,960 2,960
7.8125µs
Table Specifications Conditions Module
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V; SDRAM component values only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN) HIGH; HIGH SELF REFRESH CURRENT: 0.2V
NOTE:
SYMBOL IDD1a IDD2b IDD3a IDD4a IDD5b IDD6
-13E
-133
-10E
UNITS
NOTES 18,19,
1,736 1,616 1,616
1,456 1,456 1,456 6,400 5,920 5,920
7.8125µs
IDD7b
Value calculated module bank this condition, other module banks Power-Down Mode (IDD2). Value calculated reflects module banks this condition
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512MB (x64) 168-PIN SDRAM DIMMs
Table Capacitance 512MB Module
Note notes appear page PARAMETER Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: DQMB Input/Output Capacitance: SCL, Input/Output Capacitance: SYMBOL CIO1 CIO2 13.3 30.4 17.3 15.2 30.4 UNITS
Table Capacitance Module
Note notes appearon page PARAMETER Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: DQMB Input/Output Capacitance: SCL, Input/Output Capacitance: SYMBOL CIO1 CIO2 13.3 60.8 17.3 15.2 30.4 UNITS
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
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512MB (x64) 168-PIN SDRAM DIMMs
Table Electrical Characteristics Recommended Operating Conditions
Notes: notes appear page Module timing parameters comply with PC100 PC133 Design Specs, based component parameters ACCHARACTERISTICS PARAMETER Access timefrom (pos.edge) Address hold time Address setup time high-level width low-level width Clock cycle time hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time load) ACTIVE PRECHARGE command ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period (8,192 rows) AUTOREFRESH period PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time
-13E SYMBOL CL=3 CL=2
-133 120,000
-10E UNITS 120,000 NOTES
AC(3) AC(2)
120,000
CL=3
CK(3) CK(2)
HZ(3) HZ(2)
7.5ns
Exit SELF REFRESH ACTIVE command
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512MB (x64) 168-PIN SDRAM DIMMs
Table Functional Characteristics
Notes: notes appear page PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs DQMto data high-impedance during READs WRITE command input data delay Data-into ACTIVE command Data-into PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Lastdata-into PRECHARGE command LOADMODEREGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command SYMBOL
-13E
-133
-10E
UNITS
NOTES
CKED
ROH(3) ROH(2)
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512MB (x64) 168-PIN SDRAM DIMMs
Notes
voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; 25°C; under test biased 1.4V; MHz. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range ensured. initial pause 100µs required after powerup, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load:
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. input transition time longer than 1ns, then timing referenced (MAX) (MIN) longer 1.5V crossover point. Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate. Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate.
Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 10ns -10E, 7.5ns -13E. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -13E; 7.5ns -133 -10E after first clock delay, after last WRITE executed. exceed limit precharge mode. Precharge mode only. JEDEC PC100 specify three clocks. -133/-13E with load 4.6ns guaranteed design. Parameter guaranteed design. -13E, 7.5ns; -133, 7.5ns; -10E, CL=2 10ns HIGH during refresh command period (MIN) else LOW. IDD6 limit actually nominal value does result fail value. Refer device data sheet timing waveforms. value tRAS used -13E speed grade modules calculated from Leakage number reflects worst case leakage possible through module pin, what each memory device contributes.
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Clock Data Conventions
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions shown Figure Figure
Acknowledge
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data shown Figure device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Start Condition
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
Stop Condition
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response From Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
512MB (x64) 168-PIN SDRAM DIMMs
Table EEPROM Device Select Code
most significant (b7) sent first DEVICE TYPE IDENTIFIER Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE
Table EEPROM Operating Modes
MODE Current Address Read RandomAddressRead Sequential Read Byte Write Page Write
BYTES
INITIAL SEQUENCE Start, Device Select, Start, Device Select, Address RESTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
Table SERIAL Presence-Detect EEPROM Operating Conditions
+3.3V ±0.3V; voltages referenced PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs 3.3V ±10% POWER SUPPLY CURRENT: Clock frequency SYMBOL ICCS Write Read UNITS
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
512MB (x64) 168-PIN SDRAM DIMMs
Figure EEPROM Timing Diagram
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
Table Serial Presence-Detect EEPROM Operating Conditions
+3.3V ±0.3V; voltages referenced PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time ClockHIGHperiod Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE:
SYMBOL
UNITS
NOTES
HD:DAT HD:STA
HIGH
SU:DAT SU:STA
SU:STO
EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address.
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
512MB (x64) 168-PIN SDRAM DIMMs
Table Serial Presence-Detect Matrix
+3.3V ±0.3V; "1"/"0": Serial Data, "driven HIGH"/"driven LOW" BYTE DESCRIPTION NUMBER BYTES USED MICRON TOTAL NUMBER MEMORY BYTES MEMORY TYPE NUMBER ROWADDRESSES NUMBER COLUMN ADDRESSES NUMBER MODULE BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM CLK, (CAS LATENCY MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY FROM BACK-TO-BACK RANDOM COLUMN ADDRESSES,tCCD BURST LENGTHS SUPPORTED NUMBER BANKS DRAM DEVICE LATENCIES SUPPORTED LATENCY LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES:GENERAL SDRAM CYCLE TIME (CAS LATENCY (-133/-10E) SDRAMACCESSFROMCLK, (CAS LATENCY SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM CLK, (CAS LATENCY MINIMUM PRECHARGE TIME, MINIMUM ACTIVE ACTIVE, tRRD 15ns (-13E) 20ns (-133/-10E) 14ns (-13E) 15ns (-133) 20ns (-10E) 15ns (-13E) 20ns (-133/-10E) 45ns (-13E) 44ns (133) 50ns (-10E) ENTRY (VERSION) SDRAM LVTTL (-13E) 7.5ns (-133) (-10E) 5.4ns (-13E/-133) (-10E) NON-ECC 7.8125µs/SELF NONE PAGE UNBUFFERED 7.5ns (13E) 10ns (-133/-10E) 5.4ns (-13E) (-133/-10E) MT8LSDT6464A MT16LSDT12864A
MINIMUM RAS# CAS# DELAY, tRCD MINIMUM RAS# PULSE WIDTH, tRAS (See note
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
512MB (x64) 168-PIN SDRAM DIMMs
Table Serial Presence-Detect Matrix (Continued)
+3.3V ±0.3V; "1"/"0": Serial Data, "driven HIGH"/"driven LOW" BYTE 36-61 DESCRIPTION MODULE BANK DENSITY COMMAND ADDRESS SETUP TIME, tAS, tCMS COMMAND ADDRESS HOLD TIME, tAH, tCMH DATA SIGNAL INPUT SETUP TIME, DATA SIGNAL INPUT HOLD TIME, RESERVED REVISION CHECKSUM BYTES 0-62 ENTRY (VERSION) 512MB 1.5ns (-13E/-133) (-10E) 0.8ns (-13E/-133) (-10E) 1.5ns (-13E/-133) (-10E) 0.8ns (-13E/-133) (-10E) REV. (-13E) (-133) (-10E) MICRON MT8LSDT6464A Variable Data 01-04 Variable Data Variable Data Variable Data MT16LSDT12864A Variable Data 01-04 Variable Data Variable Data Variable Data
65-71 73-90 95-98 99-125
NOTE:
MANUFACTURER'S JEDEC CODE MANUFACTURER'S JEDEC CODE(CONT.) MANUFACTURING LOCATION MODULE PART NUMBER (ASCII) IDENTIFICATION CODE IDENTIFICATION CODE (CONT.) YEAR MANUFACTURE WEEK MANUFACTURE MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY SDRAM COMPONENT CLOCK DETAIL
(-13E/ -133/-10E)
value tRAS used -13E modules calculated from tRP. Actual device spec. value 37ns.
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
512MB (x64) 168-PIN SDRAM DIMMs
Figure 512MB Module Dimensions
STANDARD
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .125 (3.18)
.079 (2.00) (2X)
1.380 (35.05) 1.370 (34.80)
.118 (3.00) (2X) .118 (3.00) .250 (6.35) .118 (3.00) 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) .050 (1.27)
.700 (17.78)
.128 (3.25) (2X) .118 (3.00)
.054 (1.37) .046 (1.17)
(PIN BACKSIDE)
4.550 (115.57)
(PIN BACKSIDE)
PROFILE
FRONT VIEW
5.256 (133.50) 5.244 (133.20)
.125 (3.18)
.079 (2.00) (2X)
1.131 (28.73)
.700 (17.78) 1.119 (28.42)
.118 (3.00) (2X) .118 (3.00) .250 (6.35) .118 (3.00) 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) .050 (1.27)
.128 (3.25) (2X) .118 (3.00)
.054 (1.37) .046 (1.17)
(PIN BACKSIDE)
4.550 (115.57)
(PIN BACKSIDE)
NOTE:
dimensions inches (millimeters) typical where noted.
64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
512MB (x64) 168-PIN SDRAM DIMMs
Figure Module Dimensions
STADARD
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .157 (3.99)
.079 (2.00) (2X)
1.380 (35.05) 1.370 (34.80)
.118 (3.00) (2X) .118 (3.00) .250 (6.35) .118 (3.00) 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) .050 (1.27)
.700 (17.78)
.128 (3.25) (2X) .118 (3.00)
.054 (1.37) .046 (1.17)
4.550 (115.57)
BACK VIEW
PROFILE
FRONT VIEW
5.256 (133.50) 5.244 (133.20)
.157 (3.99)
.079 (2.00) (2X)
1.131 (28.73)
.700 (17.78) 1.119 (28.42)
.118 (3.00) (2X) .118 (3.00) .250 (6.35) .118 (3.00) 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) .050 (1.27)
.128 (3.25) (2X) .118 (3.00)
.054 (1.37) .046 (1.17)
4.550 (115.57)
BACK VIEW
NOTE:
dimensions inches (millimeters) typical where noted.
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64,128 SDRAM DIMMs SD8_16C64_128x64AG_A.fm Rev. 11/02
©2002, Micron Technology Inc.
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