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Intel® Xeon Processor with 512-KB L2 Cache at 1.80 GHz to 3 GHz

Order Number: 298642-006 March 2003

Intel® Xeon Processor with 512-KB L2 Cache at 1.80 GHz to 3 GHz
Datasheet
Product Features
512 KB Advanced Transfer L2 Cache (on-die, full speed Level 2 cache) with 8-way associativity and Error Correcting Code (ECC) Enables system support of up to 64 GB of physical memory Streaming SIMD Extensions 2 (SSE2) - 144 new instructions for double-precision floating point operations, media / video streaming, and secure transactions Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance Power Management capabilities - System Management mode - Multiple low-power states Advanced System Management Features - System Management Bus - Processor Information ROM (PIROM) - OEM Scratch EEPROM - Thermal Monitor - Machine Check Architecture (MCA)
The Intel® Xeon processor with 512 KB L2 cache is designed for high-performance dualprocessor workstation and server applications. Based on the Intel® NetBurst microarchitecture and the new Hyper-Threading Technology, it is binary compatible with previous Intel Architecture (IA-32) processors. The Intel Xeon processor with 512 KB L2 cache is scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP, Windows 2000, Linux, and UNIX. The Intel Xeon processor with 512 KB L2 cache delivers compute power at unparalleled value and flexibility for powerful workstations, internet infrastructure, and departmental server applications. The Intel® NetBurst micro-architecture and HyperThreading Technology deliver outstanding performance and headroom for peak internet server workloads, resulting in faster response times, support for more users, and improved scalability.
Order Number: 298642-006 March 2003
Datasheet
Contents
Datasheet
Contents
8.4 Thermal Specifications .................................................. 127 Debug Tools Specifications ..................................................... 128 9.1 Logic Analyzer Interface (LAI) ............................................ 128
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Figures
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44 sors 45 46 47 48 49 50 51 52
Mechanical Representation of the Boxed Processor Passive Heatsink for 2 - 2.80 GHz proces........................................................................ 116 Retention Mechanism ....................................................... 118 Boxed Processor Clip....................................................... 119 Multiple View Space Requirements for the Boxed Processor......................... 120 Fan Connector Electrical Pin Sequence ......................................... 121 Processor Wind Tunnel General Dimensions ..................................... 123 Processor Wind Tunnel Detailed Dimensions..................................... 124 Exploded View of the 1U Thermal Solution....................................... 125 Assembled View of the 1U Thermal Solution..................................... 126
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Tables
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Thermal Sensor SMBus Addressing .............................................. 114 Memory Device SMBus Addressing .............................................. 114 Fan Cable Connector Requirements .............................................. 122 Fan Power and Signal Specifications ............................................. 122
Datasheet
Revision History
Date of Release January 2002 April 2002 May 2002 September 2002 Revision No. -001 -002 -003 -004 Initial datasheet release. Addition of 2.40 GHz Data Updated Figures 10 and 11 Made PWRGOOD updates Addition of 2.60 and 2.80 GHz Data Updated Thermal Requirements Updated Thermal Requirements September 2002 -005 Updated Table 6, 7 Added Table 12 Added 3 GHz information. Edited definitions with current terminology. Added two TDP loadline figures in chapter 6. Added notes to signal definition tables for symmetric agents. Changed text., figures and tables for the boxed processor section. Description
February 2003
Datasheet
Intel® Xeon Processor with 512 KB L2 Cache
Introduction
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Intel® Xeon Processor with 512 KB L2 Cache
Terminology
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
· 603-pin socket - The connector which mates the Intel® Xeon processor with 512 KB L2
cache to the baseboard. The 603-pin socket is a surface mount technology (SMT), zero insertion force (ZIF) socket utilizing solder ball attachment to the platform. See the 603-Pin Socket Design Guidelines for details regarding this socket.
· Central Agent - The central agent is the host bridge to the processor and is typically known as
the chipset.
· Flip Chip Ball Grid Array (FCBGA) - Microprocessor packaging using "flip chip" design,
where the processor is attached to the substrate face-down for better signal integrity, more efficient heat removal and lower inductance.
· Front Side Bus - Front Side Bus (FSB) is the electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All memory and I / O transactions as well as interrupt messages pass between the processor and chipset over the FSB.
· Intel® Xeon processor with 512 KB L2 cache - The entire processor in its INT-mPGA
package, including processor core in its FC-BGA package, integrated heat spreader (IHS), and interposer.
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Intel® Xeon Processor with 512 KB L2 Cache
· Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal
solution to the processor.
specifications are to the pads of the processor core.
· Processor Information ROM (PIROM) - An SMBus accessible memory device located on
· Retention mechanism - The support components that are mounted through the baseboard to
the chassis to provide mechanical retention for the processor and heatsink assembly.
· Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory) - An
SMBus accessible memory device located on the processor interposer. This memory device can be used by the OEM to store information useful for system management. See Section 7.4 for details on the Scratch EEPROM.
· SMBus - System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the system. It is based on the principals of the operation of the I2C two-wire serial bus from Philips Semiconductor. Note: "I2C is a two-wire communications bus / protocol developed by Philips. SMBus is a subset of the I2C bus / protocol and was developed by Intel. Implementations of the I2C bus / protocol or the SMBus bus / protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation."
· Symmetric Agent - A symmetric agent is a processor which shares the same I / O subsystem
and memory array, and runs the same operating system as another processor in a system. Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems. Intel® Xeon (DP - Dual Processor) processors should only be used in SMP systems which have two or fewer symmetric agents.
State of Data
The data contained in this document is subject to change. It is the best information that Intel is able to provide at the publication date of this document.
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Intel® Xeon Processor with 512 KB L2 Cache
References
The reader of this specification should also be familiar with material and concepts presented in the following documents:.
Intel Order Number1 241618 245470 245471 245472 298252 298348 249672 249678 249206 249205 298646 298644 249679 298645 http://developer.intel.com2 http://developer.intel.com http://developer.intel.com http://developer.intel.com http://developer.intel.com http://www.sbs-forum.org / smbus http://developer.intel.com http://support.intel.com / support / processors / xeon
Processor and Intel 860 Chipset Platform Design Guide
Intel® Xeon Processor Thermal Design Guidelines 603 -Pin Socket Design Guidelines Intel® Xeon Processor Specification Update CK00 Clock Synthesizer / Driver Design Guidelines VRM 9.0 DC-DC Converter Design Guidelines VRM 9.1 DC-DC Converter Design Guidelines Dual Intel® Xeon Guidelines
Processor Voltage Regulator Down (VRD) Design
ITP700 Debug Port Design Guide Intel® Xeon Processor with 512 KB L2 Cache System Compatibility Guidelines Intel® Xeon Processor with 512 KB L2 Cache Signal Integrity Models Intel® Xeon Processor with 512 KB L2 Cache Mechanical Models in ProE Format Intel® Xeon Processor with 512 KB L2 Cache Mechanical Models in IGES Format Intel® Xeon Processor with 512 KB L2 Cache Thermal Models (FloTherm and ICEPAK format) Intel® Xeon Processor with 512 KB L2 Cache Core Boundary Scan Descriptor Language (BSDL) Model System Management Bus Specification, rev 1.1 Wired for Management 2.0 Design Guide Boxed Integration Notes
NOTES:
1. Contact your Intel representative for the latest revision of documents without order numbers. 2. The signal integrity models are in IBIS format.
Datasheet
Intel® Xeon Processor with 512 KB L2 Cache
Electrical Specifications
Front Side Bus and GTLREF
Most Intel® Xeon processor with 512 KB L2 cache front side bus signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. The processor termination voltage level is VCC, the operating voltage of the processor core. The use of a termination voltage that is determined by the processor core allows better voltage scaling on the processor front side bus. Because of the speed improvements to data and address busses, signal integrity and platform design methods become more critical than with previous processor families. Front side bus design guidelines are detailed in the appropriate platform design guide (refer to Section 1.3). The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard (See Table 13 for GTLREF specifications). Termination resistors are provided on the processor silicon and are terminated to its core voltage (VCC). The on-die termination resistors are a selectable feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die termination can be enabled to control reflections on the transmission line. For middle bus agents, on-die termination must be disabled. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to Section 2.12 for details on ODTEN resistor termination requirements. Note: Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard. See Table 4 for details regarding these signals. The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the front side bus, including trace lengths, is highly recommended when designing a system. Please refer to http://developer.intel.com to obtain the Intel® Xeon Processor with 512 KB L2 Cache Signal Integrity Models.
Power and Ground Pins
For clean on-chip power distribution, the Intel Xeon processor with 512 KB L2 cache has 190 VCC (power) and 189 VSS (ground) inputs. All VCC pins must be connected to the system power plane, while all VSS pins must be connected to the system ground plane. The processor VCC pins must be supplied the voltage determined by the processor VID (Voltage ID) pins.
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition.
Datasheet
Intel® Xeon Processor with 512 KB L2 Cache
Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 6. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and guidelines, refer to the appropriate platform design guidelines.
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and the baseboard designer must ensure a low interconnect resistance from the regulator (or VRM pins) to the 603-pin socket. Bulk decoupling may be provided on the voltage regulation module (VRM) to meet help meet the large current swing requirements. The remaining decoupling is provided on the baseboard. The power delivery path must be capable of delivering enough current while maintaining the required tolerances (defined in Table 6). For further information regarding power delivery, decoupling, and layout guidelines, refer to the appropriate platform design guidelines.
Front Side Bus AGTL+ Decoupling
The Intel® Xeon processor with 512 KB L2 cache integrates signal termination on the die as well as part of the required high frequency decoupling capacitance on the processor package. However, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate platform design guidelines.
Front Side Bus Clock (BCLK1:0) and Processor Clocking
BCLK1:0 directly controls the front side bus interface speed as well as the core frequency of the processor. As in previous generation processors, the processor core frequency is a multiple of the BCLK1:0 frequency. The maximum processor bus ratio multiplier will be set during manufacturing. The default setting will equal the maximum speed for the processor. The BCLK1:0 inputs directly control the operating speed of the front side bus interface. The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. Clock multiplying within the processor is provided by the internal PLL, which requires a constant frequency BCLK1:0 input with exceptions for spread spectrum clocking. Processor DC and AC specifications for the BCLK1:0 inputs are provided in Table 7 and Table 14, respectively. These specifications must be met while also meeting signal integrity requirements as outlined in Chapter 3.0. The processor utilizes a differential clock. Details regarding BCLK1:0 driver specifications are provided in the CK00 Clock Synthesizer / Driver Design Guidelines. Table 1 contains the supported bus fraction ratios and their corresponding core frequencies.
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Intel® Xeon Processor with 512 KB L2 Cache
Table 1.
Front Side Bus-to-Core Frequency Ratio
Front Side Bus-to-Core Frequency Ratio 1 / 16 1 / 17 1 / 18 1 / 19 1 / 20 1 / 21 1 / 22 1 / 24 1 / 26 1 / 28 1 / 30 Core Frequency 1.60 GHz 1.70 GHz 1.80 GHz 1.90 GHz 2 GHz 2.10 GHz 2.20 GHz 2.40 GHz 2.60 GHz 2.80 GHz 3 GHz
Bus Clock
Table 2. Front Side Bus Clock Frequency Select Truth Table for BSEL1:0
BSEL1 L L H H BSEL0 L H L H Bus Clock Frequency 100 MHz Reserved Reserved Reserved
PLL Filter
VCCA and VCCIOPLL are power sources required by the processor PLL clock generator. This requirement is identical to that of the Intel Xeon processor. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I / O timings as well as internal core timings (i.e. maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC. A typical filter topology is shown in Figure 1.
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Intel® Xeon Processor with 512 KB L2 Cache
The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or CIO in Figure 1), is as follows:
The filter requirements are illustrated in Figure 2. For recommendations on implementing the filter refer to the appropriate platform design guidelines.
Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution
Socket pin
Processor interposer "pin" R-Socket VCCA PLL R-Socket VSSA C Processor
Baseboard via that connects filter to VCC plane
R-Trace L1 / L2
R-Socket
VCCIOPLL
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Intel® Xeon Processor with 512 KB L2 Cache
Figure 2. Phase Lock Loop (PLL) Filter Requirements
0.2 dB 0 dB -0.5 dB forbidden zone
-28 dB
forbidden zone
-34 dB
DC passband
fpeak
66 MHz
fcore
high frequency band
NOTES: 1. Diagram not to scale. 2. No specifications for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
Mixing Processors
Intel only supports those processor combinations operating with the same front side bus frequency, core frequency, VID settings, and cache sizes. Not all operating systems can support multiple processors with mixed frequencies. Intel does not support or validate operation of processors with different cache sizes. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported, and is outlined in the Intel® Xeon Processor Specification Update. Additional details are provided in AP-485, the Intel Processor Identification and the CPUID Instruction application note. Unlike previous Intel® Xeon processors, the Intel Xeon processor with 512 KB L2 cache does not sample the pins IGNNE#, LINT0 / INTR, LINT1 / NMI, and A20M# to establish the core to front side bus ratio. Rather, the processor runs at its tested frequency at initial power-on. If the processor needs to run at a lower core frequency, as must be done when a higher speed processor is added to a system that contains a lower frequency processor, the system BIOS is able to effect the change in the core to front side bus ratio.
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Intel® Xeon Processor with 512 KB L2 Cache
Voltage Identification
Datasheet
Intel® Xeon Processor with 512 KB L2 Cache
Table 3. Voltage Identification Definition
Mixing Processors of Different Voltages
Mixing processors operating with different VID settings (voltages) is not supported and will not be validated by Intel.
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Intel® Xeon Processor with 512 KB L2 Cache
Reserved Or Unused Pins
Front Side Bus Signal Groups
In order to simplify the following discussion, the front side bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I / O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I / O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as
Datasheet
Intel® Xeon Processor with 512 KB L2 Cache
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous and asynchronous.
Table 4. Front Side Bus Signal Groups
Signal Group AGTL+ Common Clock Input Type Synchronous to BCLK1:0 Signals 1 BPRI#, BR3:1#3, 4, DEFER#, RESET#4, RS2:0#, RSP#, TRDY# ADS#, AP1:0#, BINIT#7, BNR#7, BPM5:0#2, BR0#2, DBSY#, DP3:0#, DRDY#, HIT#7, HITM#7, LOCK#, MCERR#7
AGTL+ Common Clock I / O
Synchronous to BCLK1:0
Signals
REQ4:0#, A16:3#6
Associated Strobe
ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
AGTL+ Source Synchronous I / O
Synchronous to assoc. strobe
A35:17#5 D15:0#, DBI0# D31:16#, DBI1# D47:32#, DBI2# D63:48#, DBI3#
AGTL+ Strobes Asynchronous GTL+ Input 4 Asynchronous GTL+ Output 4 Front Side Bus Clock TAP Input
TAP Output 2 SMBus Interface 8
Power / Other
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Intel® Xeon Processor with 512 KB L2 Cache
Asynchronous GTL+ Signals
Maximum Ratings
Table 5. Processor Absolute Maximum Ratings
Symbol TSTORAGE VCC VinAGTL+ VinGTL+ VinSMBus IVID Parameter Processor storage temperature Any processor supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS Async GTL+ buffer DC input voltage with respect to Vss SMBus buffer DC input voltage with respect to Vss Max VID pin current Min -40 -0.3 -0.1 -0.1 -0.3 Max 85 1.75 1.75 1.75 6.0 5 Unit °C V V V V mA Notes 2 1
1. This rating applies to any pin of the processor. 2. Contact Intel for storage requirements in excess of one year.
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Intel® Xeon Processor with 512 KB L2 Cache
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Section 5.1 for the processor pin listings and Section 5.2 for the signal definitions. The voltage and current specifications for all versions of the processor are detailed in Table 6. For platform planning refer to Figure 3. Notice that the graphs include Thermal Design Power (TDP) associated with the maximum current levels. The DC specifications for the AGTL+ signals are listed in Table 8. The front side bus clock signal group and the SMBus interface signal group are detailed in Table 7 and Table 11, respectively. The DC specifications for these signal groups are listed in Table 9. Table 6 through Table 11 list the processor DC specifications and are valid only while meeting specifications for case temperature (TCASE as specified in Chapter 6.0), clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter.
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Intel® Xeon Processor with 512 KB L2 Cache
Table 6. Voltage and Current Specifications
Symbol Parameter Core Freq Min Typ Max VID Unit Notes1
1.80 GHz 2.0 GHz VCC VCC for Intel Xeon processor with 512 KB L2 cache 2.20 GHz 2.40 GHz 2.60 GHz 2.80 GHz 3 GHz SMBus supply voltage
1.361 1.357 1.352 1.347 1.339 1.335 1.356 Refer to Figure 3
All freq. 1.8 GHz 2 GHz
ICC for Intel Xeon processor with 512 KB L2 cache
2.20 GHz 2.40 GHz 2.60 GHz 2.80 GHz 3 GHz
ICC for PLL power pins ICC for SMBus power supply ICC for GTLREF pins ICC Stop-Grant / Sleep ICC TCC active
All freq All freq. All freq All freq All freq
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Intel® Xeon Processor with 512 KB L2 Cache
1.51 Maximum Processor Voltage (VDC) 1.50 1.49 1.48 1.47 1.46 1.45 1.44 0 10 20 30 40 50 60 70 Processor Current (A)
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Intel® Xeon Processor with 512 KB L2 Cache
Table 7. Front Side Bus Differential BCLK Specifications
Symbol VL VH VCROSS(
Parameter Input Low Voltage Input High Voltage Absolute Crossing Point Relative Crossing Point Range of Crossing Points Overshoot Undershoot
Min -.150 0.660 0.250 0.250 + 0.5(VHavg 0.710) N / A N / A -0.300
Typ 0.000 0.710 N / A
Max N / A 0.850 0.550 0.550 +
Figure 7 7 7, 8
Notes
VCROSS(
0.5(VHavg 0.710) 0.140 VH + 0.3 N / A
VCROS
VOV VUS
NOTES:. 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 3. VHavg is the statistical average of the VH measured by the oscilloscope.
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Intel® Xeon Processor with 512 KB L2 Cache
4. Overshoot is defined as the absolute value of the maximum voltage. 5. Undershoot is defined as the absolute value of the minimum voltage. 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 9. VHavg can be measured directly using "Vtop" on Agilent scopes and "High" on Tektronix scopes. 10.VCROSS is defined as the total variation of all crossing voltages as defined in note 2.
Table 8. AGTL+ Signal Group DC Specifications
Table 9. TAP and PWRGOOD Signal Group DC Specifications
Symbol VHYS VT+ VTVOH IOL IHI ILO RON Parameter TAP Input Hysteresis TAP input low to high threshold voltage TAP input high to low threshold voltage Output High Voltage Output Low Current Pin Leakage High Pin Leakage Low Buffer On Resistance N / A N / A 8.75 Min 200 Max 300 Unit Notes 1, 2 8 5 5 V mA µA µA 3, 5 6, 7 10 9 4
NOTES:. 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. All outputs are open drain
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Intel® Xeon Processor with 512 KB L2 Cache
Table 10. Asynchronous GTL+ Signal Group DC Specifications
Symbol VIH VIL VOH IOL IHI ILO RON Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Current Pin Leakage High Pin Leakage Low Buffer On Resistance N / A N / A 7 Min 1.10 GTLREF 0.0 N / A Max VCC 0.90 GTLREF VCC 50 100 500 11 Unit V V V mA µA µA Notes1, 7 3, 5, 7 4, 6 2, 5, 7 8, 9 11 10 6
Table 11. SMBus Signal Group DC Specifications
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. These parameters are based on design characterization and are not tested. 3. All DC specifications for the SMBus signal group are measured at the processor pins. 4. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine maximum rise and fall times for SMBus signals.
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Intel® Xeon Processor with 512 KB L2 Cache
Table 12. BSEL1:0 and VID4:0 DC Specifications
Notes1 2 2 3
Symbol Ron (BSEL) Ron (VID) IHI
Parameter Buffer On Resistance Buffer On Resistance Pin Leakage Hi
Max 14.3 12.8 100
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. Leakage to Vss with pin held at 2.50V.
AGTL+ Front Side Bus Specifications
Table 13. AGTL+ Bus Voltage Definitions
Symbol GTLREF GTLREF
New Design
Parameter Bus Reference Voltage Bus Reference Voltage Termination Resistance Termination Resistance COMP Resistance
Typ 2 / 3 VCC 0.63VCC 41 50 43.2
RTT RTT New Design COMP1:0
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Intel® Xeon Processor with 512 KB L2 Cache
Table 13. AGTL+ Bus Voltage Definitions
COMP1:0 New Design COMP Resistance 49.55 50 50.45 5, 7, 8
Front Side Bus AC Specifications
Note: Care should be taken to read all notes associated with a particular timing parameter
Table 14. Front Side Bus Differential Clock Specifications
T# Parameter Front Side Bus Clock Frequency T1: BCLK1:0 Period T2: BCLK1:0 Period Stability T3: TPH BCLK1:0 Pulse High Time T4: TPL BCLK1:0 Pulse Low Time T5: BCLK1:0 Rise Time T6: BCLK1:0 Fall Time 10.00 N / A 3.94 3.94 175 175 5 5 Min Nom Max 100.0 10.20 150 6.12 6.12 700 700 Unit MHz nS pS nS nS pS pS 7 7 7 7 7 Figure Notes 1, 2 1, 3 1, 4, 5
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
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Intel® Xeon Processor with 512 KB L2 Cache
Table 15. Front Side Bus Common Clock AC Specifications
T# Parameter T10: Common Clock Output Valid Delay T11: Common Clock Input Setup Time T12: Common Clock Input Hold Time T13: RESET# Pulse Width Min 0.12 0.65 0.40 1.00 Max 1.27 N / A N / A 10.00 Unit nS nS nS mS Figure 9 9 9 12 Notes1, 2, 3 4 5 5 6, 7, 8
Table 16. Front Side Bus Source Synchronous AC Specifications (Page 1 of 2)
T# Parameter T20: Source Sync. Output Valid Delay (first data / address only) T21: TVBD Source Sync. Data Output Valid Before Data Strobe T22: TVAD Source Sync. Data Output Valid After Data Strobe T23: TVBA Source Sync. Address Output Valid Before Address Strobe T24: TVAA Source Sync. Address Output Valid After Address Strobe T25: TSUSS Source Sync. Input Setup Time T26: THSS Source Sync. Input Hold Time T27: TSUCC Source Sync. Input Setup Time to BCLK T28: TFASS First Address Strobe to Second Address Strobe Min 0.20 0.85 0.85 1.88 1.88 0.21 0.21 0.65 1 / 2 Max 1.30 Unit nS nS nS nS nS nS nS nS BCLKs Figure 10, 11 11 11 10 10 10, 11 10, 11 10, 11 10 Notes 1, 2, 3, 4, 5 1, 2, 3, 4, 5, 8 1, 2, 3, 4, 5, 8 1, 2, 3, 4, 5, 8 1, 2, 3, 4, 5, 9 1, 2, 3, 4, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 7 1, 2, 3, 4, 10, 14
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Intel® Xeon Processor with 512 KB L2 Cache
Table 16. Front Side Bus Source Synchronous AC Specifications (Page 2 of 2)
Table 17. Miscellaneous Signals+ AC Specifications
T# Parameter T35: Async GTL+ input pulse width T36: PWRGOOD to RESET# de-assertion time T37: PWRGOOD inactive pulse width T38: PROCHOT# pulse width T39: THERMTRIP# to Vcc Removal Min 2 1 10 500 0.5 Max N / A 10 N / A Unit BCLKs mS BCLKs µS S 13 13 15 16 Figure Notes 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4, 5 1, 2, 3, 4, 6
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage (VCROSS). All Asynchronous GTL+ signal timings are referenced at GTLREF. 3. These signals may be driven asynchronously. 4. Refer to Section 7.2 for additional timing requirements for entering and leaving low power states. 5. Refer to the PWRGOOD signal definition in Section 5.2 for more detail information on behavior of the signal. 6. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the assertion of PROCHOT# for the processor to complete current instruction execution.
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Intel® Xeon Processor with 512 KB L2 Cache
Table 18. Front Side Bus AC Specifications (Reset Conditions)
T# Parameter T45: Reset Configuration Signals (A31:3#, BR3:0#, INIT#, SMI#) Setup Time T46: Reset Configuration Signals (A31:3#, BR3:0#, INIT#, SMI#) Hold Time 1. Before the de-assertion of RESET# 2. After the clock that de-asserts RESET#. Min 4 2 20 Max Unit BCLKs BCLKs Figure 12 12 Notes 1 2
Table 19. TAP Signal Group AC Specifications
T# Parameter T55: TCK Period T56: TCK Rise Time T57: TCK Fall Time T58: TMS, TDI Rise Time T59: TMS, TDI Fall Time T61: TDI, TMS Setup Time T62: TDI, TMS Hold Time T63: TDO Clock to Output Delay T64: TRST# Assert Time 0 3.0 0.5 2.0 3.5 Min 60.0 9.5 9.5 8.5 8.5 Max Unit nS nS nS nS nS nS nS nS TTCK Figure 6 6 6 6 6 14 14 14 15 4 4 4 4 5, 7 5, 7 6 8 Notes 1, 2, 3, 9
Table 20. SMBus Signal Group AC Specifications (Page 1 of 2)
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Intel® Xeon Processor with 512 KB L2 Cache
Table 20. SMBus Signal Group AC Specifications (Page 2 of 2)
T# Parameter T79: Bus Free Time T80: Hold Time after Repeated Start Condition T81: Repeated Start Condition Setup Time T82: Stop Condition Setup Time Min 4.7 4.0 4.7 4.0 Max N / A N / A N / A N / A Unit µS µS µS µS Figure 17 17 17 17 Notes 1, 2, 3, 4, 6 1, 2, 3 1, 2, 3 1, 2, 3
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 14 through Table 20.
Note:
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Figure 5. Electrical Test Circuit
Figure 6. TCK Clock Waveform
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Figure 7. Differential Clock Waveform
Tph Overshoot BCLK1 VH Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tpl Tp
Figure 8. Differential Clock Crosspoint Specification
Crosspoint Specification
Crossing Point (mV) Crossing Point (V)
550 mV 550 + 0.5 (VHavg - 710)
250 + 0.5 (VHavg - 710)
250 mV
VHavg (V) Vhavg (mV)
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Figure 9. Front Side Bus Common Clock Valid Delay Timing Waveform
T0 BCLK1 BCLK0
Common Clock Signal (@ driver) Common Clock Signal (@ receiver)
valid TQ valid TR
valid
Figure 10. Front Side Bus Source Synchronous 2X (Address) Timing Waveform
BCLK1 BCLK0 ADSTB# (@ driver)
TP TR TH valid TS TJ TH valid TJ
A# (@ driver)
ADSTB# (@ receiver)
A# (@ receiver)
valid TN TM
valid
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Figure 11. Front Side Bus Source Synchronous 4X (Data) Timing Waveform
T0 BCLK1 BCLK0 DSTBp# (@ driver)
DSTBn# (@ driver)
D# (@ driver)
DSTBp# (@ receiver)
DSTBn# (@ receiver)
D# (@ receiver)
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Intel® Xeon Processor with 512 KB L2 Cache
Figure 12. Front Side Bus Reset and Configuration Timing Waveform
BLCK Tu Tt RESET# Tv
Tx Configuration (A31:3#, BR0#, SMI#, INIT#) Safe Valid
Tw Configuration (A31:3#, BR0#, SMI#, INIT#) Valid
Figure 13. Power-On Reset and Configuration Timing Waveform
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Figure 14. TAP Valid Delay Timing Waveform
V TCK Tx Signal Ts Th
V Valid
Figure 15. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform
Figure 16. THERMTRIP# to VCC Timing
THERMTRIP# Power Down Sequence
THERMTRIP#
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Intel® Xeon Processor with 512 KB L2 Cache
Figure 17. SMBus Timing Waveform
HD DAT
SU STO
Data t BUF S START S START
P STOP
Figure 18. SMBus Valid Delay Timing Waveform
DATA OUTPUT
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Intel® Xeon Processor with 512 KB L2 Cache
Power Up
PWRGD PWRGOOD
OUTEN
Processor
Power Supply
3.3 VDC
Power Down
PWROK
OUTEN
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Intel® Xeon Processor with 512 KB L2 Cache
Front Side Bus Signal Quality Specifications
This section documents signal quality metrics used to derive topology and routing guidelines through simulation. All specifications are made at the processor core (pad measurements). Source synchronous data transfer requires the clean reception of data signals and their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines. Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and undershoot can degrade timing due to the build up of inter-symbol interference (ISI) effects. For these reasons, it is crucial that the designer assure acceptable signal quality across all systematic variations encountered in volume manufacturing. Specifications for signal quality are for measurements at the processor core only and are only observable through simulation. The same is true for all front side bus AC timing specifications in Section 2.13. Therefore, proper simulation of the processor front side bus is the only means to verify proper timing and signal quality metrics.
Front Side Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines
Table 21 describes the signal quality specifications at the processor pads for the processor front side bus clock (BCLK) signals. Figure 20 describes the signal quality waveform for the front side bus clock at the processor pads.
Table 21. BCLK Signal Quality Specifications
Parameter Min Max Unit Figure Notes
BCLK1:0 Overshoot BCLK1:0 Undershoot BCLK1:0 Ringback Margin BCLK1:0 Threshold Region
0.30 0.30 N / A 0.10
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value.
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Figure 20. BCLK1:0 Signal Integrity Waveform
Overshoot BCLK1 VH Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot
Front Side Bus Signal Quality Specifications and Measurement Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are available in the appropriate platform design guidelines. Table 22 provides the signal quality specifications for all processor signals for use in simulating signal quality at the processor pads. Maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in Table 24 through Table 27. Figure 21 shows the front side bus ringback tolerance for low-to-high transitions and Figure 22 shows ringback tolerance for high-to-low transitions.
Table 22. Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers
Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure Notes
AGTL+, Asynch GTL+ AGTL+, Asynch GTL+
GTLREF + 0.100GTLREF GTLREF - 0.100GTLREF
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Table 23. Ringback Specifications for TAP Buffers
Signal Group Maximum Ringback (with Input Diodes Present) Threshold Notes
Transition
Figure
TAP and PWRGOO D TAP and PWRGOO D
VT+(max) TO VT-(max)
VT+(max)
VT-(min) TO VT+(min)
VT-(min)
NOTES: 1. All signal integrity specifications are measured at the processor core (pads). 2. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 3. Specifications are for the edge rate of 0.3 - 4.0 V / nS. 4. All values specified by design characterization. 5. Please see section 3.3 for maximum allowable overshoot.
Figure 21. Low-to-High Front Side Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers
Noise Margin
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Figure 22. High-to-Low Front Side Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers
Noise Margin
Figure 23. Low-to-High Front Side Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers
Threshold Region to switch receiver to a logic 1.
Vt+ (max) Vt+ (min) 0.5 Vcc Vt- (max)
Allowable Ringback
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Figure 24. High-to-Low Front Side Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers
Allowable Ringback
Vt+ (min) 0.5 Vcc Vt- (max) Vt- (min)
Threshold Region to switch receiver to a logic 0.
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Front Side Bus Signal Quality Specifications and Measurement Guidelines
Overshoot / Undershoot Guidelines
Overshoot / Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference level (VSS). It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently. Overshoot / undershoot magnitude levels must observe the absolute maximum specifications listed in Table 24 through Table 27. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse duration. Provided that the magnitude of the overshoot / undershoot is within the absolute maximum specifications, the pulse magnitude, duration and activity factor must all be used to determine if the overshoot / undershoot pulse is within specifications.
Overshoot / Undershoot Pulse Duration
Pulse duration describes the total time an overshoot / undershoot event exceeds the overshoot / undershoot reference voltage (VCC). The total time could encompass several oscillations above the reference voltage. Multiple overshoot / undershoot pulses within a single overshoot / undershoot event may need to be measured to determine the total pulse duration. Note 1: Oscillations below the reference voltage can not be subtracted from the total overshoot / undershoot pulse duration.
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Activity Factor
NOTE: 1. Activity factor for common clock AGTL+ signals is referenced to BCLK1:0 frequency. 2. Activity factor for source synchronous (2x) signals is referenced to ADSTB1:0#. 3. Activity factor for source synchronous (4x) signals is referenced to DSTBP3:0#and DSTBN3:0#.
Reading Overshoot / Undershoot Specification Tables
The processor overshoot / undershoot specification is not a simple single value. Instead, many factors are needed to determine what the overshoot / undershoot specification is. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot and the activity factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1. Determine the signal group that particular signal falls into. For AGTL+ signals operating in the 4X source synchronous domain, Table 24 should be used. For AGTL+ signals operating in the 2X source synchronous domain, Table 25 should be used. If the signal is an AGTL+ signal operating in the common clock domain, Table 26 should be used. Finally, for all other signals residing in the 33 MHz domain (asynchronous GTL+, TAP, etc.), Table 27 should be used. 2. Determine the magnitude of the overshoot or the undershoot (relative to VSS). 3. Determine the activity factor (how often does this overshoot occurs). 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed. 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive.
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Determining if a System Meets the Overshoot / Undershoot Specifications
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Table 24. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot / Undershoot Tolerance
NOTES: 1. These specifications are measured at the processor pad. 2. Assumes a BCLK period of 10 nS. 3. AF is referenced to associated source synchronous strobes.
Table 25. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot / Undershoot Tolerance
NOTES: 1. These specifications are measured at the processor pad. 2. Assumes a BCLK period of 10 ns. 3. AF is referenced to associated source synchronous strobes.
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Table 26. Common Clock (100 MHz) AGTL+ Signal Group Overshoot / Undershoot Tolerance
NOTES: 1. These specifications are measured at the processor pad. 2. BCLK period is 10 nS. 3. WIRED OR processor signals can tolerate upto 1 V of overshoot / undershoot. 4. AF is referenced to BCLK1:0.
Table 27. Asynchronous GTL+, PWRGOOD, and TAP Signal Groups Overshoot / Undershoot Tolerance
NOTES: 1. These specifications are measured at the processor pad.