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HX3000 FAMILY Fabricated Honeywell's Radiation Hardened 0.30


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HIGH PERFORMANCE (SOI-V) GATE ARRAYS
HX3000
FAMILY
Fabricated Honeywell's Radiation Hardened 0.30µm Leff RICMOS Silicon Insulator (SOI-V) process Array Sizes 1.0M Usable Gates 3.3V 2.5V Core Operation Mixed Voltage Power Supply (2.5V, 3.3V) CMOS, PCI, Schmitt Trigger, LVDS, Single- Multi-Port Custom SRAM Drop-In Capability Supports Chip Level Power Down Cold Sparing On-Chip Analog Phase Locked Loop (PLL) Maximum Clock Rates >250 Total Dose Hardness 3x10 rad(Si) 1x10 rad(Si) Option Available Soft Error Rate 1x10 Errors/Bit-Day Latchup Ultra Power 0.14 µW/Gate/MHz (3.3V) 0.08 µW/Gate/MHz (2.5V)
GENERAL DESCRIPTION
HX3000 gate array performance oriented sea-of-transistor array, fabricated Honeywell's Silicon Insulator (SOI-V) process. RICMOS Very high density achieved using fully planarized 4-layer metal process, providing million usable gates. high density performance characteristics SOI-V process enable device operation beyond over full military temperature range, even after exposure ionizing radiation. Flip-flops available with Soft Error Rate (SER) less than 1x10 Errors/Bit-Day Adams worst case environment. Each HX3000 design based proven Radiation Insensitive CMOS (RICMOS) ASIC Library logic elements, configurable RAMs, selectable pads. gate arrays feature skew clock distribution. This family available with Honeywell's high reliability screening procedures consistent with Class requirements. qualification anticipated. Designers choose from wide variety types. Buffer options include multiple drive strengths, three-state capability, pull-up/pulldown resistors. LVDS buffers also supported. volt tolerant provides interface legacy components.
HX3000 product family supports dual voltage I/O. designer flexibility specify either voltage supply each site. Each HX3000 array features on-chip Phase Locked Loops (PLLs) clock deskewing frequency multiplication. requires external components.
Solid State Electronics Center 12001 State Highway Plymouth, (800) 323-8295 http://www.ssec.honeywell.com
HX3000
trin X303G 249K 240K X306G 473K 440K X311G 880K 800K X314G
it-d it-d
Contact Honeywell additional options
HX3000 family special feature allow chip level power down mode which associated buses connected chip remain active. high impedance off-state buffer feature allows users power down portions their system high reliability cold sparing. HX3000 family provides options configurable single multi-port SRAMs. allow customers familiar tools libraries existing designs Honeywell library components. Timing-driven placement, clock-tree synthesis, placement-based optimization also supported fast design cycles. variety packaging options including QFP, PGA, Known-GoodDie (KGD) available. Honeywell leading role development application space qualified multichip modules last decades. HX3000 family gate arrays right choice your high reliability space applications demanding high density, high speed power. higher logic density with further power optimization, Honeywell's HX3000 (SOI-V) Standard Cell Library data sheet. learn more about Honeywell's variety space components, call 1-800-323-8295.
ASIC designers need have prior experience radiation hardening. Honeywell's Design HX3000 libraries provide necessary guidance achieve first pass design success. Design supports industry standard platforms including those offered Mentor Graphics, Synopsys Cadence. Design options includes VHDL Verilog. Honeywell perform design translations HX3000 arrays from other platforms ASIC vendors. synthesis capabilities
learn more about Honeywell Solid State Electronics Center, visit site http://www.ssec.honeywell.com
Honeywell reserves right make changes products technology herein improve reliability, function design. Honeywell does assume liability arising application product circuit described herein: neither does convey license under patent rights rights others. Rev. 2/02

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