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Data Compression Processor
DS-0002-01, 2003, Hi/fn Inc. rights reserved. 2/03 part this publication reproduced, transmitted, transcribed, stored retrieval system, translated into language form means without written permission Hi/fn, Inc. ("Hifn") Licensing Government Hifn software ("Licensed Programs") described this document furnished under license used copied only accordance with terms such license with inclusion this copyright notice. Distribution this document copies thereof ability transfer title ownership this document's contents subject terms such license. Such Licensed Programs their documentation have been developed private expense part such Licensed Programs public domain. Use, duplication, disclosure, acquisition U.S. Government such Licensed Programs subject terms definitions their applicable license. Disclaimer Hifn reserves right make changes products, including contents this document, discontinue product service without notice. Hifn advises customers obtain latest version relevant information verify, before placing orders, that information being relied upon current. Every effort been made keep information this document current accurate date this document's publication revision. Hifn warrants performance products specifications applicable time sale accordance with Hifn's standard warranty warranty provisions specified applicable license. Testing other quality control techniques utilized extent Hifn deems necessary support such warranty. Specific testing parameters, with exception those mandated government requirements, each product necessarily performed. Certain applications using Hifn products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). Hifn products designed, intended, authorized, warranted suitable life saving, life support applications, devices systems other critical applications. Inclusion Hifn products such critical applications understood fully risk customer. Questions concerning potential risk applications should directed Hifn through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. "Typical" parameters vary different applications. operating parameters, including "Typicals," should validated each customer application customer's technical experts. Hifn does warrant that products free from infringement patents, copyrights other proprietary rights third parties. event shall Hifn liable special, incidental consequential damages arising from infringement alleged infringement patents, copyrights other third party intellectual property rights. this product stateful compression protocols (for example, multi-history applications) with certain configurations require license from Motorola. such cases, license agreement right Motorola patents obtained through Hifn directly from Motorola. Patents include more following United States patents: 4,701,745; 5,003,307; 5,016,009; 5,126,739; 5,146,221; 5,414,425; 5,463,390; 5,506,580; 5,5532,694. Other patents pending. Trademarks Hi/fn®, MeterFlow®, MeterWorks registered trademarks Hi/fn, Inc. Hifnand Hifn logo trademarks Hi/fn, Inc. other trademarks trade names property their respective holders. Exporting This product only exported from United States accordance with applicable Export Administration Regulations. Diversion contrary United States laws prohibited.
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Contents
List Figures List Table Preface
About This Document Audience Document Conventions Customer Support Site
List Abbreviations Acronyms xiii Chapter
Overview
9600 Description 9600 Features Product Overview Detailed Block Diagram Signal Summary Register Summary
Chapter
Operation.
Records Commands. Command Record Termination 2.3.1 Command Termination. 2.3.2 Record Termination 2.3.3 Results. Compression
9600 Data Compression Processor Data Sheet, DS-0002-01
Contents
2.4.1 Compression, Step Step. Compression History Decompression 2.6.1 Decompression, Step Step Error Handling CRC/LCB Calculation. 2.8.1 CRC/LCB Algorithms 2.8.2 Protected Records Feedback Mode 2.9.1 Errors Feedback Mode 2.9.2 Feedback Mode Compression, Step Step Data Register Transfer 2.10.1 2.10.2 Programmed 2.10.3 Mixing Programmed transfers 2.10.4 Data Alignment Requirements 2.10.5 Requirements Writing Source FIFO 2.10.6 Characteristics When Reading From Destination FIFO FIFO Data Flow 2.11.1 Source FIFO Data Flow 2.11.2 Destination FIFO Data Flow FIFO Thresholds. 2.12.1 Programmed FIFOs Clock
2.10
2.11
2.12 2.13
Chapter
Register Descriptions
Register Overview. Data Command (1). 3.3.1 Commands 3.3.2 Command Fields Result (2,10) 3.4.1 Error 3.4.2 Value 3.4.3 Record Count 3.4.4 Consumed Byte Count 3.4.5 Destination Count Configuration (3). 3.5.1 Feedback Mode
9600 Data Compression Processor Data Sheet, DS-0002-01
Contents
3.5.2 Width 3.5.3 Endian 3.5.4 Reset Interrupt Enable (4,12). 3.6.1 Parity Error Interrupt Enable 3.6.2 Command Ready Interrupt Enable 3.6.3 SDREQ Interrupt Enable. 3.6.4 DDREQ Interrupt Enable 3.6.5 Command/Result Overrun Interrupt Enable 3.6.6 Data Error Interrupt Enable 3.6.7 Error Interrupt Enable Status (5,13) 3.7.1 Parity Error. 3.7.2 Command Ready 3.7.3 SDREQ 3.7.4 DDREQ 3.7.5 Command/Result Overrun 3.7.6 Data Error 3.7.7 Error 3.7.8 Command Progress 3.7.9 Result Progress 3.7.10 Byte Enable. 3.7.11 FIFO Configuration (7). 3.8.1 3.8.2 Source FIFO Threshold 3.8.3 Destination FIFO Threshold Chip (11).
Chapter
Signal Descriptions
Interface 4.1.1 System Data (D[31-0]). 4.1.2 Parity ([3-0]) 4.1.3 Address (A[3-0]) 4.1.4 Read/Write Command (R/W#) 4.1.5 Command Strobe (CS#) 4.1.6 Interrupt (IRQ#) Interface. 4.2.1 Byte Enable (B[3-0])
9600 Data Compression Processor Data Sheet, DS-0002-01
Contents
4.2.2 Ready (RDY#) 4.2.3 Command (EOC#). 4.2.4 Record (EOR#) 4.2.5 Source FIFO Request (SDREQ1#) 4.2.6 Source Acknowledge (SDACK1#). 4.2.7 Destination FIFO Request (DDREQ1#) 4.2.8 Destination Acknowledge (DDACK1#) 4.2.9 Command Ready. Miscellaneous Signals 4.3.1 Reset (RESET#) 4.3.2 Clock (CLK). 4.3.3 DIV1, DIV0
Chapter
Timing Descriptions
Interface Interface Examples 5.3.1 Timing Diagram Terminology 5.3.2 Burst Transfer Turn-Around Time Fixed-Length Burst Transfers 5.5.1 Reducing Dead Time Variable-Length Burst Transfers. Bursting with Wait States Bursting with Dummy Bytes 5.8.1 Write Transfers. 5.8.2 Read Transfers
Chapter
Specifications
Specifications Specifications 6.2.1 Reset Clock Timing Description Package Dimensions
9600 Data Compression Processor Data Sheet, DS-0002-01
List Figures
Figure System block diagram Figure Internal block diagram Figure Channel architecture Figure Detailed block diagram. Figure Compression example. Figure Compression example, fixed-length records Figure Decompression example Figure CRC/LCB calculation compression decompression. Figure calculation Feedback Mode Figure Data 16-bit mode Figure Data 32-bit mode Figure Command 32-bit mode Figure Command 16-bit mode Figure Result (2,10) 32-bit mode. Figure Result (2,10) 16-bit mode. Figure Endian 32-bit mode Figure Endian 16-bit mode Figure Four-transfer burst Figure DMA, turn around time Figure DMA, fixed length transfer Figure DMA, variable length transfer. Figure DMA, three-transfer burst with wait states Figure DMA, four-transfer burst Figure Pinout diagram Figure 100-pin PQFP package dimensions
9600 Data Compression Processor Data Sheet, DS-0002-01
List Figures
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viii
9600 Data Compression Processor Data Sheet, DS-0002-01
List Table
Table Signal summary Table Register summary Table Writing source FIFO Table Reading from destination FIFO Table Clock multiplier selection Table Clock multiplier example Table Register List Table Commands Table Byte enable Table Absolute maximum ratings Table Recommended operating conditions Table specification definition Table electrical characteristics Table Reset power-up timing Table timing Table timing Table timing Table Description, numerical order Table Description, alphabetical order
9600 Data Compression Processor Data Sheet, DS-0002-01
List Table
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9600 Data Compression Processor Data Sheet, DS-0002-01
Preface
About This Document
Welcome 9600 Data Sheet Hifn 9600 Data Compression Processor. This document assumes already familiar with chip technology terminology.
Audience
This document integrators application developers responsible familiar with software hardware architecture target system.
Document Conventions
following conventions used within this document:
Small Courier typeface indicates code, functions, variables Bold Courier typeface indicates items user types. Italic typeface indicates file names book titles.
Registers appear Bold typeface. SIGNAL names appear BOLD CAPS.
Path names written relative path //filename.
Customer Support
technical support about this product, please contact your local Hifn sales office, representative, distributor.
Site
general information about Hifn Hifn products refer
www.hifn.com
9600 Data Compression Processor Data Sheet, DS-0002-01
Preface
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9600 Data Compression Processor Data Sheet, DS-0002-01
List Abbreviations Acronyms
Term Command Compressed Data Stream Compressed Protected Record Compressed Record Data Stream Dummy Bytes Marker Definition single instruction 9600. series compressed bytes, which presumably consists more compressed records. compressed record which, when decompressed, contains last four bytes preceding bytes record. part compressed data stream ending with embedded marker that indicates end-of-record. Central Processing Unit cyclic redundancy calculation Series input output bytes. Direct Memory Access Transfers using 9600's request/acknowledge/ ready protocol. transfers send data into FIFOs; they cannot program internal registers. Data that transferred marked invalid through byte enables. token compressed record that indicates record. This allows record detected during decompression. End-of-Command condition. This indicated variety ways, including with EOC# signal record count fields specify amount data process. end-of-record condition, which indicated EOR# signal fixed-length records, Source Count field Command register. compression, marker embedded into compressed data stream indicate record. decompression, this marker detected 9600 automatically. First-In First-Out longitudinal check byte Lempel-Ziv-Stac compression Data that rounds compressed record 8-bit boundary. Unlike dummy bytes, padding consists valid data, required part compressed data stream. Phase-Locked Loop
FIFO Padding
9600 Data Compression Processor Data Sheet, AN-0002-01
xiii
List Abbreviations Acronyms
Term Programmed Data Stream protected record record Record SDRAM Definition Transfers using register access protocol. This method access registers FIFOs. Random Access Memory series uncompressed bytes record containing, last four bytes, preceding bytes record. bytes provided Host part record. series uncompressed bytes with condition indicated externally. portion data stream with definite start end. Compression decompression operate record-by-record basis. Synchronous Dynamic Random Access Memory
9600 Data Compression Processor Data Sheet, AN-0002-01
Overview
9600 Description
Hifn 9600 lossless Data Compression Processor. uses industrystandard Lempel-Ziv-Stac compression (LZS) algorithm. 9600 compress decompress data MB/sec. 9600 contains second decompressonly engine that used feedback mode optionally verify successful compression operations. second engine available general decompression operations. 9600 system interface supports both register Direct Memory Access (DMA) transfers widths bits. interface supports single-cycle transfers clock MHz. interface straightforward easy interface Hifn's compression algorithm been standardized many organizations, including ANSI (X.3.241), (122), IETF (RFC 1967, 1974), TIA/EIA (655), Frame Relay Forum (FRF.9).
*Note: achieved using Clock, clock multiple which provides Core Logic Clock. Section 2.13, more details.
9600 Features
Compress decompress MB/sec Industry-standard algorithm Optional feedback mode verify compression operation On-chip memory eliminates need external compression Random Access Memory (RAM) Processes multiple data records command High-speed, single-cycle burst interface
9600 Data Compression Processor Data Sheet, DS-0002-01
Overview.
Local Memory Controller
Controller
Storage Formatter
Storage
Figure System block diagram
Product Overview
9600 dual-channel device with single system interface. Each channel contains input output First-In First-Outs (FIFOs), compression/ decompression engine, dedicated internal compression memory, command, status, result registers. Channel performs both compression decompression; Channel performs decompression only only used verify compression operation feedback mode. Feedback mode fault-detection feature that verifies results compression engine real time. feedback mode, Channel compresses input data. Channel decompresses output Channel verifies resulting CRC. Figure shows internal block diagram 9600. Channel pair 64-byte FIFOs that buffer data from system data bus. These Source FIFOs Destination FIFOs. These FIFOs allow Channel operate full speed over bus. Channel also handshaking signal control movement data into FIFOs. 9600 system interface supports both register transfers widths bits. interface supports single-cycle bursting speed.
9600 Data Compression Processor Data Sheet, DS-0002-01
.Overview.
Channel (Compress/ Decompress)
Channel (Decompress Only)
Internal Data
Interface
System
Figure Internal block diagram Figure shows command data flow Channels. Unlike data flow, command flow buffered FIFOs. Host must wait until previous command completed before starting next command.
Data
Source FIFO
Command Register
Command
Engine
Result Code
Result Register
Dest FIFO
Internal Data
Figure Channel architecture external controller uses 9600 perform compression decompression following these steps: Command register loaded with command parameters. Source data written Source FIFO; output data read from Destination FIFO. (This step continues until source data been written output been read.) Results checked through polling interrupts verify that command completed without errors.
9600 Data Compression Processor Data Sheet, DS-0002-01
Overview.
While FIFOs flushed between commands, this little impact performance, since single command process number data records.
Detailed Block Diagram
Data
SDREQ1# SDACK1#
Source FIFO Compress/ Decompress Dest FIFO
Channel
Command
DDREQ1# DDACK1#
Result/ Status
D31-0
Source FIFO
Decompress
Dest FIFO
Common
RDY# B3-0 EOC# EOR# CMDRDY#
Data Command Result/Status Data
Registers Interface
A3-0 R/W# IRQ# P3-P0
Interface
Interface Misc. Signals
DIV1
DIV0
RESET#
Figure Detailed block diagram
9600 Data Compression Processor Data Sheet, DS-0002-01
.Overview.
Signal Summary
following table summarizes 9600 signals. complete signal description, Chapter list pins sorted number, sorted signal name Chapter Table Signal summary
Interface Common with Interface Signal Type Input Input Input Output Type Input Output* Input Output* Input Type Input Input Input Input Input Description 32-bit System Data Parity bits Register Select Read/Write Command Strobe Interrupt Request (open-collector) Description Byte Enable Ready Command Record Channel Input Request (Source FIFO) Channel Input Acknowledge Channel Output Request (Destination FIFO) Channel Output Acknowledge Description Hardware Reset (Schmitt input) Clock Input Clock Divisor Input +3.3 Volt supply Ground
D[31-0] P[3-0] A[3-0] R/W# IRQ#
CPU/Register Interface Only
Interface
Signal
B[3-0]
Common both channels
RDY# EOC# EOR# SDREQ1# SDACK1#
Channel
DDREQ1# DDACK1#
Signal
RESET#
Miscellaneous Signals
DIV1, DIV0
External pull-up/pull-down resistors these signals Phase-Lock Loop (PLL) clock multiple reset. Section 2.13.
9600 Data Compression Processor Data Sheet, DS-0002-01
Overview.
Register Summary
Table Register summary
Name Address Channel Channel Reserved Description 32-bit data register. Writing this register adds data Source FIFO. Reading removes data from Destination FIFO. 3x32-bit Command register. Contains Command word, 32-bit Source Count, 32-bit Record Count. Successive reads writes access three words sequence. 5x32-bit Result register. Contains result status word, 32-bit CRC, 32-bit Record Count, 32-bit Consumed Byte Count, 32-bit Destination Byte Count. Successive reads writes access five words sequence. 16-bit Configuration register. Sets device configuration, including Device Mode, Width, Big-Endian, Software Reset fields. 16-bit Interrupt Enable register. Allows interrupts enabled variety conditions 16-bit Status register. Reflects state each channel. Reserved future expansion. write this register. 16-bit FIFO Configuration register. Sets upper lower FIFO thresholds each channel. This controls point which each channel's logic will request cease request) data. 16-bit read-only Chip
Data
Command
Reserved
Result
Configuration Interrupt Enable Status
Reserved
Reserved
FIFO Configuration Chip
Reserved
Reserved
Chapter complete register descriptions.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation
Records
record fundamental unit compressed data stream. number records that processed single command specified record count field Command register. data stream consist series data bytes. record series data bytes terminated end-of-record (EOR) indicator. During compression, 9600 divides data stream into records, then compresses records, appends marker each record, emits records compressed output data stream. During decompression, 9600 takes compressed data stream produces series records, reconstructing original data stream.
Commands
command single 9600 instruction. command process number records. command launched when command structure written Command register. (There also Configuration register, shared both channels that contains state information that will change command-bycommand basis, such width.) command consists three 32-bit words 16-bit words) written sequence Command register. These words Command word, Source Count, Record Count. Writing last word launches command. Section description Command register fields. There three valid commands: Compress, Decompress, Passthrough. Passthrough command used mainly diagnostics. concept command specific 9600; precise parallel feature compression standard. simply processing more records with single instruction.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
2.3.1
Command Record Termination
Command Termination
asserting EOC# signal during write transfer. setting Status register before programmed data write. When number records indicated record count field been processed ignore record count set). error check enabled).
Commands terminated during compression decompression follows:
end-of-command (EOC) condition associated with specific byte data, flows through channel along with that byte. Thus, when exits Source FIFO, Source FIFO flushed goes idle. data will clocked into until command launched. When reaches Engine, updates Status Results registers goes idle. When exits Destination FIFO, 9600 asserts EOC# signal last output transfer containing valid data, dummy transfer following last data transfer. Destination FIFO then goes idle. After burst containing EOC, Destination FIFO interface disabled. Only register active between commands. Regardless source EOC, condition treated identically Channel. Whichever enabled condition asserted first will terminate command. example, asserting EOC# signal will terminate command asserted before Record Counter reaches vice versa. After each command, Result register updated, FIFOs flushed, history cleared. Section 2.10.4 details requirements data alignment, padding, dummy bytes during EOC.
2.3.2
Record Termination
Like EOC, condition associated with specific byte data, flows through channel along with that byte. Regardless source EOR, condition treated identically channel. enabled condition will record.
2.3.2.1
Compression
During compression, data stream divided into records either externally internally. External termination occurs when controller asserts EOR# signal last transfer each record dummy transfer following last valid transfer. last valid byte, determined
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
byte enables, becomes last byte record. (When using programmed mechanism transfer data, Status register needs mimic assertion EOR#.) Records also terminated internally, with data stream divided into records equal length before compression. This length Source Count, which command field. output, compressed record always padded 32-bit boundary. Full bytes padding marked invalid byte enables (that they transferred dummy bytes). 16-bit mode, this padding 32-bit boundaries cause dummy transfers. EOR# signal asserted 9600 transfer, from Destination FIFO, last byte data record.
2.3.2.2
Decompression
decompression, record termination internal, result embedded tokens compressed data stream. input, compressed data stream must consist multiple four valid bytes. 9600 assumes that padding exists after strips number bytes necessary record multiple four bytes. This operation done after dummy bytes stripped from input stream, record padded with dummy bytes instead valid bytes, Channel will strip bytes from beginning next record. This behavior true only input, only during decompression. output, Channel asserts EOR# signal dummy transfer after last word record been transferred from Destination FIFO. Before each record, initialized, Source Counter reset compression) maximum record length, Record Counter decremented, history reset clear history command set.
2.3.2.3
Alignment Padding
Section 2.10.4 details requirements data alignment, padding, dummy bytes during EOR.
2.3.3
Results
Result register valid each command. cleared beginning each command, contents undefined when command progress.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
Each command updates Results register, structure five 32-bit words with following fields:
status word. 32-bit last record processed. calculated (uncompressed) data stream. other words, calculated input stream during compression output stream during decompression. value usually little interest itself, useful debugging. Record Count This starts with Record Count given command, decrements with each record. This true even ignore record count set. This allows determine many records were processed, regardless source EOR. Consumed Byte Count This counter cleared beginning command, then updated each with number valid bytes processed command (dummy bytes counted). command doesn't EOR, partial record command counted. This counter used mostly decompression, where gives offset successfully decompressed portion compressed data stream. Destination Count This value increments with each valid destination byte produced either compression decompression. value cumulative across records command. reset beginning each command.
Results register valid when chip idle. Attempting read during command will cause Command/Result Overrun error. value returned such read undefined. Channel idle when:
command ready Channel Status register set,
EOC# been asserted 9600 during output transfer from Channel Destination FIFO. Feedback Mode, EOC# used signal that Channel idle, CMDRDY signals that Channel idle.
Compression
While both channels perform decompression, only Channel compress data. controller sends data Channel through Channel interface. Incoming data buffered Channel Source FIFO, which generates request signal (SDREQ1#) based programmable thresholds. Host controller initiates transfers Channel with SDACK1# signal inserts wait states with RDY#. Section 2.11.1 further details. Data also transferred through programmed mechanism. Section 2.11.2 further details.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
data must divided into records. This done internally, through Source Count field command, externally, with EOR# signal. Data must also divided into commands similar manner. These external internal methods ending records mixed. Figure shows command that consists five input records. Records terminated when Source Count reaches Records when EOR# asserted. channel creates five compressed records, making distinction between records that were terminated EOR# Source Count. These records then compressed varying degrees, depending their contents.
Source Count
record
record
record
record
record
Channel (Compress Mode)
EOR, EOC, Result
Figure Compression example output, markers embedded compressed output data stream. output data stream buffered Channel Destination FIFO, which generates request signal (DDREQ1#) based programmable thresholds. Host controller initiates transfers from Channel with DDACK1# signal inserts wait states with RDY#. During output transfers, EOR# EOC# become outputs. EOR# asserted when last bytes record transferred. EOC# asserted when last bytes command transferred across bus. bits Status register also follow status. Output 32-bit aligned; output record will begin with cycle, will with cycle padded with dummy bytes, necessary. Output padding guarantees that output stream will never contain bytes from different records. requirements alignment padding listed Section 2.10.4. record count field decrements with each record. example Figure after first record processed will will have counted down zero command. calculated automatically per-record basis data. compression, this input data.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
2.4.1 Compression, Step Step
steps below case where EOR# EOC# signals used instead Source Count Record Count features, shown Figure Compression only available Channel (Details register usage, signal definitions, system timing given Chapter Chapter Section 6.2.) Deassert EOR# EOC# pins. Test command ready Status register. This done through polling interrupts. (This step strictly necessary, 9600 always ready accept command after previous command's EOC.) Write three 32-bit words Command register: Command Word (0x00003000), Source Count (0), Record Count (0). this example, ignore source count ignore record count bits control word, values written Source Record Count don'tcares. These words must written, however, launch command, even though values ignored.) Start writing data Channel handshaking done entirely hardware, using Channel source control signals (SDREQ1#, SDACK1#, common signal RDY#). Assert EOR# along with transfer containing last byte each record. This does have occur last transfer burst. Start reading data from Channel destination interface (using handshaking signals DDREQ1#, DDACK1#, RDY#). This compressed data stream. Unlike input stream, don't know long this data stream going EOR# EOC# will asserted chip transfer last words each record command. input data stream, assert EOR# EOC# along with last data transfer. Again, this does have burst, data transferred after EOC# will discarded. Once output data been transferred (EOC# will asserted chip last transfer), read Result register check error status. Reading Result register optional (interrupts error conditions). also acceptable read only part five-word Result structure.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
record
record
record
record
record
Channel (Compress Mode)
EOR, EOC, Result
Figure Compression example, fixed-length records
Compression History
Compression algorithms maintain data-dependent state information. This information called compression history. compression history stored internal compression RAM. compression history always cleared between commands. retained across records within same command, cleared before each record, determined clear history Command register.
Decompression
Compressed data presented Channel undifferentiated data stream. data decompressed, record boundaries embedded data stream detected. compression, Command includes Source Count Record Count. example, setting Record Count five will terminate command after five records have been decompressed. command will also terminate number input bytes specified Source Count been consumed. data flow almost identical case compression, though decompression EOR# will ignored asserted along with source data stream. destination data stream, chip asserts EOR# EOC# dummy transfer each decompressed record command. start each output record aligned 32-bit boundary. Dummy bytes inserted between output records achieve this alignment. Section 2.10.4 details alignment padding requirements decompression.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
2.6.1 Decompression, Step Step
10,000 Source Bytes
Channel (decompress)
record
record
record
record
record
EOC, EOR, Result
Figure Decompression example
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
example Figure assumes that have chosen decompress block 10,000 compressed bytes. Deassert EOC# pin. Wait, through interrupts polling, until Status register (command ready) set. compression, this strictly necessary.) Write three 32-bit words Command register: Command (0x10001000), Source Count (10,000), Record Count (0). (With ignore word count Command Word, Record Count value will ignored, write must still take place.) Start writing data Channel This same previous example, except that EOR# should asserted. Start reading data from Channel This decompressed data stream. example don't know long will EOR# EOC# will asserted chip transfer data ends records commands. Stop sending data after you've transferred your 10,000 bytes. Alternatively, assert EOC# want stop before 10,000 bytes have been transferred. Wait until last byte decompressed data been transferred from channel (EOC# will asserted after last transfer valid data.) Read Result register, which contains data structure five 32-bit words. Reading Result optional. Reading only part five-word Result structure also acceptable. Note that command ended middle record Result register will that record incomplete record consumed byte count will also reflect value wished decompress record consumed byte count field would give offset first byte record
Error Handling
Status register contains error bits command/result overrun, data error, error. These error bits under following conditions: Command/Result Overrun: Command register written Result register read when there command progress. Data Error: Source FIFO overflowed Destination FIFO underflowed. Error: protected record with invalid detected.
enable must this test take place.
Parity Error: parity error detected P[3:0] during write Source FIFO.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
When error detected, current command terminated. other errors simply cause associated bits Status register set, and, associated interrupt enable set, IRQ# signal asserted. These error bits only cleared hardware software reset chip. software reset performed writing reset Configuration register.
CRC/LCB Calculation
Channel Data Compressed Data
Compression
Channel Channel Data
Decompression
Compressed Data
Figure CRC/LCB calculation compression decompression. Figure 9600 calculates (cyclic redundancy calculation) (longitudinal check byte) (uncompressed) data stream automatically. compression, calculates input data. decompression, calculates output data. These calculations done per-record basis. field Result register last complete record. field updated partial records.
2.8.1
CRC/LCB Algorithms
three algorithms, initial value ones (0xFFFFFFFF 32-bit CRC, 0xFFFF 16-bit CRC, 0xFF 8-bit LCB). either bits length. eight bits long. 32bit equation where current data byte. 16-bit equation exclusive-OR each byte record. That with each data byte, data XORed with partial LCB, result becomes LCB.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
addition, both CRC32 CRC16 should logically bit-wise inverted: CRC32 ~(x32 +1); CRC16 (x16 record pass through 9600 correctly (i.e., error).
2.8.2
Protected Records
9600 configured test integrity each record being processed. function this way, data being processed must formatted protected records. protected record record with CRC-32 appended end. Before records compressed, system must append CRC-32 each record. During compression, 9600 will verify integrity protected record scanning entire record, including appended CRC-32. CRC-32 protected record valid, device operation will continue. CRC-32 invalid, device will terminate record. entire protected record (including appended CRC-32) will compressed device becomes part compressed record. During decompression, protected record will decompressed, resulting original uncompressed protected record (with original appended CRC-32). entire record, including CRC-32 scanned integrity after decompression. protected record valid, device operation will continue. CRC-32 invalid, device will terminate record. described CRC/LCB Calculation section, CRC-32 will always calculated over uncompressed data record. However, testing integrity protected records configured enable Command Word. result integrity test part Result Status registers. 9600 updates Error flag only record. error will flagged command terminates before record processed. This prevents spurious errors from being reported every time command terminates middle record. When error detected record, command will terminate. reset must issued clear Error flag.
2.8.2.1
Notes Protected Records
CRC-32 calculated over entire protected record (including embedded CRC-32), result will always 0xDEBB20E3. This information useful when designing external logic used scan protected records decompressed 9600. embedded protected record part record. compressed decompressed along with rest record, 9600 treats like other data. embedded Host; 9600 neither adds data
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
stream removes from data stream. enable Command Word, four bytes must appended every record, Error will generated. example, 256-byte record 32-bit 0x1A9BFE29, appending 32-bit constant 0x1A9BFE29 record will create 260-byte protected record. When this record processed 9600, will return value 0xDEBB20E3. This value constant every protected record with valid 32-bit bytes.
Feedback Mode
Channel Data
Compression
Compressed Data
Channel
Decompression
Data
Figure calculation Feedback Mode 9600 operate with Feedback Mode enabled disabled. Feedback Mode, Channel used both compression decompression, while Channel used only verify proper operation device compression. figure above shows feedback-mode operation. Feedback Mode enabled setting feedback mode Configuration register. Feedback Mode, Channel used both compression decompression; Channel dedicated per-record checking during compression. Channel compresses records, while Channel decompresses them check their CRCs. Provided that input data consists valid protected records, this error will only occur there been some kind hardware failure. When device into Feedback Mode, Channel registers programmed automatically proper feedback operation. only Channel registers which accessed Feedback mode Result register, Interrupt Enable register, Status register. Writes other registers will ignored; reads undefined.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
Feedback Mode ties Destination FIFO Channel Source FIFO Channel Since both channels operate same speed, bandwidth same whether compression uses Feedback Mode not, Feedback Mode adds small amount latency. CMDRDY asserted when Channel command complete, informing Host system that Channel Result register ready that command started. Checking result requires that Host read both Results registers. Channel result will become ready same time Channel result. Channel takes place usual, with EOC# being asserted last valid data transfer from Destination FIFO. Channel opportunity assert EOC#, there data transfers from Channel Channel does, however, assert CMDRDY signal command. 9600 ready command until CMDRDY signal been asserted.
2.9.1
Errors Feedback Mode
9600 Feedback Mode with test enabled, record that fails test either Channel will cause command abort. error status will given Result register each channel. Channel failure indicates data corruption problem. Channel failure indicates device failure. error only asserted EOR. command ends partway through record, error generated. When test enabled, both Channels check with every record, both compression decompression. error only Result register also replicated Status register. Interrupt Enable register determines whether error will cause interrupt. error occurs Channel command will terminate Channel Channel will keep going until valid data produced Channel before error been processed. this case, EOC# will asserted first, followed CMDRDY some number cycles later. error occurs Channel command terminated immediately both channels. this case, CMDRDY asserted alone, EOC# will asserted all. Host state machine needs take this into account. error occurs both Channels same cycle, both EOC# CMDRDY asserted same time.
2.9.2
Feedback Mode Compression, Step Step
Enable Feedback Mode setting feedback mode Configuration register.
This example gives procedure compression Feedback Mode.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
desired, interrupt enable Error Channel Interrupt Enable register. This will catch device failures. This step absolutely necessary, since errors will cause command terminate, error will Status Result registers. desired, also interrupt enable Error Channel Interrupt Enable register. This will detect data corruption errors protected records. Again, interrupt necessary catch errors, because command will terminate errors. Compress data usual. When last byte output data been transferred from Channel Destination FIFO, EOC# will asserted usual, unless there been error Channel Channel result checked after desired. When Channel reached command, will assert CMDRDY. This marks true command. Test Channel errors usual, through programmed interrupts. Error special significance Feedback Mode, course, should always checked, there point operating chip Feedback Mode. Begin command. 9600 will ready command when CMDRDY asserted.
2.10 Data Register Transfer
Once command started, data transferred Channel. Input data written Source FIFO. Output read from Destination FIFO. There mechanisms transferring data: programmed DMA. provides higher performance. Both methods FIFOs identical manner. Since programmed method does EOR, EOC, byte-enable signals, there read/ write status register bits that provide same function. Writing these bits same effect asserting signals; reading them gives same information sampling signals. programmed data transfers should mixed same command. examples this document will unless explicitly stated that programmed being used.
2.10.1
most efficient 9600 through interface. interface allows data move directly between Host controller 9600 FIFOs. Channel FIFOs: Source FIFO Destination FIFO.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
Each FIFO request acknowledge signals. Thus, Channel SDREQ1#, SDACK1#, DDREQ1#, DDACK1#. request signals outputs; acknowledge signals inputs. addition FIFO-specific signals, there number shared signals: RDY# input bidirectional EOC#, EOR#, [31:0] data bus, B[3:0] byte enables. Once command issued, transfers begin. Source FIFO always empty beginning command, SDREQ1# signal will asserted immediately. Data processed written Host Source FIFO. Host initiates burst asserting SDACK# signal. SDREQ1# DDREQ1# signals controlled programmable FIFO thresholds. These thresholds determine points which signals asserted deasserted, based full empty FIFOs are. FIFO thresholds discussed Section 2.12. conditions indicated EOR# EOC# signals. EOR# EOC# transferred with data, immediately after part dummy transfer. When Host writing data, writes EOR# EOC# part last data write. When Host reads data, reads EOR# EOC# from 9600. Data sent Channel after considered part next record (see discussion data alignment requirements Section 2.10.4). data sent Channel after ignored. Data read from channel after invalid (these statements also true programmed I/O). other words, Host continue send data after EOC, there will adverse effects. This useful, example, decompression, where Host often idea exact position compressed record. Host send too-large block data, telling 9600 decompress correct number records. Leftover data will discarded automatically. consumed byte count field Result register will report number valid bytes processed during command (See Section 3.4.4 details consumed byte count.) timing covered detail Section 5.2.
2.10.1.1
Byte-Enable Signals
byte-enable signals, BE[3:0], written same time data data bus. They indicate which bytes data word valid. When writing data Source FIFO, byte-enables asserted pattern, 9600 will discard invalid (dummy) bytes process those marked valid. When reading from Destination FIFO, Host should discard bytes which byteenables asserted. Host logic must monitor byte-enables every read transfer from 9600.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
indicate command record without writing data, dummy word written Source FIFO. When this dummy word written, EOC# EOR# signals asserted, byte-enables not. This signals status without transferring data. Dummy bytes dummy transfers Source FIFO occupy space FIFO they were valid data. They discarded until they exit FIFO. Thus, design Host controller must count dummy bytes they were valid purposes setting Source FIFO thresholds. When using programmed I/O, byte-enable bits Status register must used indicate which bytes valid. This described further Section 2.12.1. When reading from Destination FIFO, byte-enable signals written 9600 along with data. first transfer every record always aligned boundary. some situations, there destination transfer with valid bytes mark EOC, record both. This would indicated transfer which valid data bytes, which EOC# EOR# signals asserted. Since word valid data, BE[3:0] signals bits Status register programmed I/O) would deasserted. Section detailed description interface protocol.
2.10.2
Programmed
Programmed conventional interface using R/W# signals control, A[3:0] register addressing, D[31:0]bus data transfers. Section 2.10.2 detailed description programmed protocol. Programmed only mechanism reading writing registers, including Command register. chip registers inaccessible interface. Thus, chip configuration, commands, results, status transferred exclusively through programmed I/O. basic operation programmed consists reading writing registers. Most registers either bits long. Command Results structures contain multiple 32-bit words, which read written sequentially through consecutive accesses. example, Command structure consists three 32bit words 16-bit words 16-bit mode). 32-bit mode, command launched writing three words Command register: first Command Word, then Source Count, then Record Count. command launched when third word written. Result structure five 32-bit words long 16-bit words long 16-bit mode), read through five ten) reads Result register. Command also read back. Programmed used alternative transferring data into 9600. Writes Data register send data into Source FIFO. Reads from Data register return data from Destination FIFO.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
Because crucial state information carried control signals, these signals must emulated when using programmed place DMA. signals that must emulated are: B[3-0], DDREQ1#, EOC#, EOR#, SDREQ1#. Bits emulate these signals exist Status register. These signals used indicate valid bytes, EORs commands, provide FIFO handshaking. writes, Status register first written with correct handshaking bits, then Data register written. However, transfer matches chip default conditions (all bytes valid, EOC, EOR), Status register does have written. reads, Status register read, then Data register read. Status register must examined before every data read note status 9600. Otherwise, errors, status, FIFO flags will ignored. Section 2.12.1 example programmed transfers.
2.10.3
Mixing Programmed transfers
input output data streams should provided either programmed DMA. should mixed same command. Other than optionally providing input output data stream, only programmed that should take place during command reading Status register. other register access should take place only when chip idle (after reset EOC).
2.10.4
Data Alignment Requirements
9600 different alignment requirements depending what operation being performed. When using EOR# EOC# signals indicate EOC, there problem determining which bytes transfer last byte. This issue solved either requiring particular data alignment (such requiring that every record 32-bit aligned) using byte-enables mark bytes past invalid. output byte-enables used indicate last byte. input, there cases where system cannot mark last input byte transfer:
During compression with fixed-length records, where 9600, Host, dividing data stream into records using source count field, During decompression, where Host does know exactly where EORs data stream.
chip handles these cases. following tables show alignment padding requirements different circumstances:
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
2.10.5 Requirements Writing Source FIFO
Data have alignment when sent Source FIFO. Compression Dummy bytes (that bytes marked invalid byte-enable Decompression signals) sent point record. (But 'Decompression' under 'EOR Alignment,' below.) EOR# input signal used, last transfer record must contain bytes from different records. Thus, last transfer should padded with dummy bytes, necessary, round transfer full width.If EOR# input signal used (that source count field used divide data into records), data stream continuous: last byte record first byte next record same transfer. number valid bytes record must multiple four bytes. enforce this, Source FIFO discards bytes after EOR. This happens after dummy bytes stripped from input. Thus, record must padded with bytes data after EOR. These bytes must valid bytes. practice, this generally achieved sending 32-bit-aligned records 9600 using byte enables when writing Source FIFO. EOR# signal ignored input during decompression.
Table Writing source FIFO
Start Record Alignment
Compression
Alignment
Decompression
Start Command Alignment Alignment
Compression restrictions. Decompression Compression restrictions. Data after discarded. Decompression
EOR/EOC Location
EOR# EOC# asserted Host during either Compression write containing last byte record/command, Decompression dummy transfer that follows write last valid data transfer.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
2.10.6 Characteristics When Reading From Destination FIFO
9600 never produces dummy bytes except command. bytes between start record valid. Table Reading from destination FIFO
Start Record Characteristics Records 32-bit aligned output. They always start Compression transfer. Thus, transfer never contains bytes from Decompression records. achieve 32-bit alignment output, dummy bytes added after last byte record round 32-bit boundary. Host does conclude burst immediately, dummy transfers will sent rest burst.
Characteristics: Start Command Characteristics
Compression
Compression Commands 32-bit aligned output. They always start Decompression transfer. achieve 32-bit alignment output, dummy bytes added after last byte command round 32Compression boundary. Host does conclude burst Decompression immediately, dummy transfers will sent rest burst. Compression Decompression
Characteristics
EOR# EOC# attached transfer containing
last valid data byte
EOR/EOC Location
EOR# EOC# part dummy transfer that occurs after chip writes that last valid data.
2.11 FIFO Data Flow
2.11.1 Source FIFO Data Flow
Each Channel Source FIFO. Source FIFO obtains source data from interface using either programmed transfers. Source FIFO requests data there active command there room Source FIFO additional data. Source FIFO will stop requesting data when there more room, when command terminates. thresholds which FIFO starts stops requesting data programmable. bytes Source FIFO counted when determining thresholds, even dummy bytes (marked invalid byte-enable signals). example, three 32-bit data transfers count bytes, regardless many bytes were valid.
2.11.2
Destination FIFO Data Flow
Each channel also Destination FIFO. Destination FIFO delivers destination data interface using either programmed transfers.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
Destination FIFO requests output when there enough data available. request will remain active until there little data remaining. These thresholds programmable. After last byte data from record command) entered Destination FIFO, Destination FIFO requests data transfers, regardless FIFO thresholds, until last byte record command) exits FIFO. EOR# EOC# signal asserted middle data burst, burst will continue with dummy bytes until burst concluded. EOR# EOC# signals independent another. EOC# asserted without EOR#, last record incomplete.
2.12 FIFO Thresholds
There four FIFO Threshold values each engine: Source FIFO Upper Threshold, Source FIFO Lower Threshold, Destination FIFO Upper Threshold, Destination FIFO Lower Threshold. four these values programmed user into FIFO Configuration register. upper threshold values determine when data transfers will requested. lower threshold values when request will deasserted. SDREQ1# signal (and sdreq Status register) will asserted when number bytes empty space Source FIFO greater than source FIFO upper threshold. SDREQ1# signal (and sdreq Status register) will deasserted when number bytes empty space Source FIFO less than equal Source FIFO Lower Threshold. DDREQ1# signal (and ddreq Status register) will asserted when number bytes Destination FIFO greater than destination FIFO upper threshold. DDREQ1# signal (and ddreq Status register) will deasserted when number bytes Destination FIFO less than equal destination FIFO lower threshold. thresholds below 16-bit bus, 32-bit bus, 9600 will ignore settings values respectively. (These recommended values, exist testing purposes.) FIFO thresholds allow flexibility data written Source FIFO read from Destination FIFO. example, some controllers operate fixed-length burst mode, where each operation involves fixed number transfers. Setting lower FIFO thresholds properly will guarantee minimum number bytes that will able transferred burst. this done, DREQ# signals need only checked beginning each burst.
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
example, burst size bytes, setting Source FIFO upper threshold will guarantee that least bytes empty space Source FIFO when SDREQ1# asserted. Setting Spource FIFO lower threshold will guarantee that SDREQ1# signal will deasserted when number bytes empty space Source FIFO less. Similarly, setting Destination FIFO upper threshold will guarantee that least bytes data Destination FIFO before DDREQ1# will asserted. Setting Destination FIFO lower threshold will ensure that DDREQ1# signal will deasserted there less bytes Destination FIFO. FIFO Lower Thresholds also used offset effects controllers that cannot respond immediately deassertion DREQ#. controller will continue transfer several bytes data after DREQ# signal been deasserted, then setting FIFO Lower Threshold correctly will guarantee that there will room FIFOs these additional bytes. example, setting Source FIFO lower Threshold seven will guarantee that Source FIFO will able accept additional 32-bit transfers after SDREQ1# deasserted. Similarly, setting Destination FIFO lower threshold seven will guarantee that Destination FIFO will able provide additional 32-bit transfers after DDREQ1# signal deasserted. With fixed-length bursts, FIFO Lower Threshold used give controller advance warning FIFO readiness accept burst after current burst. example, controller with 32-bit width burst size bytes could sample DREQ# cycle early FIFO Lower Threshold were rather than This reduce dead time between backto-back bursts.
2.12.1
Programmed FIFOs
Data passed into Channels using programmed access rather than must still take FIFOs into consideration. Overflowing Source FIFO underflowing Destination FIFO will cause fatal error. following pseudocode demonstrates FIFO handshaking emulated software. shows transfer single record from FIFOs, assumes that command already been issued. performance were issue, would write code transfer multiple records instead just one.)
repeat Status Read_Status_Register; (Status[SDREQ] (input_data then Write_Status(input_data); byte enables (all four are-enabled except when there fewer than four input bytes remaining (input_data possibly first data transfer). last transfer record (input_data last transfer command.*/ Write_Data[input_data]; Send data word bits except last transfer)*/ input_data input_data endif (Status[DDREQ]) then
9600 Data Compression Processor Data Sheet, DS-0002-01
Operation.
Read_Data; 32-bit word from FIFO, discard bytes which byte enables aren't asserted, store valid bytes output buffer. Also test Status word EOC. endif until (Status[EOR] Status[EOC]); errors cause EOC, bases covered
2.13 Clock
9600 internal logic based single clock input, CLK. internal locks system provides frequency-multiplied clock core logic. Because must lock after power-up, chip should accessed some time (see Specifications Chapter frequency multiple controlled pull-up pull-down resistors four pins, which sampled after each hardware reset. Their values shown below: Table Clock multiplier selection
SDREQ1# DDREQ1# DIV1 DIV0 Frequency Multiple Reserved
other combinations
table indicates pull-up resistor. indicates pull-down. SDREQ1# DDREQ1# signals tri-stated reset avoid contention with pull-ups pull-downs Because pull-downs will look Host SDREQ1# DDREQ1# being asserted, Host should sample these outputs three cycles after RESET# deasserted. Section 6.2.1. Clock Multiplier Examples Table Clock multiplier example
Clock (CLK) Logic Clock Clock Multiple
9600 Data Compression Processor Data Sheet, DS-0002-01
Register Descriptions
Register Overview
device register list shown below. Each Channel registers, excluding shared Configuration Chip registers. Some Channel registers inaccessible when device Feedback Mode. These registers shown with bolded text Table Many registers bits wide. device operating 16-bit mode, accessing these registers will require transfers. first transfer writes lower bits register, second writes upper bits. Only Data register effected big-endian Configuration register. register descriptions that follow, some bits will marked "Reserved." Reserved bits must written zeros ignored when read. Table Register List
Name Address Channel (reserved) (reserved) Channel (reserved) (reserved)
Data Command Result Configuration Interrupt Enable Status
Reserved
FIFO Configuration Chip
9600 Data Compression Processor Data Sheet, DS-0002-01
Register. Descriptions
Data
Data (15-0)
Figure Data 16-bit mode
Data (31-0)
Figure Data 32-bit mode Register Data register Channel This register read written. write Data Register writes data Source FIFO. read reads data from Destination FIFO. Data register provides access FIFOs through programmed mechanism. mechanism more efficient. Transfers from Data register only take place under same conditions that transfer take place. That state FIFO must taken into consideration. Status register SDREQ DDREQ bits reflect state SDREQ1# DDREQ1# signals. Data register should only read when DDREQ set, should only written when sdreq set. these conditions observed, Channel terminate command when attempt made write full FIFO read from empty one. data error Status register will indicate error. This fatal error which requires hardware software reset before command processed. programmed transfers, behavior EOC#, EOR#, B[3-0] signals must duplicated software. This done through read/write bits Status register. When setting these bits, Status register written first, then Data register. Section 2.10.2 Section 2.12.1 further details. example, signal programmed compression, Host would Status register, then write final data word record Data register.
9600 Data Compression Processor Data Sheet, DS-0002-01
.Register.Descriptions.
Write Order
Command
Clear History Enable Reserved Type Reserved Ignore Source Count Ignore Record Count
Command
Reserved
Reserved
Reserved
Source Count (31- Record Count (31-
Figure Command 32-bit mode
Write Order
Command Clear History Reserved Ignore Source Count Ignore Record Count Reserved Enable Reserved Source Count (31-16) Source Count (15-0) Record Count (31-16) Record Count (15-0)
Reserved Type Reserved
Figure Command 16-bit mode Register Command register Channel Command register read written. specifies command executed sets command parameters. Three 32-bit write operations (six 16-bit mode) required launch command. writes must take place. command progress Status register used verify synchronization write operations. This will after first write Command register, cleared after last write. command issued when cammand ready Status register set. command also read CPU. This would generally done except testing purposes. Reading Command register similar writing command progress Status register must clear before read transfer initiated. entire Command (three 32-bit words) must read.
9600 Data Compression Processor Data Sheet, DS-0002-01
Register. Descriptions
3.3.1 Commands
4-bit command field specifies function executed. These listed below: Table Commands
Command Compress Decompress Passthrough Reserved Command field 3-15
Compress: This channel will compress data. Section details Compress command operates. Decompress: channel will decompress data. Section details Decompress command operates. Passthrough: This channel passes data unmodified from input output. Compression history affected. This command mostly used diagnostics.
3.3.2
Command Fields
Clear History: This significant both compression decompression, determines whether compression history will cleared between records same command. History always cleared before first record command, regardless setting this bit. compression, compression history only cleared before first record command, this compression, compression history cleared between records this decompression, this tells Engine whether clear history between records. set, history cleared. Otherwise, not. Decompression requires that state clear history match compression mode used compress data. Ignore Source Count: This significant Compress command. this set, value source count command field ignored. source count significant. Ignore Record Count: This significant both Compress Decompress commands. set, record count command field ignored. record count field significant. Enable: This significant compress decompress commands, only 32-bit mode. this will verified against constant value protected record (0xDEBB20E3). this will checked. result test written error
9600 Data Compression Processor Data Sheet, DS-0002-01
.Register.Descriptions.
bits Status Results registers. Setting this enables test, requires source data protected records, causes errors become fatal errors. Section 2.8.2. Type: Selects checksum algorithm current command. This 2-bit field decoded follows:
Value Check Type 32-bit 16-bit 8-bit Reserved
Section discussion CRC/LCB generation. Source Count: This field initial value used Source Counter. Source Counter used only Compress command. Compress Command, Source Count specifies size each record compressed. Each time Source Count reaches (unless ignore source count Command register marker will appended compression operation will begin next record. Source Count record length bytes compression. Record Count: This field initial value used Record Counter. Record Count specifies number records that will compressed decompressed during command. When Record Count reaches (unless ignore record count Command register command will terminate. Record Count records will processed before command terminates.
Write Order Error
Result (2,10)
Reserved Value (31- Record Count (31- Consumed Byte Count (31- Dest Count (31-
Figure Result (2,10) 32-bit mode
9600 Data Compression Processor Data Sheet, DS-0002-01
Register. Descriptions
Write Order
Error
Reserved Reserved Value (31-16) Value (15-0) Record Count (31-16) Record Count (15-0) Consumed Byte Count (31-16) Consumed Byte Count (15-0) Dest Count (31-16) Dest Count (15-0)
Figure Result (2,10) 16-bit mode Register Result register Channel Register Result register Channel This read-only register reports result completed command. Reading Result register optional. Five read operations (ten 16-bit mode) required properly read result. result progress Status register used verify synchronization read operations. reads must take place before result progress will cleared. This normally effect operation chip, however, will cleared event when command launched. Results register only updated every command. These registers affected hardware software reset; contents will unknown power will only known after command passed through 9600. This applies blocks result register: Error, Value Record Count Consumed Byte Count Dest Count
3.4.1
Error
This significant Compress Decompress commands, only error Command register 32-bit algorithm selected. used check integrity protected records.
9600 Data Compression Processor Data Sheet, DS-0002-01
.Register.Descriptions.
this value field correct, test enabled. this value field failed test. Unless record valid protected record, will fail test. When test enabled, error will cause current command terminate. Section details when this will set.
3.4.2
Value
This field significant Compress Decompress commands. This field represents calculated 32-bit CRC, 16-bit 8-bit value most recently completed record. algorithm selected Command word. These calculations performed data (input compression, output decompression). Values aligned least-significant bit, 16-bit occupies bits 15:0, while longitudinal check byte occupies bits 7:0. This field will contain results selected checksum algorithm every operation, regardless state enable bit. they generated, protected records always have 32-bit value 0xDEBB20E3.
3.4.3
Record Count
This field significant commands. represents number records remaining processed command. value Record Count result field calculated follows: internal record counter initialized less than Record Count Command field. internal counter decremented with each record processed. When command terminates, value internal counter written into Record Count Result field. command terminated because number records specified Command word been processed successfully, this field will
3.4.4
Consumed Byte Count
This field significant commands. contains number input bytes processed Channel since start command. Neither dummy bytes partial records command counted. primary Consumed Byte Count identify point compressed data stream which decompression recommenced. example, issued command decompress records, Consumed Byte Count would contain offset compressed data stream from which decompression eleventh record could begin with command. Consumed Byte Count cleared beginning command. temporary register input Engine (below Source FIFO) counts valid bytes input data stream. Valid bytes those bytes whose address enables were asserted. each EOR, count temporary register added Consumed Byte Count. Since Consumed Byte Count only updated EOR, partial records command contribute count.
9600 Data Compression Processor Data Sheet, DS-0002-01
Register. Descriptions
3.4.5 Destination Count
This field significant commands. Destination Count starts each command increments with each destination byte produced Channel. Thus, Destination Count gives number valid output bytes produced command.
Configuration
Reserved, must zero
Feedback Width Endian Reset Mode
There only Configuration register, which configures both Channels. This register read written. used configure chip options. default value fields this register after hardware reset
3.5.1
Feedback Mode
Feedback Mode selects mode operation. set, device operates feedback mode.
Value Mode Normal Feedback
3.5.2
Width
This selects width system bus. this width will bits. this width will bits. This significant only data three registers: Data register, Command register, Result register. other registers bits.
3.5.3
Endian
Little-Endian
Big-Endian
Figure Endian 32-bit mode
9600 Data Compression Processor Data Sheet, DS-0002-01
.Register.Descriptions.
Little-Endian
First Transfer Second Transfer
Big-Endian
First Transfer Second Transfer
Figure Endian 16-bit mode big-endian selects byte order data transferred interfaces Data register. Byte ordering registers other than Data register will affected. Bytes processed order shown (that byte first, then bytes this this chip operates were attached Little Endian processor. Bits data processed first. this this chip operates were attached Endian processor. 32-bit mode, data bits 32-24 will processed first. 16-bit mode, data bits 15-8 will processed first.
3.5.4
Reset
Setting this similar asserting deasserting hardware RESET# signal. chip will immediately stop current activity into known state. difference between this RESET# signal that this will clear Configuration FIFO Configuration registers. During hardware reset, this hardware until device ready normal operation. access device (except read Configuration register) after reset until after reset returns Writing this will clear reset, will clear automatically.
Interrupt Enable (4,12)
Cmnd/ Parity Cmnd Data Result Error Int. Ready SDREQ DDREQ Overrn Error Error Int.
Reserved
This register read written. default value bits this register after reset
3.6.1
Parity Error Interrupt Enable
While this IRQ# signal will asserted while parity error Status register
9600 Data Compression Processor Data Sheet, DS-0002-01
Register. Descriptions
3.6.2 Command Ready Interrupt Enable
While this IRQ# signal will asserted while command ready Status register
3.6.3
SDREQ Interrupt Enable
While this IRQ# signal will asserted while sdreq Status register
3.6.4
DDREQ Interrupt Enable
While this IRQ# signal will asserted while ddreq Status register
3.6.5
Command/Result Overrun Interrupt Enable
While this IRQ# signal will asserted while command/ result overrun Status register
3.6.6
Data Error Interrupt Enable
While this IRQ# signal will asserted while data error Status register
3.6.7
Error Interrupt Enable
While this IRQ# signal will asserted while error Status register
Status (5,13)
Parity Error
Cmnd Ready
SDREQ DDREQ
Cmnd/ Result Overun
Data Error
Error
Reser- Cmnd Result Prog. Prog.
Byte Enable (3-0)
Status register reports status Channel. default value bits this register listed under each description. Only Byte Enable, EOC, fields affected writes. Writing these bytes affects Source FIFO logic corresponding signals been asserted. Reading them reads state signals Destination FIFO logic. error bits Parity Error, Command/Result Overrun, Data Error, Error persistent across commands. Writing them effect. They only cleared hardware software reset.
9600 Data Compression Processor Data Sheet, DS-0002-01
.Register.Descriptions.
3.7.1 Parity Error
read-only parity error when Channel detects parity error incoming data. chip supports byte-wise parity P[3:0]. This error persistent across commands. only cleared through hardware software reset.
3.7.2
Command Ready
read-only command ready when Channel ready accept command. also indicates that Channel idle that results previous command read from Result register. This cleared writing first word Command register. When cleared, this will again until chip ready accept another command (after current command completed).
3.7.3
SDREQ
This read-only when number bytes empty space Source FIFO greater than Source FIFO Upper Threshold value programmed FIFO Configuration register. This when number bytes empty space Source FIFO less than equal Source FIFO Lower Threshold value programmed FIFO Configuration register. sdreq will operate identically SDREQ1# signal. That this will when SDREQ1# signal inactive (high), when SDREQ1# signal active (low). used, SDREQ1# signal used. However, operation sdreq remains same SDREQ1# signal.
3.7.4
DDREQ
This read-only when number bytes Destination FIFO greater than Destination FIFO Upper Threshold value programmed FIFO Configuration register. This when number bytes Destination FIFO less than equal Destination FIFO Lower Threshold value programmed FIFO Configuration register. ddreq will operate same DDREQ1# signal. That this will when DDREQ1# signal inactive (high), when DDREQ1# signal active (low). used, DDREQ1# signal used. However, operation ddreq remains same DDREQ1# signal
9600 Data Compression Processor Data Sheet, DS-0002-01
Register. Descriptions
3.7.5 Command/Result Overrun
This read-only Command register written Result register read while command progress. When set, this persistent across commands only cleared hardware software reset.
3.7.6
Data Error
This read-only Source FIFO written when full (overflow), Destination FIFO read when empty (underflow). When set, this persistent across commands only cleared hardware software reset.
Note
Data error will when Destination FIFO send follow with "DUMMY" bytes. Just ignore data error
when multiple record command.
3.7.7
Error
This read-only follows state error Result register. Section 3.4.1 further details. When set, this persistent across commands only cleared hardware software reset.
3.7.8
Command Progress
This read-only indicates that command currently middle being written read. This becomes after first access Command register. This returns after last access Command register.
3.7.9
Result Progress
This read-only indicates that result currently middle being read. This becomes after first read from Result register. This returns after last read from Result register, when command launched.
3.7.10
Byte Enable
read/write Byte Enable field allows information provided B[3-0] signals during transferred when data stream provided through programmed I/O.
9600 Data Compression Processor Data Sheet, DS-0002-01
.Register.Descriptions.
3.7.10.1 Write Transfer
During write transfer Data register, this field indicates which bytes next write Data register valid. Invalid bytes treated dummy bytes. Table determine which bits correspond which bytes. default value 0b1111 (all bytes valid). byte-enables reinitialized this value after every write Data register.
3.7.10.2
Read Transfer
During read transfer from Data register, this field will indicate valid bytes next read transfer. Invalid bytes should treated dummy bytes. Table determine which bits correspond which bytes. Table Byte enable
BYTE ENABLE BYTE ENABLE BYTE ENABLE BYTE ENABLE
D[7-0] D[15-8] D[23-16] D[32-24
3.7.10.3
allows information provided EOC# signals during transferred when data stream provided through programmed I/O.
3.7.10.4
Write Transfer
During write transfer Data register, this must before last write transfer command. next write Data register will flagged last data current command. command must started before further data will processed. default value EOC). reset after each write Data register.
3.7.10.5
Read Transfer
During read transfer from Data register, this will next read transfer last transfer command. data will processed until command issued.
3.7.11
allows information provided EOR# signals during transferred when data stream provided through programmed I/O.
9600 Data Compression Processor Data Sheet, DS-0002-01
Register. Descriptions
3.7.11.1 Write Transfer
During write transfer from Data register, this must before last write transfer record. next write Data register will flagged last data current record. This reset default value (indicating EOR) after every write Data register.
3.7.11.2
Read Transfer
During read transfer from Data register, this will next read transfer last transfer record. Data following next transfer will from next record.
FIFO Configuration
Rsrvd Rsrvd
Source FIFO Lower Threshold Source FIFO Upper Threshold
Reserved Reserved
Dest FIFO Lower Threshold Dest FIFO Upper Threshold
Register FIFO Configuration register Channel This register read written. configures thresholds which FIFO will request data transfers. These thresholds determine when FIFO ready status bits Status register request signals will asserted. Section 2.12 more information FIFO programming. FIFO threshold values range 0-59.
3.8.1
This determines whether upper lower threshold pairs accessed. writes, this lower FIFO thresholds Source Destination FIFOs will accessed. this upper FIFO thresholds will accessed. reads, reports whether upper lower thresholds were read. When reading this register, upper lower halves will returned alternately, there request other. reading register twice examining bits, there ambiguity over which data which.
3.8.2
Source FIFO Threshold
This field sets both upper lower source FIFO thresholds. lower FIFO threshold will set. upper/lower upper FIFO threshold will set.
9600 Data Compression Processor Data Sheet, DS-0002-01
.Register.Descriptions.
When number bytes empty space source FIFO greater than value Source FIFO Upper Threshold field, sdreq Status register will SDREQ1# will become active. When number bytes empty space source FIFO less than equal value Source FIFO Lower Threshold field, sdreq Status register will zero SDREQ1# will become inactive. Section 2.11.1 Section 2.12 more information regarding this field. Allowable values this field default values both upper lower thresholds after reset 0x00.
SDREQ will never asserted unless there least full transfer that take place (except last transfer command, which less than full-width).
3.8.3
Destination FIFO Threshold
This field sets both upper lower Destination FIFO thresholds. zero, lower FIFO threshold will written. upper FIFO threshold will set. When number bytes Destination FIFO greater than value Destination FIFO Upper Threshold field, ddreq Status register will DDREQ1# will become active. When number bytes Destination FIFO less than equal value Destination FIFO Lower Threshold field, ddreq Status register will zero DDREQ1# will become inactive. Section 2.11.2 Section 2.12 more information regarding this field. Allowable values this field default values both upper lower thresholds after reset 0x00.
DDREQ will never asserted unless there least full transfer that take place (except last transfer command, which less than full-width).
This field defaults zero reset.
Chip (11)
Chip
This register only read. upper bits defined product code lower bits reserved. When this register read, returns Chip value 0x08XX.
9600 Data Compression Processor Data Sheet, DS-0002-01
Register. Descriptions
THIS PAGE INTENTIONALLY LEFT BLANK
9600 Data Compression Processor Data Sheet, DS-0002-01
Signal Descriptions
Interface
This section describes interface signals system bus. interface shares some signals with interface.
4.1.1
System Data (D[31-0])
Bi-directional system data bus. This configured either 16-bit 32bit operation with width Configuration register. While configured 16-bit mode, upper bits (D[31-16]) left unconnected, they terminated with internal pull-up resistors. system data shared with interface.
4.1.2
Parity ([3-0])
Bi-directional parity data bus. Each reflects 8-bits data bus. least-significant corresponds least significant byte bus. configured 16-bit operation, only PB1-PB0 significant. other parity signals left unconnected, they have internal pull-up resistors. parity shared with interface. parity used. That byte 00000000b would result corresponding parity '1'.
4.1.3
Address (A[3-0])
Address input signals Interface. These signals significant only register accesses, accesses.
4.1.4
Read/Write Command (R/W#)
This input signal determines direction data during register transfer. this signal high, read transfer will take place. this signal low, write transfer will take place.
9600 Data Compression Processor Data Sheet, DS-0002-01
Signal. Descriptions
4.1.5 Command Strobe (CS#)
Active input. While this signal active, register access will take place. data direction determined R/W# signal.
4.1.6
Interrupt (IRQ#)
Active output. This signal will become active when event occurs that enabled either Interrupt Enable registers. Once asserted, IRQ# persistent across commands, will deasserted until 9600 receives hardware software reset, until appropriate interrupt enable bits cleared. Interrupt Enable register description further information about when this signal asserted deasserted. This signal open collector output requiring external pull-up resistor VCC.
Interface
This section describes interface signals system bus. Inputs 9600 sampled rising edge CLK. Outputs valid rising edge CLK. protocol covered Section 5.3.3. timing parameters covered Section 6.2.
4.2.1
Byte Enable (B[3-0])
Bi-directional byte-enable data bus. Each reflects enable eight bits data bus. least significant corresponds least significant byte bus. This signal driven Host writes Source FIFO chip reads from Destination FIFO. 16-bit operation, B[3:2] left unconnected, they have internal pull-up resistors.
4.2.2
Ready (RDY#)
Active input. This signal enables data transfers within 9600. When asserted, transfer current cycle completed (written into Source FIFO read from Destination FIFO). When deasserted, transfer deferred. Deasserting RDY# reads from Destination FIFOs causes output wait states. 9600 will drive same Destination FIFO data every clock cycle until RDY# asserted. Asserting RDY# completes transfer enables FIFO clocking that data will appear transfer. Deasserting RDY# input transfers Source FIFOs causes input wait states. Data ignored until RDY# asserted. When RDY# asserted, data latched rising edge current clock cycle written Source FIFO.
9600 Data Compression Processor Data Sheet, DS-0002-01
Signal.Descriptions.
This signal shared between both FIFOs.
4.2.3
Command (EOC#)
Bi-directional signal. This signal indicates current transfer contains last byte current command, current transfer dummy transfer byte-enables asserted), that previous transfer contained last byte current command. This signal used both Channel Channel During transfer Source FIFO, this signal operates input. During transfer from Destination FIFO, this signal operates output.
4.2.4
Record (EOR#)
Bi-directional signal. This signal both active input active output. This signal indicates current transfer contains last byte current record, current transfer dummy transfer byteenables asserted), that previous transfer contained last byte current record. This signal used both Channel Channel During transfer Source FIFO, this signal operates input. During transfer from Destination FIFO, this signal operates output.
4.2.5
Source FIFO Request (SDREQ1#)
Active output. This signal becomes active when Source FIFO contains enough free space accept burst, determined upper FIFO threshold. signal will become inactive when Source FIFO contains number data bytes greater than source FIFO lower threshold. Section 2.11.1 Section 2.12 more information FIFO usage. Both DREQ# signals (DDREQ1#, SDREQ1#) active same time. responsibility Host choose which FIFO service.
4.2.6
Source Acknowledge (SDACK1#)
Active input. Host asserts SDACK# signal initiate writes Source FIFO. Only DACK# signals (DDACK1#, SDACK1#) should asserted same time. SDACK1# signal causes 9600 accept data next clock cycle. data will written Source FIFO RDY# asserted. RDY# asserted, data written FIFO. Section 2.11.1 Section 2.12 more information FIFO usage.
4.2.7
Destination FIFO Request (DDREQ1#)
Active output. This signal becomes active when Destination FIFO contains enough data deliver burst, determined upper FIFO threshold. signal will become inactive when Destination FIFO contains bytes data
9600 Data Compression Processor Data Sheet, DS-0002-01
Signal. Descriptions
less than equal value Lower FIFO threshold, record command, when FIFO empty. Section 2.11.2 Section 2.12 more information FIFO usage. Both DREQ# signals (DDREQ1#, SDREQ1#) active same time. responsibility Host choose which FIFO service.
4.2.8
Destination Acknowledge (DDACK1#)
Active input. Host asserts DDACK# signal initiate reads from Destination FIFO. Only DACK# signals (DDACK1#, SDACK1#) should asserted same time. DDACK1# signal causes 9600 drive data with data after one-cycle delay. RDY# used insert wait states. Section 2.11.2 Section 2.12 more information FIFO usage.
4.2.9
Command Ready
Active-low output. CMDRDY signal active-low output that indicates that Channel ready accept command. used Feedback-Mode handshaking. When 9600 feedback mode, only EOC# should used detect command termination.
4.3.1
Miscellaneous Signals
Reset (RESET#)
Active input. While this signal active, chip will immediately stop current activity into known state. After hardware reset, Compression History will cleared before first use. chip requires several cycles reset itself. reset Configuration register will until this process complete. Except reading Configuration register, chip should accessed until reset clears.
4.3.2
Clock (CLK)
system clock. 9600's internal Engines driven times rate CLK. Section 2.13.
4.3.3
DIV1, DIV0
These inputs used conjunction with SDREQ1# DDREQ1# pins reset time determine internal clock frequency, shown Table previous section. These inputs pulled down external resistors.
9600 Data Compression Processor Data Sheet, DS-0002-01
Timing Descriptions
Both interfaces system operate synchronous mode. signals relative rising edge signal.
Interface
typical access consists clock cycles T2), with number wait states (Tw) between cycles. cycle with activity identified This mode supports minimum cycle time clock cycles. cycle identified assertion signal clock. ADDR signals must also valid. following clock cycle will either based value signal following clock cycle. active, then this cycle will inactive, then this cycle will There number cycles (including zero). During cycle, data will active. ADDR signals longer need valid. following clock cycle will either based value signal following clock cycle. active, then this cycle will inactive, then this cycle will During data transfer remains active. following clock cycle will either based value signal following cycle. active then this cycle will inactive, then this cycle will There number cycles (including zero). During cycle, data will inactive.
Interface
access initiated when Host asserts DACK# signals (DDACK1#, SDACK1#), ends cycle after DACK# deassertion. DACK# signal indicates that Host will either read write next clock cycle. Data transfers must only take place when there space available Source FIFO data available Destination FIFO, indicated SDREQ1# DDREQ1# signals. data overflow underflow occurs during command, data error Status register. device must reset hardware software recover from this error. exception this rule that both reads writes after ignored.
9600 Data Compression Processor Data Sheet, DS-0002-01
Timing .Descriptions
transfer will take place rising clock edge DACK# signal active previous rising clock edge, RDY# signal active current rising clock edge. both DACK# RDY# kept active, device will burst data transfer every clock. When DACK# asserted, considered idle. When DACK# asserted without RDY#, considered wait state. burst ends cycle after DACK# deasserted. Note that DREQ# active following first data transfer, based values FIFO Configuration register amount data FIFO.
Examples
programmable FIFO thresholds allow Host interface designed several ways. Depending burst size FIFO thresholds, Host have sample DREQ# once cycle, once burst, some intermediate value. Similarly, leaving more room FIFOs will allow Host controller take extra cycles start stop bursting without overflowing underflowing FIFOs. timing diagrams following sections provided example implement controller. following sections analyze timing following conditions:
Burst transfer turn around Fixed length burst transfer Variable length burst transfer Burst with wait states Burst with dummy bytes
5.3.1
Timing Diagram Terminology
Cycles start rising edges. "beginning" cycle leading rising edge, "end" cycle trailing rising edge. This shown diagrams cycle numbers located between rising edges. term "clock refers sample point cycle term "cycle indicates entire clock cycle. Signals driven beginning cycle sampled cycle.
Example: Figure DACK# driven system beginning cycle sampled 9600 clock
9600 Data Compression Processor Data Sheet, DS-0002-01
.Timing.Descriptions.
5.3.2 Burst Transfer
DREQ#
DACK#
RDY# EOC#, EOR#
CMDRDY
Read
Write
Figure Four-transfer burst transfers consists data bursts. burst consist only transfer. maximum burst size limited amount space Source FIFO (for write transfer), amount data Destination FIFO (for read transfer). Figure shows four-transfer burst. 9600 will assert DREQ# signals FIFOs that ready accept data transfer. DREQ# signals (DDREQ1#, SDREQ1#) active once. Host controller selects target FIFO asserts DACK# signals (SDDACK1#, DDACK1#). 9600 samples signals rising edge CLK. cycle after 9600 samples DACK# active, RDY# signal will indicate data transfer take place. data transfer will take place current clock RDY# sampled active current cycle DACK# sampled active previous cycle. When 9600 samples DACK# active RDY# inactive, current cycle wait state.
9600 Data Compression Processor Data Sheet, DS-0002-01
Timing .Descriptions
Holding DACK# RDY# active more than clock will transfer byte clock. This figure shows four-transfer burst. DACK# sampled active cycles 3-6, RDY# sampled active cycles 4-7, data transferred clocks 4-7. size bursts device handle using FIFO Threshold values, described Section 3.13. Figure also shows EOC# EOR# CMDRDY occurring burst. indicates that current transfer contains last byte record. EOC# indicates that current transfer contains last command. Note that EOR#/EOC# signal shown burst, this necessary conclude burst. Figure shows timing EOR# EOC# occur middle burst. CMDRDY asserted only feedback mode, when Channel finished command. position relative EOC# undefined. occur same time later. Channel detects error, EOC# asserted all. Only CMDRDY will asserted. Section 4.2.9.
Turn-Around Time
SDREQ#
DDREQ#
SDACK#
DDACK#
RDY# Data
Figure DMA, turn around time Figure shows turn-around time transfers from different FIFOs. This occurs when Host stops servicing FIFO switches another one. example, when switching between writing Source FIFO reading from Destination FIFO. Once Host releases deasserting
9600 Data Compression Processor Data Sheet, DS-0002-01
.Timing.Descriptions.
DACK# signal, claim asserting different DACK# after clock cycle. That dead clock cycle must come between different accesses bus.
status individual DREQ# signals based their respective FIFO thresholds, independent which DACK# currently active.
Fixed-Length Burst Transfers
DREQ#
DACK#
RDY#
Read
Write
Figure DMA, fixed length transfer Figure shows fixed-length burst transfer. During fixed length burst, number transfers will take place. After burst finished, Host will check DREQ# another burst take place. 9600 itself does differentiate between fixed-length variable-length transfers. difference FIFO thresholds programmed Host logic treats DREQ# signals. fixed-length transfers, FIFOs that both lower upper threshold same, accommodate complete burst. Knowing that DREQ# signals will asserted unless FIFO read write entire burst, Host logic only needs sample DREQ# signals beginning burst. DREQ# signal become deasserted some point during burst, this effect transfer. transfers occur regardless state DREQ#.
9600 Data Compression Processor Data Sheet, DS-0002-01
Timing .Descriptions
Figure shows two-transfer bursts. Each burst begins clock that 9600 samples DACK# active ends clock that 9600 samples DACK# inactive. Once burst completes, Host sample DREQ# next clock following burst. This will determine another burst same FIFO occur. Figure DREQ# active after first burst, deasserted after second burst. Thus, another burst occur. command ends middle read burst, transfers after EOC, still within burst, will consist dummy bytes (with byte enables deasserted). After command ends burst containing EOC# complete, chip's interface disabled, with DREQ#, DACK#, RDY# signals deasserted. 9600 will ignore attempts read write over interface until next command issued.
5.5.1
Reducing Dead Time
two-clock delay occurs because DREQ# sampled clock edge after last transfer, DACK# cannot activated again until determined that DREQ# still active. figure shows cycles dead time both read write operations. Dead time reduced cycle setting both FIFO thresholds transfer larger than burst size. This will cause DREQ# asserted cycle earlier. example, threshold instead 16-byte bursts with 32-bit bus. This works because 9600 will transfer data when DREQ# deasserted.
9600 Data Compression Processor Data Sheet, DS-0002-01
.Timing.Descriptions.
Variable-Length Burst Transfers
DREQ#
DACK#
RDY#
Read
Write
Figure DMA, variable length transfer Figure shows timing variable length burst transfer. this case, Host controller been designed sample DREQ# every clock cycle, continue transfers until DREQ# deasserted 9600. This will occur when FIFO's Lower Threshold crossed when reached. number transfers burst known advance. Figure controller samples DREQ# signal inactive cycle lower FIFO threshold being crossed after transfer cycle Then, controller deactivates DACK#, which 9600 samples inactive cycle which transferred. After DACK# signal deactivated, will still active until cycle transfer take place. Thus, variable length transfers done, there another transfers after contoller samples DREQ# inactive. order prevent data error from occurring, lower threshold values must accommodate least transfers. this instance, lower FIFO threshold must least (for 32-bit bus). lower threshold could RDY# were deasserted DACK# deasserted (9600 samples both signals inactive cycle because that would inhibit transfer this case, will driven data will transferred. Thus, lower FIFO Threshold RDY# determine number transfers that occur after DREQ# detected inactive.
9600 Data Compression Processor Data Sheet, DS-0002-01
Timing .Descriptions
Bursting with Wait States
DREQ#
DACK#
RDY# EOC# EOR# Read
Write
Figure DMA, three-transfer burst with wait states Figure shows burst transfer where Host using RDY# signal insert wait states. Wait states never required 9600. They inserted Host accommodate Host-side delays. When DACK# signal held active, 9600 will continue drive data transfers from Destination FIFO. However, data transfer will complete (either writing source FIFO reading dest FIFO) only cycle where RDY# asserted. Figure also shows EOC# EOR# signal signifying that transfer represents last transfer record command).
9600 Data Compression Processor Data Sheet, DS-0002-01
.Timing.Descriptions.
Bursting with Dummy Bytes
SDACKx#
DDACKx#
RDY# EOC# EOR# Read
Write
Figure DMA, four-transfer burst Figure shows burst where EOR# EOC# signal occurs middle burst. example, this might occur destination transfer using fixed-length bursts during compression. Section 2.10.4 data alignment requirements different kinds transfers.
5.8.1
Write Transfers
write transfers Source FIFO, Host asserts EOR# signal indicate that current transfer contains last byte record. Host asserts byte-enable signals indicate last valid byte record. next transfer burst contains valid data determined byte-enables), data treated start next record. decompression, possible that transfer after will contain bytes that Channel will consider part current record, data record 32-bit aligned. Section. 3.11.4 When Host asserts EOC# signal command, transfers between start next command treated dummy bytes (regardless state byte-enables) discarded.
9600 Data Compression Processor Data Sheet, DS-0002-01
Timing .Descriptions
5.8.2 Read Transfers
read transfers from Destination FIFO, behavior 9600 identical. EOR# EOC# signals indicate that current transfer contains last byte record command. Subsequent transfers burst always consist solely dummy bytes, should ignored Host. next burst reassertion DACK# after least cycle DACK# deassertion) will read 32-bit-aligned data from next record. spite dummy bytes, still possible underflow Destination FIFOs. Dummy bytes used burst. burst will pull valid data from FIFO, possibly underflowing controller does first sample DREQ#.
9600 Data Compression Processor Data Sheet, DS-0002-01
Specifications
Specifications
Table Absolute maximum ratings
Supply Voltage (VDD) Input Voltage Input Current Operating Temperature Storage Temperature -0.3V +7.0V -0.3V +7.0V ±10mA -55°C +125°C -65°C +150°C
Caution: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect device reliability.
Table Recommended operating conditions
Supply Voltage Operating Temperature +3.0V +3.6V +70°C
Table specification definition
Symbol Parameter Load Supply voltage Ground potential Ambient operating temperature Conditions 3.3V 0.3V +70°C
9600 Data Compression Processor Data Sheet, DS-0002-01
Specifications
Table electrical characteristics
Symbol Parameter level input voltage Clock Input (CI) High level input voltage (I,SI) Clock Input (CI) Schmitt hysteresis level input current (I,SI) With Pull-up (PI) High level input current level output voltage (02) (04) (06) (08) High level output voltage (02) (04) (06) (08) COUT CI/O High impedance leakage current Quiescent supply current Input capacitance Output capacitance Input/Output capacitance Power dissipation Conditions Units
3.6V
3.3V 3.0V
3.0V
-2mA -4mA -6mA -8mA
3.6V 3.3V 3.3V 3.3V 3.3.V
Core Logic Clock 80MHz Clock
9600 Data Compression Processor Data Sheet, DS-0002-01
.Specifications.
6.2.1
Specifications
Reset Clock Timing
Table Reset power-up timing
Reset
Number Description Reset width First access after Reset already locked) 12*CLK 2*CLK
lock time after stable
Table timing
Item
Description Oscillator frequency Clock period Clock width high Clock width Clock rise time from Clock fall time from
Units
9600 Data Compression Processor Data Sheet, DS-0002-01
Specifications
Table timing
Access Access wait state
Addr
Read Operation R/W#
Data
Write Operation R/W#
Data
Item
Description Addr setup Addr hold
Units
setup hold R/W# setup R/W# hold
Data output valid delay (read) Data hold (read) Data setup (write) Data hold (write) Tri-state enable Tri-state disable
14.5 16.3
9600 Data Compression Processor Data Sheet, DS-0002-01
.Specifications.
Table timing
xDREQ#
xDACK#
RDY#
Read
Write
Item
Description
14.8
Units
DREQ# output valid delay DREQ# hold DACK# setup DACK# hold RDY# setup RDY# hold EOR# EOC# output valid delay EOR# EOC# hold
Read data output valid delay Read data hold Write data setup Write data hold Data Tri-state enable Data Tri-state disable
14.8 14.5
16.3
9600 Data Compression Processor Data Sheet, DS-0002-01
Specifications
Description
Signal Signal Signal
Table Description, numerical order
CMDRDY R/W# SDREQ1# SDACK1# DDREQ1# DDACK1# DIV1 DIV0 RDY# IRQ# RESET# EOR# EOC#
9600 Data Compression Processor Data Sheet, DS-0002-01
.Specifications.
Table Description, alphabetical order
Signal Signal Signal
CMDRDY
DDACK1# DDREQ1# DIV0 DIV1 EOC# EOR# IRQ#
R/W# RDY# RESET# SDACK1# SDREQ1#
9600 Data Compression Processor Data Sheet, DS-0002-01
Specifications
RESET#
EOC#
EOR#
IRQ#
R/W#
Figure Pinout diagram
9600 Data Compression Processor Data Sheet, DS-0002-01
SDREQ1#
SDACK1#
CMDRDY
RDY# DIV0 DIV1 DDACK1# DDREQ1#
9600 View
.Specifications.
0.825
Package Dimensions
23.8 20.0
14.0
0.575
0.65BSC
3.05
0.13
17.8
0.19
0.15
+0.1
-0.05
0-10
PRS002542
Note: units
Figure 100-pin PQFP package dimensions
9600 Data Compression Processor Data Sheet, DS-0002-01
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