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AN120E04 Datasheet Reconfigurable FPAA
www.anadigm.com
DS021000-U004d
Disclaimer
Anadigm reserves right make changes without further notice products herein. Anadigm makes warranty, representation guarantee regarding suitability products particular purpose, does Anadigm assume liability arising application product circuit, specifically disclaims liability, including with limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Anadigm does this document convey license under patent rights rights others. Anadigm software associated products cannot used except strictly accordance with Anadigm software license. terms appropriate Anadigm software license shall prevail over above terms extent inconsistency.
Anadigm® Ltd. 2003 Anadigm®, Inc. 2003 Rights Reserved.
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
PRODUCT ARCHITECTURE OVERVIEW
AN120E04 member Anadigm®'s second generation FPAA family Anadigmvortex family. Based fully differential switched-capacitor architecture, this product family features higher bandwidth, improved total harmonic distortion (THD) ability implement host advanced functions relative Anadigm®'s first generation product. AN120E04 device provides low-cost path implementing analog signal conditioning high-volume applications. AN120E04 consists matrix fully configurable switched capacitor configurable analog blocks (CABs), enmeshed fabric programmable interconnect resources. These programmable features directed on-chip SRAM configuration memory. four CABs have access single Look-Up Table (LUT) which used implement linear functions such user-defined input-to-output transfer functions, arbitrary signal waveform generation. Analog input signals come from outside world four input cells. fourth input cell AN120E04 special `multiplexing' feature which allows connection four unique signal sources. input cell accept either singleended signal differential signal pair. input cells each have built-in programmable anti-aliasing filters, well high gain amplifier which optional chopper stabilized operating mode designed with signals requiring significant gain hence ultra input offset voltages.
Figure Architectural overview AN120E04 device
PRODUCT FEATURES
Fully differential architecture Fully differential buffering with options single ended differential conversion input offset through chopper stabilized amplifiers Built-in Successive Approximation Register (SAR) Byte Look-Up Table (LUT) linearization arbitrary signal generation Input multiplexer Typical Signal Bandwidth: DC-2MHz (Bandwidth dependent) Signal Noise Ratio: Broadband 80dB Narrowband (audio) 100dB Total Harmonic Distortion (THD): 80dB offset <100µV Package: 44-pin (10x10x2mm) Lead pitch 0.8mm Supply voltage:
APPLICATIONS
Sensor interfacing signal conditioning Complex filtering applicable variety applications Industrial control automation Medical monitoring diagnostics Adaptive designs Precision control Ultra-low frequency signal conditioning Custom analog signal processing
ORDERING CODES
AN120E04-QFPSP AN120E04-QFPTY AN120E04-QFPTR AN220D04-EVAL AN220D04-DEVLP Reconfigurable FPAA Sample Pack Reconfigurable FPAA Tray pcs) Reconfigurable FPAA Tape Reel (1000 pcs) AN220E04 Evaluation AN220E04 Development
[For more detailed information features AN220E04 device, please refer AN120E04/AN220E04 User Manual]
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Power Supplies xVDD xVDD Offset Package Power Dissipation Analog Digital Input Voltage Ambient Operating Temperature Storage Temperature
Symbol
AVDD(2) BVDD DVDD Pmax 25°C Pmax 85°C Vinmax Tstg
-0.5 -0.5 Vss-0.5
Unit
Comment
AVSS, BVSS, DVSS SVSS held Ideally supplies should same voltage Still air, heatsink, layer board, pins. 55°C/W
0.73 Vdd+0.5
Absolute Maximum Power Supply Rating failure mode non-catastrophic volts, will cause reduced operating life time. additional stress caused higher local electric fields within CMOS circuitry induce metal migration, oxide leakage other time/quality related issues.
Recommended Operating Conditions
Parameter
Power Supplies
Symbol
AVDD(2) BVDD DVDD Vina Vind
4.75 VMR-1.9
5.00
5.25 VMR+1.9 DVDD
Unit
Comment
AVSS, BVSS, DVSS SVSS held volts above AVSS Assume package 55°C/W
Analog Input Voltage. Digital Input Voltage Junction Temp
order calculate junction temperature must first empirically determine current draw (total Idd) design. Once current consumption established then following formula used; °C/W, where ambient temperature. worst case °C/W assumes flow additional heatsink type.
General Digital Characteristics (Vdd 10%, deg.C)
Parameter
Input Voltage Input Voltage High Output Voltage Output Voltage High Input Leakage Current Input Leakage Current Max. Capacitive Load Min. Resistive Load DCLK Frequency ACLK Frequency Clock Duty Cycle
Symbol
Cmax Rmin Fmax Fmax
±12.0
±1.0
Unit
Kohm
Comment
DVDD DVDD DVDD DVDD pins except DCLK DCLK crystal connected on-chip oscillator used maximum load digital output Kohm maximum load digital output Kohm MODE DCLK Divide down prior clock clocks
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Detailed Digital Interface Characteristics: 5.0volts LCCb
Parameter
Output Voltage Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source
Symbol
Cmax Rmin Isnkmax Isrcmax
Unit
Kohm
Comment
Load 20pF//50Kohm Load 20pF//50Kohm Maximum load Kohm Maximum load Kohm LCCb shorted LCCb shorted
CFGFLG, ACTIVATE
Parameter
Input Voltage Input Voltage High Output Voltage Output Voltage High Output Voltage Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source External Resistive Pullup Cmax Rmin Isnkmax Isrcmax Rpullupext Kohm Kohm
Symbol
Unit
Comment
DVDD DVDD load Internal pullup 20pF//50K load Internal pullup 20pF//50K Load External pullup 20pF//50K Load External 5Kohm pullup 20pF//50K Maximum load Kohm Maximum load Kohm shorted shorted only internal pullup deselected
ERRb
Parameter
Input Voltage Input Voltage High Output Voltage Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source External Resistive Pullup
Symbol
Cmax Rmin Isnkmax Isrcmax Rpullupext
Unit
Kohm Kohm
Comment
DVDD DVDD
Maximum load Kohm Maximum load Kohm
Parameter
Input Voltage Input Voltage High
Symbol
Unit
Comment
DVDD DVDD
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
OUTCLK/SPIMEM,DOUTCLK
Parameter
Output Voltage Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source
Symbol
Cmax Rmin Isnkmax Isrcmax
Unit
Kohm
Comment
DVDD DVDD Maximum load Kohm Maximum load Kohm
ACLK/SPIP
Parameter
Input Voltage Input Voltage High Output Voltage Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source
Symbol
Cmax Rmin Isnkmax Isrcmax
Unit
Kohm
Comment
DVDD DVDD DVDD DVDD Maximum load Kohm Maximum load Kohm
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Analog Inputs General
Parameter
High Precision Input Range Standard precision Input Range High Precision Differential Input Standard Precision Differential Input Common Mode Input Range Input Offset Input Frequency
Symbol
Vina Vina Vdiffina Vdiffina
+/-3.0 +/-3.8
Unit
Comment
1.5v 1.9v Common mode voltage Common mode voltage
Fain
Non-chopper stabilized input value clock, input stage dependant. Input frequency limited approx <2MHz signal processing which based sampled data architectures.
High precision operating range provides optimal linearity dynamic range. Standard precision operating range provides maximum dynamic range reduced linearity.
Input Differential Amplifier filter
Parameter
Input Range Gain Setting Gain Accuracy Gain Drift (Temperature, Supply Voltage zand Time) Equivalent Input Offset Voltage
Symbol
Vina Vdiffina Ginamp Dist
Unit
Comment
Usable input range will reduced effective gain setting
analog input above
Offset Voltage Temperature Coefficient Input Frequency Input Frequency Power Supply Rejection Ratio Common Mode Rejection Ratio Large Signal Harmonic Distortion Input Resistance Input Capacitance Input Referred Noise Figure
Non-chopper stabilized input When input amplifier filter used combination contribution comes only from input amplifier from -40°C 125°C
Voffsettc Fain Fain PSRR CMRR Dist
µV/°C Mohm µV/sqrtHz
d.c. Gain a.c. graphs page 0.4v Differential input 660Hz Gain setting Input cell Gain Applies audio frequency range (400Hz 30KHz). graphical data page Input signal diff, audio frequency range graphical data page Input signal diff graphical data page
Signal-to Noise Ratio Distortion Spurious Free Dynamic Range
SINAD SFDR
High precision operating range provides optimal linearity dynamic range. Standard precision operating range provides maximum dynamic range reduced linearity.
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Input Differential Chopper Amplifier filter
Parameter
Input Range Gain Setting Gain Accuracy Gain Drift, (Temperature, Supply Voltage Time) Chopper Frequency Clock Range
Symbol
Vina Vdiffina Ginamp
>250
Unit
Comment
Usable input range will reduced effective gain setting
analog input above
master clock frequency slow possible 250KHz will result some signal attenuation Chopper stabilized amplifier maximum value 200µV guaranteed production test This tester limitation from -40°C 125°C d.c. a.c. graphs page 0.4v Differential input 660Hz Gain setting Fch=Chopper clock frequency chopper frequency input frequency should chosen such that subsequent pass filtering remove chopper stage frequency elements Input filter chopper Input cell Gain Applies Audio frequency range Chopper clock 250KHz graphical data page Input signal differential, Audio frequency range graphical data page Input signal =100 differential graphical data page
Equivalent Input Offset Voltage Offset Voltage Temperature Coefficient Power Supply Rejection Ratio Common Mode Rejection Ratio Large Signal Harmonic Distortion Input Frequency Fain Voffsettc PSRR CMRR Dist
Fc/260100
<100
µV/°C
Fch/20
Fch/2
Input Resistance Input Capacitance Input Referred Noise Figure
0.09
Mohm µV/sqrtHz
Signal-to Noise Ratio Distortion Spurious Free Dynamic Range
SINAD
SFDR
Input Differential Amplifier filter
Parameter
Input Range Equivalent Input Offset Offset Voltage Temperature Coefficient Input Frequency Fain
Symbol
Vina Vdiffina Voffsettc
Unit
Comment
Non-chopper stabilized input, Filter corner frequency =470KHz from -40°C 125°C measured filter corner=470Khz maximum Filter corner=76KHz Input filter frequency will define maximum frequency Input filter recommended >30x higher than input frequency, 80dB distortion performance
analog input above
0.05
mV/°C
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Common Mode Rejection Ration Power Supply Rejection Ratio Large Signal Harmonic Distortion Input Pass Filter (Anti-Alias) Corner Frequency Settings Input Resistance Input Capacitance Input Referred Noise Figure Signal-To Noise Ratio Distortion Spurious Free Dynamic Range CMRR PSRR Dist Ffiltcorner SINAD SFDR 0.17 Mohm µV/sqrtHz Input filter chopper Input cell filter corner 470KHz Applies Audio frequency range graphical data page Input signal 1400 diff, Audio frequency range graphical data page Input signal =1400 differential graphical data page d.c. a.c. graphical data page Differential input 660Hz Filter corner frequency 470KHz
Input Differential Voltage mode, Amplifier OFF, Filter Unity Gain stage
Parameter
Input Range Equivalent Input Offset Offset Voltage Temperature Coefficient Input Frequency Power Supply Rejection Ratio Common Mode Rejection Ratio Large Signal Harmonic Distortion Large Signal Harmonic Distortion Input Resistance Input Capacitance Input Referred Noise Figure Signal-To Noise Ratio Distortion Spurious Free Dynamic Range
Symbol
Vina Vdiffina Voffsettc Fain PSRR CMRR Dist Dist SINAD SFDR
0.16
Unit
µV/°C Kohm µV/sqrtHz
Comment
Non-chopper stabilized input from -40°C 125°C Gain Bandwidth limited input impedance d.c. a.c. graphs page Differential input 660Hz single ended signal 660Hz Input unity gain stage Applies Audio frequency range graphical data page Input signal 1400 diff, Audio frequency range graphical data page Input signal =1400 differential graphical data page
analog input above
Input Differential Voltage mode, Amplifier OFF, Filter Unity Gain stage
Parameter
Input Range Equivalent Input Offset Offset Voltage Temperature Coefficient Input Frequency Power Supply Rejection Ratio Large Signal Harmonic Distortion Input Resistance
Symbol
Vina Vdiffina Voffsettc Fain PSRR Dist
Unit
µV/°C Mohm
Comment
Amp. from -40°C 125°C Dependant upon Input directly (Input cell bypass mode). This variable influenced capacitor size, clock frequency architecture Input directly (Input cell bypass mode) This variable influenced capacitor size, clock frequency architecture
analog input above
Input Capacitance
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Analog Outputs
(See "Output Cell" section AN120E04/AN220E04 user manual more details)
Parameter
High Precision Output Range Standard Precision Output Range High Precision Differential Output Standard precision Differential Output Common Mode Voltage
Symbol
Vouta Vouta Vdiffouta Vdiffouta
+/-3.0 +/-3.8
Unit
Comment
1.5v 1.9v Common mode voltage Common mode voltage
High precision operating range provides optimal linearity dynamic range. Standard precision operating range provides maximum dynamic range reduced linearity.
Output Voltage mode filter corner frequency 470KHz
Parameter
Input Range Equivalent Input Offset Offset Voltage Temperature Coefficient Output Frequency Faout
Symbol
Vina Vdiffina Voffsettc
0.05
Unit
mV/°C
Comment
analog input above
Power Supply Rejection Ratio Large Signal Harmonic Distortion Input Pass Filter (Anti-Alias) Corner Frequency Settings Output Load Output Load Output Load
PSRR Dist Ffiltcorner Rload Cload
Mohm
from -40°C 125°C measured filter corner: 470Khz maximum filter corner: 76KHz Output filter frequency will define maximum frequency Input filter recommended >30x higher then input frequency, good distortion performance d.c. a.c. graphical data page Differential input 660Hz Filter corner frequency 470KHz
Rload
Kohm
Output Load Common Mode Rejection Ratio Input Referred Noise Figure
Additional loading causes internal voltage drops across output stage series resistances output stage small signal output impedance approx 10ohm
Cload CMRR
0.22
µV/sqrtHz Output filter corner 470KHz Applies Audio frequency range graphical data page Input signal 1400 diff, Audio frequency range graphical data page Input signal =1400 diff graphical data page
Signal-To Noise Ratio Distortion Spurious Free Dynamic Range
SINAD SFDR
High precision operating range provides optimal linearity dynamic range. Standard precision operating range provides maximum dynamic range reduced linearity. maximum load analog output Kohms. This load maybe with respect analog ground AVSS.
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Output Voltage mode filter (bypass mode)
Parameter
Input Range Equivalent Input Offset Offset Voltage Temperature Coefficient Output Frequency Output Frequency
Symbol
Vina Vdiffina Voffsettc Faout Faout
Unit
mV/°C Mohm
Comment
realizable output frequency limited approx <2MHz signal processing which based sampled data architectures.
analog input above
Power Supply Rejection Ratio Large Signal Harmonic Distortion Output Load Output Load
PSRR Dist Rload Cload
High precision operating range provides optimal linearity dynamic range. Standard precision operating range provides maximum dynamic range reduced linearity. maximum load analog output Kohms. This load maybe with respect analog ground AVSS. maximum load analog output Kohms. This load must differential with respect analog ground(VMR).
(voltage Rail) VREF (Reference Voltage) Ratings
Parameter
Output Voltage VREF+ Output Voltage VREF- Output Voltage Output Voltage Deviation VREF+, VMR, VREFVoltage Temperature Coefficient VREF+, VMR, VREFPower Supply Rejection Ratio, Power Supply Rejection Ratio Vref+ VrefStart Time
V+ref temperature
Symbol
Vvmr Vref+ VrefVrefout Vreftc PSSR PSSR Tstart
1.925 0.45
2.01 3.51 0.505 temperature
2.075 0.55
Unit
Comment
25°C, Vdd=5.00 volts 25°C, Vdd=5.00 volts 25°C, Vdd=5.00 volts Over process supply voltage corners typical graphical data below -40°C 125°C
Assuming recommended capacitors
0.510 0.505
Vref- temperature
3.510 3.505
Volts
2.010 2.005
Volts
3.500 3.495 3.490
Tchip
2.000 1.995 1.990
Tchip
Volts
0.500 0.495 0.490
Tchip
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
(Configurable Analog Block) Differential Operational Amplifier
Parameter
High Precision Input/Output Range Standard Precision Input/Output Range High Precision. Differential Input/Output Standard Precision Differential Input/Output Common Mode Input Voltage Range Common Mode Output Voltage Range Equivalent Input Voltage Offset. Offset Voltage Temperature Coefficient Power Supply Rejection Ratio Common Mode Rejection Ratio CMRR Common Mode Rejection Ratio CMRR
Symbol
Vinouta Vinouta Vdiffioa Vdiffioa Voffset
+/-3.0 +/-3.8
Unit
Comment
1.5v +/-1.9v Common mode voltage Common mode voltage
Voffsettc
µV/°C
PSSR
Differential Slew Rate, Internal Differential Slew Rate, External Unity Gain Bandwidth, Full Power Mode. Input Impedance, Internal Output Impedance, Internal
Slew Slew Rout
V/µsec V/µsec Mohm Ohms
Some CAMs (Configurable Analog Modules) inherently compensate from -40°C 125°C some CAMs (Configurable Analog Modules) inherently compensate Variation between CAMs expected because variations architecture Example GainInv clock 1MHz parameter settings Gain Example Filterbiquad Setting pass filter clock 1MHz parameter settings Gain Corner frequency 50KHz Quality Factor 0.707 Applicable when OpAmp load internal FPAA Applicable when OpAmp driving signal FPAA package Applicable when sourcing loading OpAmp with load internal FPAA OpAmp output designed drive internal nodes, these dominantly capacitive loads Output FPAA output (ouput cell bypass mode). This variable influenced capacitor size, clock frequency architecture
Output Impedance, External Output Load, External Output Load, External Output Load, External
Rout Rload Cload
Ohms Mohm
Rload
Kohm
Output Load, External Noise Figure
Additional loading causes internal voltage drops across output stage series resistances output stage small signal output impedance approx 10ohm Example1 GainInv clock 1MHz Gain
Cload Noise
0.13
µV/sqrtHz
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Signal-To Noise Ratio Distortion SINAD Input signal=1400 differential Audio frequency range Example. GainInv clock 1MHz Gain Input signal=1400 differential, Audio frequency range Example. GainInv clock 1MHz Gain
Spurious Free Dynamic Range SFDR
High precision operating range provides optimal linearity dynamic range. Standard precision operating range provides maximum dynamic range reduced linearity. maximum load analog output Kohms. This load with respect analog ground AVSS. Using FPAA with Amp's driving directly off-chip, requires care, full characterization performance each application circuit circuit designer necessary. This specification parameter only characterized when circuit topology configured onto differential amplifier architecture. figure provided here representative performance specific CAM, specified comments.
Idealized Open Loop Gain [dB] 1000 100000 Frequency (KHz)
Open Loop Gain (dB)
idealized open loop gain plot provided information only. This information associated with FPAA full power mode operation. FPAA operation amplifier open loop gain cannot observed used when associated with external connections device. Internal reprogrammable routing impedances switched capacitor circuit architecture using this operational amplifier limit effective usable bandwidth circuit realized FPAA less than 2MHz.
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
(Configurable Analog Block) Differential Comparator
Parameter
Input Range, Internal Input Range, External Differential Input, Internal Differential Input, External Common Mode Output Voltage Range, Internal Common Mode Input Voltage Range, External Common Mode Input Voltage, External Differential Output Single Output (Ox1P) Input Voltage Offset Offset Voltage Temperature Coefficient Setup Time, Internal Setup Time, External Delay Time Output Load Rload Output Load Cload Differential Variable Reference Voltage Settings Differential Hysteresis Differential Hysteresis Differential Hysteresis Differential Hysteresis Hysteresis Setting Accuracy Hysteresis Temperature Coefficient Hysteresis Temperature Coefficient Hysteresis Temperature Coefficient Hysteresis Temperature Coefficient
Symbol
Vina Vina Vdiffina Vdiffina Voutdiff Vout Voffcomp Voffsettc Tsetint Tsetext Tdelay
Voffcomp
+/-3.8 +/-5 +/-4.0
Unit
µV/°C nsec nsec nsec Kohm µV/°C µV/°C µV/°C µV/°C
Comment
Common mode voltage
comparator will function correctly Zero hysterisis from -40°C 125°C, Zero Hysterisis
1/Fc master clock frequency Applies comparator drive chip with output cell bypass mode Applies comparator drive chip with output cell bypass mode Hysteresis setting zero Hysteresis setting 10mV Hysteresis setting 20mV Hysteresis setting 40mV Hysteresis setting zero Hysteresis setting 10mV Hysteresis setting 20mV Hysteresis setting 40mV
CompVref Hysta1 Hysta2 Hysta3 Hysta4 Hystb Hysttc1 Hysttc2 Hysttc3 Hysttc4
High precision operating range provides optimal linearity dynamic range. Standard precision operating range provides maximum dynamic range reduced linearity.
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Characteristics
Type
Digital Inputs Digital Outputs Digital Bidirectional Digital Open Drain Analog Inputs Analog Outputs Reference Voltages
Human Body Model
4000V 4000V 4000V 4000V 2000V 1500V 1500V
Machine Model
250V 250V 250V 250V 200V 100V 100V
Charged Device Model
AN120E04 (electrostatic discharge) sensitive device. Electrostatic charges high 4000V readily accumulate human body test equipment discharge without detection. Although AN120E04 device features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Power Consumption Power Mode
Parameter
Minimum Power Nominal Power1b Nominal Power Nominal Power1d Maximum Power1e
Symbol
Unit
µA/°C
Comment
Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=4.75 volts, Tj=85°C Vdd=5.00 volts, Tj=25°C Vdd=5.25 volts, -40°C
Temperature Coefficient
External clock, analog function disabled, memory active. FPAA active elements core op-amps (low power mode), comparator, input (bypass mode), output filter differential single-ended converter (low power mode). FPAA active elements Four core op-amps (low power mode), comparators (one using SAR), inputs (bypass mode), output filters differential singleended converters (low power mode). FPAA active elements core op-amps (low power mode), three comparators (two using SAR), three inputs (bypass mode, output filters differential single-ended converters (low power mode). FPAA active elements Eight core op-amps (low power mode), four comparators (two using SAR), four inputs (bypass mode), output filters differential singleended converters (low power mode).
Power consumption power mode (temp degree (mA) Vdd=4.75V Vdd=5.0V Vdd=5.25V 100%
Resource Utilization
Power Consumption Full Power Mode
Parameter
Full Power Mode Minimum Power Full Power Mode Nominal Power2b Full Power Mode Nominal Power2c Full Power Mode Nominal Power2d Full Power Mode Maximum Power2e
Symbol
Unit
Comment
Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=4.75 volts, Tj=85°C Vdd=5.00 volts, Tj=25°C Vdd=5.25 volts, -40°C
AN220E04 Crystal Oscillator, analog functions disabled, memory active. FPAA active elements core op-amps, comparator, input filter chopper amplifier, output filter differential single-ended converter. FPAA active elements Four core op-amps, comparators (one using SAR), Input filters chopper amplifiers, output filters differential single-ended converters. FPAA active elements core op-amps, three comparators (two using SAR), three input filters three chopper amplifiers, output filters differential single-ended converters. FPAA active elements Eight core op-amps, four comparators (two using SAR), four input filters chopper amplifiers, output filters differential single-ended converters.
Power consumption full power mode (temp degree (mA) Vdd=4.75V Vdd=5.0V Vdd=5.25V 100%
Resource Utilization
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
PINOUT
Numb
Name
I4PA I4NA AVSS AVDD SHIELD AVDD2 VREFMC VREFPC VMRC BVDD BVSS CFGFLGb
Type
Analog Analog INAnalog OUT+ Analog OUTAnalog Analog Analog Analog Analog Analog INAnalog Analog INAnalog Analog Vref Vref Vref Analog Analog Digital Digital
Comments
CS2b CS1b
Digital Digital (during config) Digital (after config)_ Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital (monitored OUT) Digital Digital
noise bias capacitor array n-wells Analog power Attach filter capacitor VREFAttach filter capacitor VREF+ Attach filter capacitor (Voltage Main Reference) Analog power bandgap Vref Generators Analog ground bandgap Vref Generators multi-device systems. Ignore incoming data (unless currently addressed) attention incoming data (watching address) Device being configured Device being configured internal pullup selected) Chip selected Chip selected Allow configuration proceed Hold configuration Passes read-back data through LCC_B Digital ground substrate Synchronous serial interface EPROM Interface MODE analog clock MODE EPROM serial EPROM clock During power-up, sources EPROM initialization command string After power-up, sources four internal analog clocks
DCLK SVSS MODE ACLK SPIP OUTCLK SPIMEM DVDD DVSS LCCb ERRb
ACTIVATE
DOUTCLK TEST PORb EXECUTE I4PD I4ND I4PC I4NC I4PB I4NB
Digital Digital Digital Digital Analog Analog INAnalog Analog INAnalog Analog INAnalog Analog
Serial configuration data input Local configuration needed. Once configuration completed, registered version CS1b device addressed read, serves serial data port Initiate reset action Error condition error condition (external pullup required) Hold completion configuration Rising Edge, Allow completion configuration O.D. Output device completed primary configuration Device completed primary configuration internal pullup selected) buffered version DCLK. (Factory reserved test input. Float unused) Chip held reset state Rising edge, re-initiates power reset sequence initiate reset cycle, minimum pulse width required PORb 25ns. action Transfer shadow into configuration
Analog multiplexer input signals. multiplexer accept differential inputs single ended inputs
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
MECHANICAL HANDLING
AN120E04 comes industry standard lead package. pack handling recommended. package qualified MSL3 (JEDEC Standard, J-STD-020A, Level Once device removed from pack, 30°C humidity longer than hours maximum recommended exposure prior solder reflow. pack longer than this recommended period time, then recommended bake procedure prior solder reflow hours 125°C.
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Distortion, SINAD Measurements
following plots give indication Distortion, SINAD some representative CAMs.
INPUT CELL SNR, DSTN, SINAD
-100
SNR[
INPUT CELL PASS FILTER SNR, DSTN, SINAD
[dB]
[dB]
SINAD[ DISTN[
-100
SNR[ SINAD[ DISTN[
INPUT [Vp-p]
INPUT [Vp-p]
100.00 80.00 60.00 40.00 20.00 0.00 -20.00 -40.00 -60.00 -80.00 -100.00 0.08 0.14 0.21 0.28 0.35 0.42 0.49
SNR[ SINAD[ DISTN[
INPUT CELL AMPLIFIER SNR,DSTN,SINAD Measured with Inputcell Gain Same results Input Amplifier Chopper Amplifier stage, signal from chopper Amplifier correctly filtered before measurement.
[dB]
INPUT [Vp-p]
Output Cell SNR, DSTN, SINAD
-100
[dB]
SNR[dB] SINAD[dB] DISTN[dB]
INPUT [Vp-p]
SNR[ SINAD[ DISTN[
GAININV SNR, DSTN, SINAD This graph shows typical performance FPAA when configured with this example GainInv Input signal=1400 differential, clock 1MHz parameter settings Gain
[dB]
INPUT [Vp-p]
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Power Supply Rejection Ratio (PSRR) Measurements
following plots give indication PSRR some representative CAMs. AVDD Power Supply (PS): 0.25v sinusoidal waveform (100 MHz)
INPUT PSRR [dB]
80.00 70.00 60.00 50.00 40.00 30.00 20.00 1KHz 10KHz 100KHz
80.00 70.00 60.00 50.00 40.00 30.00 20.00 1KHz 10KHz 100KHz
INPUT PSRR [dB]
100.00 90.00 80.00 70.00 60.00 50.00 40.00 30.00 20.00
VMR, Vref+, Vref-
PSRR [dB]
PSRR_VMR PSRR_VREFP PSRR_VREFP
1KHz
10KHz
100KHz
OUTPUT Voltage Mode PSRR [dB]
80.00 70.00 60.00 50.00 40.00 30.00 20.00 1KHz 10KHz 100KHz
GAININV_1MHz PSRR [dB]
1KHz 10KHz 100KHz
GAININV_4MHz PSRR [dB]
1KHz
10KHz
100KHz
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
following provided information only, when additional characterization data collected `noise measurements' will added formally datasheet.
Noise Distortion Observations
following plots give indication noise characteristics Anadigm®'s AN120E04 FPAA device. These were done using simple set-up many cases reflect noise limit setup. Actual device noise margins expected better.
Signal Noise Input Cell (input signal 50mVp-p differential FPAA kHz)
Signal Noise: 376KHz,
Input gain stage Input anti-aliasing filter Input chopper amplifier
Signal Noise Output Cell (with differential input p-p, 660Hz)
Signal Noise: -106 345KHz,
Voltage output mode (including filter) Output smoothing filter
DS021000-U004d
AN120E04 Datasheet Reconfigurable FPAA
Measured input output cells (with differential input p-p, 660Hz)
Settings
Input cell with anti-aliasing filter Output cell with differential single ended converter output smoothing filter
Distortion
81.6
Signal Noise representative Gaininv (input signal 700mV differential kHz)
Signal Noise: kHz,
representative Gaininv (with differential input p-p, 660Hz)
Clock Frequency
Distortion (dB)
80.00 72.83 69.22 73.48
above, zoom lower frequency
DS021000-U004d
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