QuadPortDatapath Switching Element (DSE) Family QuadPortDatapath

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QuadPortDatapath Switching Element (DSE) Family QuadPortDatapath

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CY7C0452V18/0451V18/0450V18 CY7C0431V18/0430V18 PRELIMINARY
QuadPortDatapath Switching Element (DSE) Family
QuadPortDatapath Switching Element (DSE) allows four independent ports access data path management switching. Synchronous pipelined device 128K CY7C0452V18 CY7C0451V18 CY7C0450V18 128K CY7C0431V18 CY7C0430V18 Clock operation High Bandwidth Gbps LVTTL SSTL2 standard LVPECL differential clock inputs Impedance matching data outputs Simple array partitioning (except CY7C0452V18) Internal mask register burst counter control Counter-Interrupt flags indicate terminal count Block Retransmit Capability Counter mask register readback address lines Dual Chip Enables ports easy depth expansion (except CY7C0452V18) Separate byte select controls ports package (676 balls, pitch) Commercial Industrial temperature ranges IEEE 1149.1 JTAG boundary scan 1.8V Supply Voltage Active 1300 (maximum) Standby (maximum)
QuadPort Applications
PORT PORT
PORT
PORT
BUFFERED SWITCH
PORT
PORT
PORT
PORT
REDUNDANT DATA MIRROR
PORT
PORT
PORT
PORT
DATA PATH AGGREGATOR
Cypress Semiconductor Corporation Document 38-06065 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised August 2002
CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18
Configuration
Ball Grid Array (BGA) (CY7C0451V18)[1]
CNTRDB CNTL
CNTI
CNTI INTB
CNTI INTB
CNTI
CNTRDB CNTL
CE0B
RETX CNTRST
RETX CNTRST
CE0B
TRST
DQ10
DQ11
DQ12
DQ13
DQ14
DQ14
DQ13
DQ12
DQ11
DQ10
DQ15
DQ16
DQ17
DQ18
DQ19
DQ19
DQ18
DQ17
DQ16
DQ15
REFA
REFA
REFA
REFA
REFA
REFA
REFA
REFA
DQ21
DOFF DQ23
DOFF DQ23
DQ21
DQ20
DQ22
DQ24
DQ24
DQ22
DQ20
DQ25
DQ26
DQ27
DQ28
DQ29
DQ29
DQ28
DQ27
DQ26
DQ25
DQ30
DQ31
DQ32
DQ33
DQ34
DQ34
DQ33
DQ32
DQ31
DQ30
DQ35
DQ36
DQ37
DQ38
DQ39
DQ39
DQ38
DQ37
DQ36
DQ35
DQ35
DQ36
DQ37
DQ38
DQ39
DQ39
DQ38
DQ37
DQ36
DQ35
DQ30
DQ31
DQ32
DQ33
DQ34
DQ34
DQ33
DQ32
DQ31
DQ30
DQ25
DQ26
DQ27
DQ28
DQ29
DQ29
DQ28
DQ27
DQ26
DQ25
DQ20
DQ21
DQ22
DQ23
DQ24
DQ24
DQ23
DQ22
DQ21
DQ20
DOFF
DOFF
REFA
REFA
REFA
REFA
REFA
REFA
REFA
REFA
DQ15
DQ16
DQ17
DQ18
DQ19
DQ19
DQ18
DQ17
DQ16
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ14
DQ13
DQ12
DQ11
DQ10
INTB
INTB
CE0B
CNTRST RETX
CNTL CNTRDB
CNTI
CNTI
CNTL CNTRDB
CNTRST RETX
CE0B
CNTI
CNTI
Note: Following name represents active signal. example,
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CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18
Table Table (CY7C0451V18) VSSPIN CY7C0451V18 VDDC VDDC VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDC VDDC MKLDB RETXB CNTRDB WRP0B CNTINTB CNTINTB Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 WRP0B CNTRDB RETXB MKLDB CE0B CNTRSTB CNTLDB CNTINCB MKRDB INTB INTB MKRDB CNTINCB CNTLDB CNTRSTB CE0B VDDQ TRST READYB
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Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 READYB VDDQ VDDQ VDDQ VDDQ DQ10 Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 DQ11 DQ12 DQ13 DQ14 DQ13 DQ12 DQ11 DQ10 VDDQ VDDQ DQ15 DQ16 DQ17 DQ18 DQ19
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Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 DQ19 DQ18 DQ17 DQ16 DQ15 VDDQ VDDC VREFA VREFA VREFA VREFA VREFA VREFA VREFA VREFA VDDC VDDQ DOFFB Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 DOFFB VDDQ VDD1 DQ20 DQ21 DQ22 DQ23 DQ24 VREFQ VREFQ DQ24 DQ23 DQ22 DQ21 DQ20 VDDQ VDDQ DQ25 DQ26 DQ27
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Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 DQ28 DQ29 VREFQ VREFQ DQ29 DQ28 DQ27 DQ26 DQ25 VDDQ VDDQ DQ30 DQ31 DQ32 DQ33 DQ34 VREFQ VREFQ DQ34 DQ33 Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 DQ32 DQ31 DQ30 VDDQ VDDQ DQ35 DQ36 DQ37 DQ38 DQ39 VREFQ VREFQ DQ39 DQ38 DQ37 DQ36 DQ35 VDDQ VDDQ DQ35 DQ36 DQ37 DQ38 DQ39 VREFQ
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Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 VREFQ DQ39 DQ38 DQ37 DQ36 DQ35 VDDQ VDDQ DQ30 DQ31 DQ32 DQ33 DQ34 VREFQ VREFQ DQ34 DQ33 DQ32 DQ31 DQ30 VDDQ VDDQ DQ25 DQ26 DQ27 DQ28 DQ29 Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 VSSVSS VREFQ VREFQ DQ29 DQ28 DQ27 DQ26 DQ25 VDDQ VDDQ DQ20 DQ21 DQ22 DQ23 DQ24 VREFQ VREFQ DQ24 DQ23 DQ22 DQ21
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Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 DQ20 VDDQ VDDQ DOFFB DOFFB VDDQ VDDC VREFA VREFA VREFA VREFA VREFA VREFA VREFA Table Table (CY7C0451V18) (continued) VSSPIN CY7C0451V18 VREFA VDDC VDDQ DQ15 DQ16 DQ17 DQ18 DQ19 MRSTB DQ19 DQ18 DQ17 DQ16 DQ15 VDDQ VDDQ DQ10 DQ11 DQ12 DQ13 DQ14
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Table Table (CY7C0451V18) (continued) VSSPIN AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 CY7C0451V18 DQ13 DQ12 DQ11 DQ10 VDDQ VDDQ VDDQ Table Table (CY7C0451V18) (continued) VSSPIN AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 CY7C0451V18 VDDQ READYB READYB VDDQ CE0B CNTRSTB CNTLDB CNTINCB MKRDB INTB INTB
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Table Table (CY7C0451V18) (continued) VSSPIN AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF10 CY7C0451V18 MKRDB CNTINCB CNTLDB CNTRSTB CE0B MKLDB RETXB CNTRDB WRP0B CNTINTB CNTINTB WRP0B CNTRDB RETXB MKLDB VDDC VDDC VDDA VDDA VDDA Table Table (CY7C0451V18) (continued) VSSPIN AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 CY7C0451V18 VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDC VDDC
Functional Description
family synchronous true four-ported Datapath Switching Element (DSE), Gb/s density. four ports clocked independent frequencies from another. Writes reads permitted simultaneously from four ports switch array. Simultaneous reads allowed accesses same address location; however, simultaneous reading writing same location allowed. QuadPort family clocked with synchronous, pipelined accesses MHz. Clock data valid Registers control, address data lines allow minimal set-up hold time. QuadPort family supports burst counter block transfers data. QuadPort also supports features such impedance matching, memory block retransmit capability, counter address readback, mask address readback. Burst Counter Operation Each port contains burst counter input address register. After externally loading counter with initial address, counter will self-increment address internally (more details follow). internal write pulse width independent duration input signal. internal write pulse self-timed allow shortest possible cycle times. Counter enable inputs provided block external address input utilize internal address generated internal counter fast interleaved memory applications. port's burst counter loaded with external address when port's Counter Load (CNTLD) asserted LOW. When port's Counter Increment (CNTINC) asserted, address counter will increment each subsequent LOW-toHIGH transition that port's clock signal. This will read/write word from/into each successive address location until CNTINC deasserted. counter address entire memory array will loop back start. Counter Reset
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(CNTRST) used reset unmasked portion burst counter. counter-mask register used control counter wrap. counter mask register operations described more detail following sections. counter mask register values read back bidirectional address lines activating CNTRD MKRD, respectively. Block Retransmit Retransmit feature that allows reread block memory more than once without need reload initial address. This eliminates need external logic store route data. also reduces complexity system design saves board space. internal "mirror register" used store initially loaded address counter value. When counter unmasked portion reaches maximum value mask register, will wrap back initial value stored this "mirror register". unmasked bits will wrap zero. mirror register value will loaded into counter when RETX asserted LOW. When unmasked wrap mirror register. counter continuously configured increment mode, will increment again maximum value wraps back value initially stored into "mirror register," thus allowing access same data repeatedly without need external logic. Programmable I/Os Each port will have strapping pins that used select standard used data address/control. will standard data will standard address control. Either LVTTL SSTL2 Class I/Os will selected shown. traces cause these effects. These mismatches cause reflections board, which dramatically impact system's ability transmit data. most common ways used solve this problem place terminating resistors each trace board. These resistor nets ensure that impedance device's matches traces board. This approach, though, have huge impact amount board space required system. QuadPort solves both problems allowing designer impedance driver match impedance board traces. Each port QuadPort Variable Impedance Sense (VIS) circuit. circuit sets output impedance bus. calibration circuit input called calibrating resistor (RQ) connected between ground. value must value intended line impedance driven QuadPort DSE. allowable range guarantee impedance matching with tolerance ±15% between 500. When MRST asserted LOW, control circuitry reset Ready deasserted. When MRST released, circuit begins process matching output impedance 0.2*RQ. Ready will asserted within 1024 cycles each port's respective clock. Each port's output impedance guaranteed correct range when Ready output asserted LOW. output impedance adjusted account drifts supply voltage temperature every 1024 port clock cycles thereafter. user also choose disable variable impedance matching connecting directly VDD. When disabled, output impedance will less-than equal
Variable Impedance Parameters
Parameter Value Output Impedance Reset Time Update Time Minimum Maximum 1024 1024 Units cycles cycles Tolerance ±15%
Standard Strapping Codes
Strapping Value Variable Impedance Sense Another problem that often encountered high-speed digital design what commonly known transmission line effects. Impedance mismatches between devices Standard Selected LVTTL SSTL2
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Port Operation-Control Logic Blocks[2,
READY DOFF B0P1 B1P1 B2P1
B3P1
MRST
Reset Logic
R/WP1 OEP1
CE0P1
CE1P1 DIOP1 AIOP1 C-P1 C+P1 I/O0P1-I/O39P1 ZQP1 A0P1-A15P1 MKLDP1 CNTLDP1 CNTINCP1 CNTRDP1 MKRDP1 CNTRSTP1 WRPP1 RETXP1 INTP1 CNTINTP1
Port-1 Control Logic
TRST
JTAG Controller
Port
Port Logic Blocks[4]
Port Counter/ Mask Reg/ Address Decode
Port
Port
QuadPort Array
5/2/1 128/64/32Kx40 128/64Kx20
Port
Port
Port Logic Blocks[4]
Port Logic Blocks[4]
Notes: CY7C0431/0430V18 pins instead CY7C0452/0431V18 (128K) have address bits instead CY7C0451/0430V18 (64K) have address bits. CY7C0450V18 (32K) address bits instead Port Port Port Logic Blocks similar Port Logic Blocks.
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Definitions
Port Port Port Port Description Ground supply core, address/control, data, clock. Power supply core. user must ensure that ramps simultaneously ahead other device power supplies. VDDA VDDQ VREFA VREFQ A0P4-A15P4[3]. DQ0P4- DQ39P4[2] C+P4 Power supply address/control port Power supply data port Power supply clock Pins must connected reference voltage using SSTL address/control port Pins must connected reference voltage using SSTL data port Address Input/Output Data Input/Output Positive Clock Input. used capture synchronous inputs device. This input free running strobed. Maximum clock input rate fMAX. Negative Clock Input. used capture synchronous inputs device must equal frequency. This input free running strobed. Maximum clock input rate fMAX. Data Standard Select Input. This will select standard data pins. HIGH signal will select pins switch SSTL2 levels. signal will select pins switch LVTTL levels. pins must strapped either upon power-up. Address/Control Standard Select Input. This will select standard address control pins. HIGH signal will select pins switch SSTL2 levels. signal will select pins switch LVTTL levels. pins must strapped either upon power-up. Byte Select Input. Asserting this signal enables read write operations byte read operations both signals must asserted drive output data lower byte data pins. Byte Select Input. Same function byte
VDDA VDDQ VREFA VREFQ A0P1-A15P1[3]. DQ0P1- DQ39P1[2] C+P1
VDDA VDDQ VREFA VREFQ A0P2-A15P2[3]. DQ0P2- DQ39P2[2] C+P2
VDDA VDDQ VDDC VREFA VREFQ A0P3-A15P3[3]. DQ0P3- DQ39P3[2] C+P3
C-P1
C-P2
C-P3
C-P4
DIOP1
DIOP2
DIOP3
DIOP4
AIOP1
AIOP2
AIOP3
AIOP4
B0P1
B0P2
B0P3
B0P4
B1P1 B2P1[5] B3P1[5] CE0P1,CE1P1
B1P2 B2P[5]2 B3P2[5] CE0P2,CE1P2
B1P3 B2P3[5] B3P3[5] CE0P3,CE1P3
B1P4 B2P4 B3P4[5] CE0P4,CE1P4
Byte Select Input. Same function byte Byte Select Input. Same function byte Chip Enable Input. select port, both must asserted their active states (CE0 VIH). Output Enable Input. This signal must asserted enable data lines during read operations. asynchronous input. Read/Write Enable Input. This signal asserted write QuadPort memory array. read operations, assert this HIGH.
OEP1
OEP2
OEP3
OEP4
R/WP1
R/WP2
R/WP3
R/WP4
Note: available CY7C0431/0430V18
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Definitions (continued)
Port Port MRST Port Port Description Master Reset Input. This signal Ports. MRST asynchronous input. Asserting MRST performs reset functions described text. MRST operation must performed power-up. CNTRSTP4[6] Counter Reset Input. Asserting this signal resets unmasked portion burst address counter respective port zero. CNTRST second MRST priority with respect counter mask register operations. Mask Register Load Input. Asserting this signal loads mask register with external address available address lines. MKLD operation higher priority over CNTLD operation. Counter Load Input. Asserting this signal loads burst counter with external address present address pins. Counter Increment Input. Asserting this signal increments burst address counter respective port each rising edge Counter Readback Input. When asserted LOW, internal address value counter will read back address lines. During CNTRD operation, both CNTLD CNTINC must HIGH. Counter readback operation higher priority over mask register readback operation. Counter readback operation independent port chip enables. address readback operation occurs with chip enables active (CE0 LOW, HIGH), data lines (I/Os) will three-stated. Mask Register Readback Input. When asserted LOW, value mask register will readback address lines. During mask register readback operation, counter MKLD inputs must HIGH (see Counter Mask Register Operations truth table). Mask register readback operation independent port chip enables. three-stated regardless chip enables. When internal counter driven address pins, pins three-stated. Counter Interrupt Flag Output. Flag asserted clock cycle when counter reaches maximum count. Interrupt Flag Output. Interrupt permits communications between four ports. upper four memory locations used message passing. Example operation: INTP4 asserted when another port writes mailbox location Port Flag cleared when Port reads contents mailbox. same operation applicable Ports When burst counter reaches maximum count, unmasked bits will wrap asserted LOW. Otherwise, counter will loaded with contents mirror register. When RETX asserted burst counter loaded with contents mirror register.
CNTRSTP1[6]
CNTRSTP2[6]
CNTRSTP3[6]
MKLDP1[6]
MKLDP2[6]
MKLDP3[6]
MKLDP4[6]
CNTLDP1[6] CNTINCP1[6] CNTRDP1[6]
CNTLDP2[6] CNTINCP2[6] CNTRDP2[6]
CNTLDP3[6] CNTINCP3[6] CNTRDP3[6]
CNTLDP4[6] CNTINCP4[6] CNTRDP4[6]
MKRDP1[6]
MKRDP2[6]
MKRDP3[6]
MKRDP4[6]
CNTINTP1[6]
CNTINTP2[6]
CNTINTP3[6]
CNTINTP4[6]
INTP1
INTP2
INTP3
INTP4
WRPP1[6]
WRPP2[6]
WRPP3[6]
WRPP4[6]
RETXP1[6]
RETXP2[6]
RETXP3[6]
RETXP4[6]
Note: available CY7C0452V18
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Definitions (continued)
Port ZQP1 Port ZQP2 Port ZQP3 Port ZQP4 Description Output Impedance Matching Input. This input used adjust device data outputs impedance match system data impedance. Output impedance where resistor connected between ground. acceptable resistor values 500. Alternately, this connected directly VDD, which disables impedance matching. This cannot connected directly left floating. Output indicates port ready operation. been properly locked clock input signals. requires 1024 cycles lock following master reset operation. input disables integrated Delay Locked Loop circuit port. DOFF toggled then HIGH reset associated port. That port will require 1024 cycles relock, other ports unaffected. JTAG Port Reset JTAG Test Clock Input. This port external clock connected JTAG TAP. JTAG Test Data Input. This only data input. inputs will shift data serially selected register. JTAG Test Data Output. This only data output. transitions occur falling edge TCK. normally three-stated except when captured data shifted JTAG TAP. JTAG Test Mode Select Input. controls advance JTAG state machine. State machine transitions occur rising edge TCK.
READYP1
READYP2
READYP3
READYP4
DOFFP1
DOFFP2
DOFFP3
DOFFP4
TRST
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Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -40°C 125°C Ambient Temperature with Power Applied. -40°C 125°C Supply Voltage Ground Potential -0.5V 1.9V Voltage Applied Outputs High State LVTTL -0.3V 3.9V Input Voltage. -0.3V 3.9V Voltage Applied Outputs High State SSTL2. -0.3V 2.7V Input Voltage SSTL2 .-0.3V 2.7V Output Current into Outputs (LOW). Static Discharge Voltage (HBM) >2200V Static Discharge Voltage (CDM) >750V Latch-Up Current >200
Operating Ranges
Range Commercial Industrial Ambient Temperature +70°C -40°C +85°C 1.8V 1.8V
Current Characteristics Over Operating Range
-167 Parameter ICCQ ISBQ Description Core Operating Current (VDD Max., IOUT Outputs Disabled, VIL, fmax Core Standby Current Ports CMOS Level, active) CE1-4 VIH, Operating Current port (VDDQ Max, external load, fmax) Standby Current port (VDDQ Max, external load, Outputs Disabled Address/ Control Operating Current port (VDDA Max, external load, fmax) Address/Control Standby Current port (VDDA Max, external load, Clock JTAG Operating Current Total (VDDC Max, fmax) Clock JTAG Standby Current Total (VDDC Max, CE1-4 VIH) Typ. Max. 1300 Typ. -133 Max. 1100 Typ. -100 Max. Unit
ICCA ISBA ICCC ISBC
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Electrical Characteristics
0430V18 Parameter VDDQ/A VREF VDDQ/A VDDC VIDIF LVPECL (Clocks only) LVTTL Type Description Reference Voltage Termination Voltage Input High Voltage Input Voltage (VDDQ 2.3V-2.7V) Output Leakage Current Output Source Current (VDDQ 2.3V) Output Sink Current (VDDQ 2.3V) Supply Voltage Input High Voltage Input Voltage Output High Voltage (IOH Output Voltage (IOL Output Leakage Current Supply Voltage Input High Voltage Input Voltage Input Differential Voltage -100 1.85 Min. 1.15 VREF 0.04 VREF 0.18 -0.3 -100 -7.6 -0.3 0.85 1.45 1000 Max. 1.35 VREF 0.04 VDDQ VREF 0.18 Unit SSTL2-Class Supply Voltage
JTAG Electrical Characteristics Over Operating Range
Parameter VOH1 VOL1 Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage -8.0 Test Conditions Min. Max. Unit
Capacitance
Parameter (ALL PINS) COUT (ALL PINS) PINS) Description Input Capacitance Output Capacitance Input Capacitance Test Conditions 25°C, MHz, 3.3V Max. Unit
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Test Load
OUTPUT OUTPUT MEASURE POINT
1.5V
1.5V OUTPUT
Normal Load (LVTTL)
OUTPUT
3.3V
Three-state Delay
VDDQ
3.0V
Normal Load (SSTL2 Class
1.5V VSWING (MAX)
1.5V
LVTTL INPUTS
VIHmin(AC) VREF 0.35V VREF 1.25V VILmax(AC) VREF 0.35V deltaT deltaT
Load
SLEW (VIHMIN(AC) VILMAX(AC))/deltaT V/ns
SSTL2 INPUTS
LVPECL Input Waveform
VDD_CLK VIH(MAX) VIH(MIN)
VIDIF VIL(MAX) VIL(MIN) VSS_CLK Rise Time Fall Time timing referenced crossing
LVPECL INPUTS
Note: Test Conditions:
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Switching Characteristics Over Commercial/Industrial Operating Range
Parameter qualifier fMAX tCYC tSWRP tHWRP tSRT tHRT tSCLD tHCLD tSCINC tHCINC tSCRD tHCRD tSRST tHRST tSMLD tHMLD tSMRD tHMRD tOLZ tOHZ tCKHZA Description Maximum Operating Frequency Clock Cycle Time Clock HIGH Time Clock Time Clock Rise Time Clock Fall Time Input Data Set-up Time Input Data Hold Time WRP0 Set-up Time WRP0 Hold Time RETX Set-up Time RETX Hold Time Address Set-up Time Address Hold Time Byte Set-up Time Byte Hold Time Chip Enable Set-up Time Chip Enable Hold Time Set-up Time Hold Time CNTLD Set-up Time CNTLD Hold Time CNTINC Set-up Time CNTINC Hold Time CNTRD Set-up Time CNTRD Hold Time CNTRST Set-up Time CNTRST Hold Time MKLD Set-up Time MKLD Hold Time MKRD Set-up Time MKRD Hold Time Output Enable Data Valid Output Enable Output Enable High Clock Counter Addr. Readback Valid Address Output Hold After Clock HIGH Clock High Address Output High 10.0 Min. -167 Max. Min. -133 Max. Min. -100 Max. Unit
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Switching Characteristics Over Commercial/Industrial Operating Range (continued)
Parameter qualifier tCKLZA tCKLZ tCKHZ tCD2 tDC2 tCKHZ2 tCKLZ2 tCCS tSCINT tRCINT tSINT tRINT tRSR tRSF tRDY fJTAG tTCYC tTMSS tTMSH tTDIS tTDIH tTDOV tTDOX tTRS with with with with Description Clock High Address Output Clock Master Register Readback Valid Clock Valid DQ/A Output Hold After Clock HIGH Clock High DQ/A Output Clock High DQ/A Output High Clock Valid (DOFF=0) DQ/A Output Hold After Clock HIGH (DOFF=0) Clock HIGH DQ/A Output High (DOFF=0) Clock HIGH DQ/A Output (DOFF=0) Clock Clock Set-up Time Clock CNTINT Clock CNTINT HIGH Clock Clock HIGH Master Reset Pulse Width Master Reset Recovery Time Master Reset Outputs Inactive/High Master Reset Release Port Ready JTAG Controller Frequency Cycle Time High Time Time Set-Up Rise Hold Rise Set-Up Rise Hold Rise Valid Invalid TRST Pulse Width 20.0 1024 22.5 22.5 1024 20.0 1024 Min. -167 Max. Min. -133 Max. Min. -100 Max. Unit Cycles
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JTAG Timing Switching Waveforms
Test Clock
tTMSS tTMSH
tTCYC
Test Mode Select
tTDIS tTDIH
Test Data-In
Test Data-Out
tTDOX tTDOV
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Switching Waveforms
Master Reset[8,
tCYC tCHCH MRST tRSF READY tRDY tRSR
DQ39:0[2]
A16:0[3]
CNTINT
tS[9] Control Inputs tTRS TRST
INACTIVE ACTIVE
Notes: master reset cycle required after power-up parameter represents set-up time required each input power TRST must asserted least tTRS ensure controller Test-Logic-Reset state.
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Switching Waveforms (continued)
Read Cycle[6,
tCYC tCHCH A16:0[3] An+1 DQ39:0[2] Qx-3 Qx-2 Qx-1 An+2 An+3 Qn+1 An+4 An+5 tCHC
Write Cycle[11,
tCYC tCHCH A16:0[3] An+1 DQ39:0[2] Dn+1 Dn+2 An+2 Dn+3 Dn+4 An+3 An+4 tCHCH
Notes: address location data written location data read from location There cycles latency data reach response read instruction CNTLD VIL, MRST CNTRST MKLD VIH, CNTINC RETX WRP0 CNTRD MKRD CNTLD VIL, MRST CNTRST MKLD VIH, CNTINC RETX WRP0 CNTRD MKRD
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Switching Waveforms (continued)
Bank Select Read During Depth Expansion[11,
tCYC tCHCH A16:0(B1)[3] An+1 CE0(B1) DQ39:0(B1)
tCHCH
An+2 An+3 An+4 An+5 An+6
tCKHZ
tCKLZ Qn+2
A16:0(B2)[3] An+1 CE1(B2) DQ39:0(B2)
An+2 An+3 An+4 An+5 An+6
tCKHZ
Qn+1
tCKLZ
Qx-2
Qx-1
Notes: represents Bank represents Bank Each bank consists QuadPort device. A(B1) A(B2) CE0(B2) CNTLD VIL, MRST CE1(B1) CNTRST MKLD VIH, CNTINC RETX WRP0 CNTRD MKRD
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Switching Waveforms (continued)
Bank Select Write During Depth Expansion[11,
tCYC tCHCH A16:0(B1)
tCHCH
An+2 An+3 An+4 An+5 An+6
An+1
CE0(B1) DQ39:0(B1)[2] Dn+1 A16:0(B2)[3] An+1 CE1(B2) DQ39:0(B2)
Dn+2 An+2 An+3 An+4 An+5 An+6 Dn+3 Dn+4 Dn+5 Dn+6
Dn+2 Dn+3 Dn+4 Dn+5 Dn+6
Dn+1
Note: CE0(B2) CNTLD VIL, MRST CE1(B1) CNTRST MKLD VIH,CNTINC RETX WRP0 CNTRD MKRD=
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Switching Waveforms (continued)
Read-to-Write VIL)[11,
tCYC tCHCH A16:0
tCHCH
An+1
An+2
DQ39:0
Qx-2 Qx-1
tCKHZ
Dn+1
Dn+2
Qx-4
Qx-3
Read-to-Write Controlled)[11,
tCYC tCHCH A16:0
tCHCH
Ax+2 Ax+3 Ax+4 An+1 An+2
An+3
An+4
DQ39:0
Qx-1
Dn+1 Dn+2
Dn+3
Dn+4
Qx-2
Notes: When VIL, last read operation allowed complete before three-stated user allowed drive write data. Four dummy writes should issued accomplish turnaround. fifth write instruction first valid write. address should held constant during four dummy writes first valid write instruction avoid data corruption. CNTLD VIL, MRST CNTRST MKLD VIH, CNTINC RETX WRP0 CNTRD MKRD should deasserted tOHZ allowed elapse before first write operation issued. read scheduled complete after asserted will preempted. CNTLD VIL, MRST CNTRST MKLD VIH, CNTINC RETX WRP0 CNTRD MKRD
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Switching Waveforms (continued)
Byte Enable Write[11,
tCYC tCHCH tCHCH
A16:0[3] DQ39:30[2,5] 0x000 0x3FF 0x155
0x155
DQ29:20[2,5]
0x000
0x3FF
0x155
0x3FF
DQ19:10[2]
0x000
0x3FF
0x2AA
0x2AA
DQ9:0[2]
0x000
0x3FF
0x2AA
0x000
B3[5]
B2[5]
Note: CNTLD VIL, MRST CNTRST MKLD VIH, CNTINC RETX WRP0 CNTRD MKRD
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Switching Waveforms (continued)
Byte Enable Read[11,
tCYC tCHCH tCHCH
A16:0[3] DQ39:30
[2,5]
0x000 tCKHZ 0x000 tCKLZ
DQ29:20
[2,5]
0x3FF
0x3FF
DQ19:10
0x155
0x155
DQ9:0[2]
0x2AA
0x2AA
B3[5]
B2[5]
Note: CNTLD VIL, MRST CNTRST MKLD VIH, CNTINC RETX WRP0 CNTRD MKRD
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Switching Waveforms (continued)
Read with Address Counter Advance[6,
tCYC tCHCH A16:0
tCHCH
Internal address tSCLD CNTLD
tHCLD
An+1
An+2
An+3
tSCINC CNTINC DQ39:0
tHCINC
Qn+1 Qn+2
Qx-2
Qx-1
Note: VIL, MRST CNTRST MKLD RETX VIH, WRP0 CNTRD MKRD
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Switching Waveforms (continued)
Write with Address Counter Advance[6,
tCYC tCHCH A16:0[3] tCHCH
Internal address tSCL CNTLD tHCLD
An+1
An+2
An+3
tSCINC CNTINC DQ39:0[2] Dn+1 Dn+2 Dn+2
tHCINC
Dn+3
Dn+4
Dn+5
Note: VIL, MRST CNTRST MKLD RETX VIH, WRP0 CNTRD MKRD
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Switching Waveforms (continued)
Counter Reset[6,
tCYC tCHCH A16:0[3] OX1755 tCHCH
Internal address tSCLD CNTLD tHCLD
0X17550
0X17551
0X17000
0X17001
0X17002
tSCINC CNTINC tSRST CNTRST DQ39:0[2] tHRST
tHCINC
Q17550 Q17551 Q17000
Notes: Only umasked bits burst counter reset response CNTRST operation. MASK 0x00FFF. VIL, MRST CNTRST MKLD RETX VIH, WRP0 CNTRD MKRD MASK 0x00FFF.
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Switching Waveforms (continued)
Counter Interrupt (WRP VIH)[6,
tCYC tCHCH A16:0[3] OX17FFC tCHCH
Internal address tSCLD CNTLD tHCLD
0X17FFC
0X17FFD
0X17FFE
0X17FFF
0X17FFC
tSCINC CNTNC tSCINT CNTINT DQ39:0[2]
tHCINC
tRCINT
Q17FFC Q17FFD Q17FFE
Notes: internal burst counter reaches maximum count when each either masked equal Each port mirror register that loads external address value response CNTLD operation. bits mirror register reset response MRST operation. Unmasked bits mirror register reset response CNTRST operation. value mirror register unaffected other burst counter operations including CNTINC. When WRP0 VIH, internal burst counter loaded with contents mirror register cycle after COUNT maximum count. VIL, MRST CNTRST MKLD RETX VIH, CNTRD MKRD
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Switching Waveforms (continued)
Counter Interrupt (WRP VIL)[6,
tCYC tCHCH A16:0[3] OX17FFC tCHCH
Internal address tSCLD CNTLD tHCLD
0X17FFC
0X17FFD
0X17FFE
0X17FFF
0X17000
tSCINC CNTNC tSCINT CNTINT DQ39:0[2]
tHCINC
tRCINT
Q17FFC
Q17FFD
Q17FFE
Notes: When WRP0 VIL, unmasked bits burst counter reset cycle after COUNT maximum count. VIL, MRST CNTRST MKLD RETX VIH, CNTRD MKRD
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Switching Waveforms (continued)
Forced Retransmit[6,
tCYC tCHCH A16:0[3] tCHCH
Internal address tSCLD CNTLD tHCLD
An+1
An+2
An+1
tSCINC CNTINC tSRT RETX DQ39:0[2] tHRT
tHCINC
Qn+1 Qn+2
Notes: When RETX= VIL, value mirror register loaded burst counter regardless counter's current value. VIL, MRST CNTRST MKLD VIH, WRP0 CNTRD MKRD
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Switching Waveforms (continued)
Load Read Address Counter[6,
tCHC A16:0
tCHCH
tCKLZ
tCKHZ An+1
tSCLD CNTLD
tHCLD
tCA2
tSCIN CNTINC
tHCINC
tSCR CNTRD
tHCRD
DQ39:0
tCKHZ Qn+1
tCKLZ Qn+1
Note: VIL, MRST CNTRST MKLD RETX VIH, WRP0 MKRD
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Switching Waveforms (continued)
Load Read Mask Register[6,
A16:0
0x17FF
tCKLZ
tCKHZ 0x17FFC
tSMLD MKLD
tHMLD
tCA2
tSMMKRD
tHM-
tCKHZ DQ39:0
tCKLZ
tCKHZ
tCKLZ
Note: VIL, MRST CNTRST CNTLD CNTINC RETX CNTRD VIH, WRP0
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Switching Waveforms (continued)
Mailbox Interrupt[11,
tCYC C+(P1) tCHC C-(P1) A16:0(P1)
tCHCH
0x1FFF
R/W(P1) DQ39:0(P1)
D1FFFE tSINT tRINT
INT(P2) C+(P2) tCHC C-(P2) A16:0(P2)
tCHCH
0x1FFFE
R/W(P2)
DQ39:0(P2)
Q1FFFE
Notes: Port Mailbox Address 0x1FFFF, Port Mailbox Address 0x1FFFE, Port Mailbox Address 0x1FFFD, Port Mailbox Address 0x1FFFC There cycle latency between writing mailbox location flag being asserted LOW. There cycle latency between reading mailbox location flag being deasserted HIGH. CNTLD VIL, MRST CNTRST MKLD VIH, CNTINC RETX WRP0 CNTRD MKRD
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Switching Waveforms (continued)
Port Write Port Read[11,
tCYC C+(P1) tCHCH C-(P1) A16:0(P1)
tCHCH
R/W(P1) DQ39:0(P1)
tCCS
C+(P2) tCHCH C-(P2) A16:0(P2)[3] R/W(P2) DQ39:0(P2)[2] tCHCH
Notes: tCCS allowed elapse between write Port Read Port data resulting from read operation indeterminate. This waveform applies write read operations ports. CNTLD VIL, MRST CNTRST MKLD VIH, CNTINC RETX WRP0 CNTRD MKRD
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Table Read/Write Enable Operation (Any Port)[52, Inputs Outputs I/O0-I/O39 High-Z High-Z DOUT High-Z Deselected Deselected Write Read Outputs Disabled Operation
Table Address Counter Counter-Mask Register Control Operation (Any Port)[6,
MRST CNTRST MKLD CNTLD RETX CNTINC CNTRD MKRD Mode Operation
Master Reset Reset Load Load
Counter/Address Register Reset Mask Register (resets entire chip reset state table) Counter/Address Register Reset Load Address Lines into Mask Register Load Address Lines into Counter/Address Register
ReLoad address from Mask Register Transmit Increment Readback Readback Hold Counter Increment Readback Counter Address Lines Readback Mask Register Address Lines Counter Hold
Notes: "Don't Care," VIH, VIL. asynchronous input signal. When changes state, deselection read happen after cycle latency. VIL; VIH. Counter operation mask register operation independent Chip Enables.
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Master Reset
QuadPort global asynchronous master reset input, MRST. complete device reset initiated time asserting MRST LOW. master reset cycle required power-up. MRST must remain asserted least tRS. Additionally, MRST should released until power supplies fully ramped port clocks stable. Asserting MRST will have following effects: Ready deasserted (driven HIGH). address three-stated. effect JTAG/TAP signals) internal burst counter each port reset internal mirror register each port reset internal mask register each port (fully unmasked state). pipeline control registers will inactive state. mailbox burst counter interrupts will deasserted (driven HIGH). control circuitry internal delay-locked-loops (DLLs) variable impedance sense (VIS) circuitry ports will reset. circuitry each port includes delay-lock-loop (DLL) variable impedance sense (VIS). circuits require fully ramped power supply stable clock operate correctly. Releasing MRST signal QuadPort that power supplies have fully ramped port clocks stable. this time lock sequence matching procedure will commence. Each port's READY signal will asserted (LOW) when locked output impedance matched READY will asserted within 1024 clock cycles MRST's release. Releasing MRST following effects: circuit starts lock procedure. circuit starts matching output impedance. READY each port asserted within 1024 clock cycles clock respective port. both circuitry port disabled (DOFF VCC), then port's READY asserted within clock cycles. following operation commences independent READY output state. Data address outputs remain three-state, three-state control passes control pipeline. burst counter released from reset. mirror register released from reset. mask register released from preset. External control inputs allowed latch into control pipeline. mailbox burst counter interrupts released from preset.
READY Outputs
QuadPort output circuitry includes some advanced features that enhance user's interface bus. Each port includes on-board that used reduce output timing parameters. Each port also circuit that matches output driver impedance fifth external calibration resistor (0.2 RQ). user circuit match output driver impedance board trace impedance, which eliminates requirement external series match resistors. Both circuits require calibration period. Calibration cannot start before supplies each port have ramped clock inputs stable. Both circuits reset when MRST asserted. Calibration both circuits starts when MRST released. When either circuits enabled, device will fully functional until calibration period elapsed. This indicated user READY output each port. When MRST asserted (LOW), READY deasserted (HIGH). READY will asserted until both circuits have completed calibration. READY guaranteed asserted within 1024 clock cycles after MRST released. operation that results data being driven prohibited before READY asserted. other operations allowed during period between release MRST assertion READY. circuit disabled asserting DOFF. disabled connection input VDD. both circuits disabled when MRST asserted, READY will asserted within clock cycles after MRST released.
Interrupts
upper four memory locations used message passing permit communications between ports. Table shows interrupt operation ports. 2-Meg QuadPort DSE, highest memory location FFFF mailbox Port FFFE mailbox Port FFFD mailbox Port FFFC mailbox Port Table shows that order Port INTP1 flag, write other port address FFFF will assert INTP1 LOW. read FFFF location Port will reset INTP1 HIGH. When port writes other port's mailbox, Interrupt flag (INT) port that mailbox belongs asserted LOW. Interrupt reset when owner (port) mailbox reads contents mailbox. Each port read other port's mailbox without resetting interrupt. application does require message passing, pins should treated no-connect should left floating. When ports more write same mailbox same time will asserted contents mailbox guaranteed valid.
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Table Interrupt Operation Example[57] Port Function Port INTP1 Flag Reset Port INTP1 Flag Port INTP2 Flag Reset Port INTP2 Flag Port INTP3 Flag Reset Port INTP3 Flag Port INTP4 Flag Reset Port INTP4 Flag A0P1-15P1 FFFF FFFE FFFD FFFC INTP1 Port A0P2-15P2 FFFF FFFE FFFD FFFC INTP2 Port A0P3-15P3 FFFF FFFE FFFD FFFC INTP3 Port A0P4-15P4 FFFF FFFE FFFD FFFC INTP4
Note: During Master Reset control signals will deselected read state: CE0i R/Wi MKLDi MKRDi CNTRDi CNTRSTi CNTLDi CNTINCi VIH; CE1i VIL. suffix these signals denotes that these internal registered equivalent associated signals.
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Address Counter Control Operations[6]
Counter enable inputs provided stall operation address input utilize internal address generated internal counter fast interleaved memory applications. port's burst counter loaded with port's Counter Load (CNTLD). When port's Counter Increment (CNTINC) asserted, address counter will increment each transition that port's clock signal. This will read/write word from/into each successive address location until CNTINC deasserted. Depending mask register state, counter address entire memory array will loop back start. Counter Reset (CNTRST) used reset Burst Counter (the Mask Register value unaffected, unmasked bits reset). When using counter readback mode, internal address value counter will read back address lines when Counter Readback Signal (CNTRD) asserted. Figure provides block diagram readback operation. Table lists control signals required counter operations. signals listed based their priority. example, Master Reset takes precedence over Counter Reset, Counter Load lower priority than Mask Register Load (described below). counter operations independent Chip Enables (CE0 CE1).The read back address either burst counter mask register based levels Counter Read signal (CNTRD) Mask Register Read signal (MKRD). Both signals synchronized port's clock shown Table Counter read higher priority than mask read.
CNTRD MKRD
Read back Register
Addr. Read Back
MKLD Bidirectional Address Lines Mask Register
QuadPort Array
RETX CNTINC CNTLD CNTRST
Counter/ Address Register
Figure Counter Mask Register Read Back Address Lines
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Counter-Mask Register
Example: Load Counter-Mask Register CNTINT
Mask Register bit-0 Address Counter bit-0
Blocked Address Load Address Counter Address Register Address Register
Counter Address
Figure Programmable Counter-Mask Register Operation[58] burst counter mask register that controls when where counter wraps. interrupt flag (CNTINT) asserted clock cycle when unmasked portion counter address reaches maximum count (all 1s). example Figure shows counter mask register loaded with mask value 003F unmasking first bits with "15" MSB. maximum value mask register loaded with FFFF. Setting mask register this value allows counter access entire memory space. address counter then loaded with initial value XXX8. "blocked" addresses this case, address through 15th address) loaded with address increment once loaded. counter address will start address XXX8. With CNTINC asserted LOW, counter will increment internal address value till reaches mask register value wraps around memory block location XXX0. Therefore, counter uses mask-register define wrap-around point. mask register port loaded when MKLD (mask register load) that port LOW. When MKRD LOW, value mask register read address lines manner similar counter read back operation (see Table required conditions). When burst counter loaded with address higher than mask register value, higher addresses will form masked portion counter address called blocked addresses. blocked addresses will changed affected counter increment operation. only exception mask register masked allow address counter increment two. mask register loaded with logic value "0," then address counter masked changed during counter increment operation.
Note: this diagram represents counter upper-bits.
loaded value address counter "0," counter will increment address values even. loaded value address counter "1," counter will increment address values odd. This operation allows user achieve 80-bit interface using ports, where counter port counts even addresses counter other port counts addresses. This even-odd address scheme stores half 80-bit word even memory locations, other half memory locations. CNTINT will asserted when unmasked portion counter reaches maximum count. Loading mask register with allows counter increment address value sequentially. Table groups operations mask register with operations address counter. Address counter mask register signals synchronized port's clock Master reset (MRST) only asynchronous signal listed Table Signals listed based their priority going from left column right column with MRST being highest. MRST will reset counter register zeros mask register ones. other hand, CNTRST will only clear address counter register zeros mask register will remain unaffected. There four operations counter mask register: Load operation: When CNTLD MKLD LOW, address counter mask register loaded with address value presented address lines. This value ranges from FFFF (64K). mask register load operation higher priority over address counter load operation.
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Increment: Once address counter loaded with external address, counter internally increment address value asserting CNTINC LOW. counter address entire memory array (depend value mask register) loop back location increment operation second priority load operation. Readback: internal value either burst counter mask register read address lines when CNTRD MKRD LOW. Counter readback higher priority over mask register readback. Counter mask register readback have same latency memory READ operations, i.e., three cycles. address will valid after tCA2 (for counter readback) tCM2 (for mask readback) from port's third following clock rising edge. Address readback operation independent port's chip enables (CE0 CE1). address readback occurs while port enabled (chip enables active), data lines (I/Os) will three-stated, during cycle address driven from part. Hold operation: order hold value address counter certain address, signals Table have HIGH. This operation least priority. This operation useful many applications where wait states needed when address available cycles ahead data. counter mask register operations totally independent port chip enables. Test Data (TDO) output used serially clock data from registers. output active depending upon current state state machine (see Controller State Diagram (FSM)). output changes falling edge TCK. connected least significant (LSB) register. Test Reset (TRSTB) This input provides asynchronous initialization controller. According IEEE 1149.1-2001 controller shall asynchronously reset TEST-Logic_reset controller state when logic applied TRSTB. initialization independent system initialization (MRSTB). Registers Registers connected between pins allow data scanned into QuadPort test circuitry. Only register selected time through instruction registers. Data serially loaded into rising edge TCK. Data output falling edge TCK. Instruction Register Four-bit instructions serially loaded into instruction register. This register loaded when placed between pins shown following JTAG/BIST Controller diagram. Upon power-up, instruction register loaded with IDCODE instruction. also loaded with IDCODE instruction controller placed reset state described Test Reset section. When controller CaptureIR state, least significant bits loaded with binary "01" pattern allow fault isolation board level serial test path. Bypass Register save time when serially shifting data through registers, sometimes advantageous skip certain devices. bypass register single-bit register that placed between pins. This allows data shifted through QuadPort with minimal delay. bypass register (VSS) when BYPASS instruction executed. Boundary Scan Register boundary scan register connected input output pins QuadPort DSE. boundary scan register loaded with contents Input Output ring when controller Capture-DR state then placed between pins when controller moved Shift-DR state. EXTEST, SAMPLE/PRELOAD instructions used capture contents Input Output ring. Identification (ID) Register register loaded with vendor-specific, 32-bit code during Capture-DR state when IDCODE command loaded instruction register. IDCODE hardwired into QuadPort shifted when controller Shift-DR state. register vendor code other information described Identification Register Definitions table.
IEEE 1149.1 Serial Boundary Scan (JTAG)
CY7C0452/451/450/431/430V18 incorporates serial boundary scan test access port (TAP). This port operates accordance with IEEE Standard 1149.1-2001. Note that controller functions manner that does conflict with operation other devices using 1149.1 fully compliant TAPs. operates using JEDEC standard 3.3V logic levels. composed four input connections output connection required test logic defined standard. Disabling JTAG Feature possible operate QuadPort without using JTAG feature, setting TRST* ground (VSS). Test Access Port (TAP) Test Clock (TCK) test clock used only with controller. inputs captured rising edge TCK. outputs driven from falling edge TCK. Test Mode Select input used give commands controller sampled rising edge TCK. allowable leave this unconnected used. pulled internally, resulting logic HIGH level. Test Data-In (TDI) used serially input information into registers connected input registers. register between chosen instruction that loaded into instruction register. information loading instruction register, Controller State Diagram. internally pulled unconnected unused application. connected most significant (MSB) register.
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Instruction Sixteen different instructions possible with 4-bit instruction register. combinations listed Table Instruction Codes. Seven these instructions (codes) listed RESERVED should used. other nine instructions described detail below. controller used this QuadPort fully compliant 1149.1 convention. controller used load address, data control signals into QuadPort preload Input output buffers. QuadPort implements 1149.1 instructions except INTEST. Table lists instructions. Instructions loaded into controller during Shift-IR state when instruction register placed between TDO. During this state, instructions shifted through instruction register through pins. execute instruction once shifted controller needs moved into Update-IR state. EXTEST EXTEST mandatory 1149.1 instruction that executed whenever instruction register loaded with EXTEST allows circuitry external QuadPort package tested. Boundary-scan register cells output pins used apply test stimuli, while those input pins capture test results. IDCODE IDCODE instruction causes vendor-specific, 32-bit code loaded into identification register. also places identification register between pins allows IDCODE shifted device when controller enters Shift-DR state. IDCODE instruction loaded into instruction register upon power-up when-ever controller given test logic reset state. High-Z High-Z instruction causes bypass register connected between pins when controller Shift-DR state. also places QuadPort outputs into High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD 1149.1 mandatory instruction. When SAMPLE/PRELOAD instructions loaded into instruction register controller Capture-DR state, snapshot data inputs output pins captured boundary scan register. user must aware that controller clock only operate frequency MHz, while QuadPort clock operates more than order magnitude faster. Because there large difference clock frequencies, possible that during Capture-DR state, input output will undergo transition. then capture signal while transition (metastable state). This will harm device, there guarantee value that will captured. Repeatable results possible. guarantee that boundary scan register will capture correct value signal, QuadPort signal must stabilized long enough meet controller's capture set-up plus hold times. Once data captured, possible shift data putting into Shift-DR state. This places boundary scan register between pins. controller goes into Update-DR state, sampled data will updated. BYPASS When BYPASS instruction loaded instruction register placed Shift-DR state, bypass register placed between pins. advantage BYPASS instruction that shortens boundary scan path when multiple devices connected together board. CLAMP optional CLAMP instruction allows state signals driven from QuadPort pins determined from boundary-scan register while BYPASS register selected serial path between TDO. CLAMP controls boundary cells
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Controller State Diagram (FSM)[59]
TEST-LOGIC RESET SELECT IR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR EXIT2-IR UPDATE-IR CAPTURE-IR SHIFT-IR EXIT1-IR PAUSE-IR
RUN_TEST/ IDLE
SELECT DR-SCAN
Note: next each state represents value rising edge TCK.
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Bypass Register (BYR) Instruction Register (IR) Selection Circuitry (MUX)
Identification Register (IDR) Register Register Boundary Scan Register (BSR)
CONTROLLER
TRST
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Table Scan Registers Sizes Register Name Bypass (BYR) Instruction (IR) Identification (IDR) Electrical Identification Register (EID) Variable Impedance Register (VIS) Boundary Scan (BSR) Table Instruction Identification Codes Instruction Bypass Sample/Preload Extest[60] Idcode Clamp[60] Highz
[60]
Size
Code 1111 1000 0000 1011 0100 0111 0001
Description Places bypass register (BYR) between TDO. Captures Input/Output ring contents. Places boundary scan register (BSR) between TDO. Captures Input/Output ring contents. Places boundary scan register (BSR) between TDO. Loads register (IDR) with vendor code places register between TDO. Controls boundary 1/0. Uses BYR. Places between TDO. Forces QuadPort output drivers High-Z state. Allows testing on-chip system logic while component assembled board. test stimuli shifted time applied on-chip system logic. Loads Electrical Identification Register (EID) with vendor Electrical code places register between TDO. Loads Variable Impedance Register (VIS) with vendor code places register between TDO.
Intest[60]
Eidcode
1001 1010
Note: Instruction that requires master reset after completion before using chip normal mode
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CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18
Ordering Information
128K 1.8V Synchronous QuadPort Speed (MHz) Speed (MHz) Speed (MHz) Speed (MHz) Speed (MHz) Ordering Code CY7C0452V18-167BBI CY7C0452V18-167BBC CY7C0452V18-133BBI CY7C0452V18-133BBC CY7C0452V18-100BBC 1.8V Synchronous QuadPort Ordering Code CY7C0451V18-167BBI CY7C0451V18-167BBC CY7C0451V18-133BBI CY7C0451V18-133BBC CY7C0451V18-100BBC 1.8V Synchronous QuadPort Ordering Code CY7C0450V18-167BBC CY7C0450V18-133BBC CY7C0450V18-100BBC Package Name BB676 BB676 BB676 Package Name BB676 BB676 BB676 BB676 Package Name BB676 BB676 BB676 Package Type Operating Range Package Name BB676 BB676 BB676 BB676 BB676 Package Type Operating Range Package Name BB676 BB676 BB676 BB676 BB676 Package Type Operating Range
Ball Grid Array (BGA) 1.0-mm pitch Industrial Ball Grid Array (BGA) 1.0-mm pitch Commercial Ball Grid Array (BGA) 1.0-mm pitch Industrial Ball Grid Array (BGA) 1.0-mm pitch Commercial Ball Grid Array (BGA) 1.0-mm pitch Commercial
Ball Grid Array (BGA) 1.0-mm pitch Industrial Ball Grid Array (BGA) 1.0-mm pitch Commercial Ball Grid Array (BGA) 1.0-mm pitch Industrial Ball Grid Array (BGA) 1.0-mm pitch Commercial Ball Grid Array (BGA) 1.0-mm pitch Commercial
Ball Grid Array (BGA) 1.0-mm pitch Commercial Ball Grid Array (BGA) 1.0-mm pitch Commercial Ball Grid Array (BGA) 1.0-mm pitch Commercial Operating Range
128K 1.8V Synchronous QuadPort Ordering Code CY7C0431V18-167BBI CY7C0431V18-167BBC CY7C0431V18-133BBC CY7C0431V18-100BBC Package Type
Ball Grid Array (BGA) 1.0-mm pitch Industrial Ball Grid Array (BGA) 1.0-mm pitch Commercial Ball Grid Array (BGA) 1.0-mm pitch Commercial Ball Grid Array (BGA) 1.0-mm pitch Commercial Operating Range
1.8V Synchronous QuadPort Ordering Code CY7C0430V18-167BBC CY7C0430V18-133BBC CY7C0430V18-100BBC Package Type
Ball Grid Array (BGA) 1.0-mm pitch Commercial Ball Grid Array (BGA) 1.0-mm pitch Commercial Ball Grid Array (BGA) 1.0-mm pitch Commercial
Document 38-06065 Rev.
Page
CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18
Package Diagram
676-Ball FBGA BB676
51-85125-*B
QuadPort trademark Cypress Semiconductor Corporation. product company names mentioned this document trademarks their respective holders.
Document 38-06065 Rev.
Page
Cypress Semiconductor Corporation, 2002. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
CY7C0452V18/0451V18/0450V18 PRELIMINARY CY7C0431V18/0430V18
Document Title: QuadPortDatapath Switching Element (DSE) Family Document Number: 38-06065 REV. 117356 Issue Date 08/02/02 Orig. Change Data Sheet Description Change
Document 38-06065 Rev.
Page

QuadPortDatapath Switching Element (DSE) Family QuadPortDatapath

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