AS7C33512NTD32A AS7C33512NTD36A 65$0 ZLWK 17' Organization:

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AS7C33512NTD32A AS7C33512NTD36A 65$0 ZLWK 17' Organization:

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AS7C33512NTD32A AS7C33512NTD36A
65$0 ZLWK 17'
Organization: 524,288 words bits NTDTM1 architecture efficient operation Fast clock speeds LVTTL/LVCMOS Fast clock data access: 2.6/2.8/3/3.4 Fast access time: 2.6/2.8/3/3.4 Fully synchronous operation Flow-through pipelined mode Asynchronous output enable control
NTDis trademark Alliance Semiconductor Corporation.
Available 100-pin TQFP 165-ball package Byte write enables Clock enable operation hold Multiple chip enables easy expansion 3.3V core power supply 2.5V 3.3V operation with separate VDDQ Self-timed write cycles Interleaved linear burst modes Snooze mode standby operation
Logic block diagram
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Selection guide
-250 Minimum cycle time Maximum pipelined clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
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Units
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ball assignment 165-ball view
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ADV/LD
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least significant bits (LSB) address field internal burst counter burst desired.
100-pin TQFP view
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Functional description
AS7C33512NTD32A/36A family high performance CMOS Mbit synchronous Static Random Access Memory (SRAM) organized 524,288 words bits incorporates LATE LATE Write. This variation 16Mb+ synchronous SRAM uses Turnaround Delay (NTDTM) architecture, featuring enhanced write operation that improves bandwidth over pipelined burst devices. normal pipelined burst device, write data, command, address applied device same clock edge. read command follows this write command, system must wait 'dead' cycles valid data become available. These dead cycles significantly reduce overall bandwidth applications requiring random access read-modifywrite operations. NTDdevices memory more efficiently introducing write latency which matches two-cycle pipelined one-cycle flowthrough read latency. Write data applied cycles after write command address, allowing read pipeline clear. With NTDTM, write read operations used order without producing dead cycles. Assert perform write cycles. Byte write enable controls write access specific bytes, tied full writes. Write enable signals, along with write address, registered rising edge clock. Write data applied device clock cycles later. Unlike some asynchronous SRAMs, output enable does need toggled write operations; tied normal operations. Outputs high impedance state when device de-selected three chip enable inputs. pipelined mode, cycle deselect latency allows pending read write operations completed. (burst advance) input perform burst read, write deselect operations. When high, external addresses, chip select, pins ignored, internal address counters increment count sequence specified control. device operations, including burst, stalled using CEN=1, clock enable input. AS7C33512NTD32A/36A operates with 3.3V power supply device core (VDD). circuits separate power supply (VDDQ) that operates across 3.3V 2.5V ranges. These devices available 100-pin TQFP package Ball Grid Array package.
Capacitance
Parameter Input capacitance capacitance Symbol CI/O pins Signals Address control pins Test conditions Vout Unit
Burst order
Interleaved burst order Starting address First increment Second increment Third increment Starting Address First increment Second increment Third increment Linear burst order
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Signal descriptions
Signal DQ[a,b,c,d] CE0, CE1, ADV/LD BW[a,b,c,d] Properties Description CLOCK SYNC SYNC SYNC SYNC SYNC SYNC SYNC ASYNC STATIC STATIC SYNC SYNC SYNC SYNC ASYNC Clock. inputs except LBO, synchronous this clock. Clock enable. When de-asserted high, clock input signal masked. Address. Sampled when chip enables active ADV/LD asserted. Data. Driven output when chip enabled active. Synchronous chip enables. Sampled rising edge CLK, when ADV/LD asserted. ignored when ADV/LD high. Advance Load. When sampled high, internal burst address counter will increment order defined input value. (refer table page When low, address loaded. high during LOAD initiates READ operation. during LOAD initiates WRITE operation. ignored when ADV/LD high. Byte write enables. Used control write individual bytes. Sampled along with WRITE command BURST WRITE. Asynchronous output enable. pins driven when inactive. Count mode. When driven high, count sequence follows Intel convention. When driven low, count sequence follows linear convention. This input should static when device operation. Flow-through mode.When low, enables single register flow-through mode. Connect unused pipelined operation. Serial data-out JTAG circuit. Delivers data negative edge TCK. (BGA only) Serial data-in JTAG circuit. Sampled rising edge TCK. (BGA only) This controls Test Access Port state machine. Sampled rising edge TCK. (BGA only) Serial data-out JTAG circuit. Delivers data negative edge TCK. (BGA only) Snooze. Places device power mode; data retained. Connect unused. connects.
Absolute maximum ratings
Parameter Power supply voltage relative Input voltage relative (input pins) Input voltage relative (I/O pins) Power dissipation output current Storage temperature (plastic) Temperature under bias (junction) Symbol VDD, VDDQ IOUT Tstg Tbias -0.5 -0.5 -0.5 +4.6 VDDQ +150 +150 Unit
Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only, functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect reliability.
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Synchronous truth table
ADV/LD BW[a,b] Address source External External Burst counter Stall Operation Deselect, high-Z Deselect, high-Z Deselect, high-Z Begin read Begin write Burst2 Inhibit
Should burst write, unless specific bytes need inhibited Refer state diagram below. Key: don't care, low, high
State diagram SRAM
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Recommended operating conditions
Parameter Supply voltage 3.3V supply voltage 2.5V supply voltage Address control pins pins Ambient operating temperature Symbol VDDQ GNDQ VDDQ GNDQ 3.135 2.375 2.35 -0.5 -0.52
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Nominal
3.465 3.465 2.65 VDDQ
Unit
Input voltages
Input voltage ranges apply 3.3V operation. 2.5V operation, contact factory input specifications. -2.0V pulse width less than tRC.
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electrical characteristics 3.3V operation
Parameter Input leakage current Output leakage current Operating power supply current2
Test conditions VIH, Max, Vout VIL, VIH, VIL, fmax, Iout Deselected, fmax Deselected, 0.2V 0.2V Deselected, fMax, 0.2V, VDDQ 3.6V VDDQ 3.0V
Unit
Max,
Standby power supply current
ISB1 ISB2
Output voltage
LBO, FTX, pins JTAG pins (TMSX, TDIX, TCKX) have internal pull-up, input leakage given with output loading. increases with faster cycle times greater output loading.
electrical characteristics 2.5V operation
Parameter Output leakage current Output voltage
Test conditions VIH, Max, Vout VDDQ 2.65V VDDQ 2.35V
Unit
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Timing characteristics over operating range
Parameter Clock frequency Cycle time (pipelined mode) Cycle time (flow-through mode) Clock access time (pipelined mode) Clock access time (flow-through mode) Output enable data valid Clock high output Data output invalid from clock high Output enable output Output enable high output high Clock high output high Clock high output high Clock high pulse width Clock pulse width Address Control setup clock high Data setup clock high Write setup clock high Chip select setup clock high Address hold from clock high Data hold from clock high Write hold from clock high Chip select hold from clock high Clock enable setup clock high Clock enable hold from clock high setup clock high hold from clock high
"Notes" page
FMAX tCYC tCYCF tCDF tLZC tLZOE tHZOE tHZC tHZCN tCSS tCSH tCENS tCENH tADVS tADVH
Unit
Notes1
2,3,4 2,3,4 2,3,4 2,3,4
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IEEE 1149.1 serial boundary scan (JTAG)
SRAM incorporates serial boundary scan test access port (TAP). port operates accordance with IEEE Standard 1149.1-1990 does have functions required full 1149.1 compliance. inclusion these functions would place added delay critical speed path SRAM. controller functionality does conflict with operation other devices using 1149.1 fully compliant TAPs. uses JEDEC-standard 2.5V logic levels. SRAM contains controller, instruction register, boundary scan register, bypass register, register.
Disabling JTAG feature
JTAG function being implemented, pins/balls left unconnected. power-up, device will come reset state which will interfere with operation device.
controller state diagram
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controller block diagram
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Test access port (TAP) Test clock (TCK)
test clock used with only controller. inputs captured rising edge TCK. outputs driven from falling edge TCK.
Test mode select (TMS)
controller receives commands from input. sampled rising edge TCK. leave this pin/ball unconnected used. pin/ball pulled internally, resulting logic high level.
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Test data-in (TDI)
pin/ball serially inputs information into registers connected input registers. register between chosen instruction that loaded into instruction register. information loading instruction register, Controller State Diagram. internally pulled unconnected unused application. connected most significant (MSB) register.
Test data-out (TDO)
output pin/ball serially clocks data-out from registers. output active depending upon current state state machine. output changes falling edge TCK. connected least significant (LSB) register. (See Controller State Diagram.)
Performing RESET
perform RESET forcing high (VDD) five rising edges TCK. This RESET does affect operation SRAM performed while SRAM operating. power-up, reset internally ensure that comes high-Z state.
registers
Registers connected between pins/balls. They allow data scanned into SRAM test circuitry. Only register selected time through instruction register. Data serially loaded into pin/ball rising edge TCK. Data output pin/ball falling edge TCK.
Instruction register
serially load three-bit instructions into instruction register. register loaded when placed between pins/ balls shown Controller Block Diagram. instruction register loaded with IDCODE instruction power also controller placed reset state, described previous section. When controller Capture-IR state, least significant bits loaded with binary "01" pattern allow fault isolation board-level series test data path.
Bypass register
save time when serially shifting data through registers, sometimes advantageous skip certain chips. bypass register single-bit register that placed between pins/balls. This allows data shifted through SRAM with minimal delay. bypass register (Vss) when BYPASS instruction executed.
Boundary scan register
boundary scan register connected input bidirectional pins/balls SRAM. configuration 70-bit-long register configuration 51-bit-long register. boundary scan register loaded with contents ring when controller Capture-DR state then placed between pins/balls when controller moved Shift-DR state. EXTEST, SAMPLE/RELOAD, SAMPLE instructions used capture contents ring. boundary scan order table shows order which bits connected. Each corresponds bumps SRAM package. most significant (MSB) register connected TDI, least significant (LSB) connected TDO.
Identification (ID) register
register vendor code other information described Identification register definitions table. register loaded with vendor-specific, 32-bit code during Capture-DR state when IDCODE command loaded instruction register. IDCODE hardwired into SRAM shifted when controller Shift-DR state.
instruction
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Eight different instructions possible with 3-bit instruction register. combinations listed Instruction Codes table. Three these instructions reserved should used. Note that controller used this SRAM fully compliant 1149.1 convention because some mandatory 1149.1 instructions fully implemented. controller cannot used load address, data, control signals into SRAM cannot preload buffers. SRAM does implement 1149.1 commands EXTEST INTEST PRELOAD portion SAMPLE/ PRELOAD. Instead, performs capture ring when these instructions executed. Instructions loaded into controller during Shift-IR state when instruction register placed between TDO. During this state, instructions shifted through instruction register through pins/balls. execute instruction once shifted controller needs moved into Update-IR state.
EXTEST
EXTEST instruction, which executes whenever instruction register loaded with implemented this SRAM controller. controller, however, does recognize all-0 instruction. When EXTEST instruction loaded into instruction register, SRAM responds SAMPLE/PRELOAD instruction been loaded. Unlike SAMPLE/PRELOAD instruction, EXTEST places SRAM outputs high-Z state. EXTEST mandatory 1149.1 instruction. this device, therefore, compliant with 1149.1.
IDCODE
IDCODE instruction loaded into instruction register upon power-up whenever controller given test logic reset state. IDCODE instruction causes vendor-specific, 32-bit code loaded into instruction register. also places instruction register between pins/balls allows IDCODE shifted device when controller enters Shift-DR state.
SAMPLE
SAMPLE instruction causes boundary scan register connected between pins/balls when controller Shift-DR state. also places SRAM outputs into high-Z state.
SAMPLE/PRELOAD
When SAMPLE/PRELOAD instruction loaded into instruction register controller Capture-DR state, snapshot data inputs bidirectional pins/balls captured boundary scan register. Note that SAMPLE/PRELOAD 1149.1 mandatory instruction, PRELOAD portion this instruction implemented this device. controller, therefore, fully 1149.1 compliant. aware that controller clock operate only frequency Mhz, while SRAM clock operates more than order magnitude faster. Because there large difference clock frequencies, possible that during Capture-DR state, input output undergo transition. then capture signal while transition (metastable state). This will harm device, there guarantee value that will captured. Repeatable results possible. guarantee that boundary scan register captures correct value signal, SRAM signal must stabilized long enough meet controller's capture setup plus hold time (tCS plus tCH). SRAM clock input might captured correctly there design stop slow) clock during SAMPLE/PRELOAD instruction. this issue, possible capture other signals ignore value captured bounder scan register. Once data captured, possible shift data putting into Shift-DR state. This places boundary scan register between pins. Note that since PRELOAD part command implemented, putting Update-DR state while performing SAMPLE/ PRELOAD instruction will have same effect Pause-DR command.
BYPASS
advantage BYPASS instruction that shortens boundary scan path when multiple devices connected together board. When BYPASS instruction loaded instruction register placed Shift-DR state, bypass register placed between TDO.
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Reserved
reserved instruction.These instructions implemented reserved future use.
timing diagram
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electrical characteristics
notes +10oC +110oC +2.4V +2.6V.
Description Clock Clock cycle time Clock frequency Clock high time Clock time Output Times unknown valid valid high high invalid Setup Times setup Capture setup Hold Times hold Capture hold
Symbol tTHTH tTHTL tTLTH tTLOX tTLOV tDVTH tTHDX tMVTH
Units
tTHMX
refer setup hold time requirements latching data from boundary scan register.
Test conditions specified using load figure output
load equivalent.
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test conditions
Input pulse levels. 2.5V Input rise fall times. Input timing reference levels. 1.25V Output reference levels 1.25V Test load termination supply voltage. 1.25V
output load equivalent
3.3V VDD, electrical characteristics operating conditions
(+10oC +110oC +3.135V +3.465V unless otherwise noted)
Description Input high (logic voltage Input (logic voltage Input leakage current Output leakage current Output voltage Output voltage Output high voltage Output high voltage
Conditions
Symbol
-0.3 -5.0 -5.0
Units
Notes
Outputs disabled, VDDQ(DQx) IOLC 100µA IOLT IOHS -100µA IOHT -2mA
VOL1 VOL2 VOH1 VOH2
2.5V VDD, electrical characteristics operating conditions
(+10oC +110oC +2.4V +2.6V unless otherwise noted)
Description Input high (logic voltage Input (logic voltage Input leakage current Output leakage current Output voltage Output voltage Output high voltage Output high voltage
voltage referenced VSS(GND).
Conditions
Symbol
-0.3 -5.0 -5.0
Units
Notes
Outputs disabled, VDDQ(DQx) IOLC 100µA IOLT IOHS -100µA IOHT -2mA
VOL1 VOL2 VOH1 VOH2
Overshoot: VIH(AC) 1.5V tKHKH/2 Undershoot:VIL(AC) -0.5 tKHKH/2 Power-up: +2.6V 2.4V VDDQ 1.4V 200ms During normal operation, VDDQ must exceed VDD. Control input signals (such R/W, etc.) have pulsed widths less than tKHKL(Min) operate frequencies exceeding fKF(Max).
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Identification register definitions
Instruction field Revision number (31:28) Device depth (27:23) Device width (22:18) Device (17:12) JEDEC code (11:1) register presence indicator 512K 32/36 xxxx Description Reserved version number.
xxxxx/xxxxx Defines depth 512K words. xxxxx/xxxxx Defines width bits. xxxxxx Reserved future use. Indicates presence register. 00000110100 Allows unique identification SRAM vendor.
Scan register sizes
Register name Instruction Bypass Boundary scan x18:51 size x36:70
Instruction codes
Instruction EXTEST IDCODE SAMPLE Reserved SAMPLE/PRELOAD Reserved Reserved BYPASS Code Description Captures ring contents. Places boundary scan register between TDO. Forces SRAM outputs high-Z state. This instruction 1149.1-compliant. Loads register with vendor code places register between TDO. This operation does affect SRAM operations. Captures ring contents. Places boundary scan register between TDO. Forces SRAM output drivers high-Z state. use. This instruction reserved future use. Captures ring contents. Places boundary scan register between TDO. Does affect SRAM operation. This instruction does implement 1149.1 preload function therefore 1149.1-compliant. use. This instruction reserved future use. use. This instruction reserved future use. Places bypass register between TDO. This operation does affect SRAM operations.
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165-ball boundary scan order (x36)
Signal Name DQPa DQPb ADV/LD Ball Signal Name DQPc DQPd Ball
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switching waveforms
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Timing waveform read/write cycle
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NOP, stall deselect cycles
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test conditions
Output load: tLZC, tLZOE, tHZOE, tHZC, Figure others, Figure Input pulse level: Figure Input rise fall time (measured 0.3V 2.7V): Figure Input output timing reference levels: 1.5V.
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Notes
test conditions, test conditions", Figures This parameter measured with output load condition Figure This parameter sampled, 100% tested. tHZOE less than tLZOE, tHZC less than tLZC given temperature voltage. measured high above VIH, measured below This synchronous device. addresses must meet specified setup hold times rising edges CLK. other synchronous inputs must meet setup hold times with stable logic levels rising edges when chip enabled. Write refers BW[a,b,c,d]. Chip select refers CE0, CE1, CE2.
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Package dimensions 100-pin quad flat pack (TQFP)
TQFP 0.05 0.15 1.35 1.45 0.22 0.38 0.09 0.20 13.90 14.10 19.90 20.10 0.65 nominal 15.90 16.10 21.90 22.10 0.45 0.75 1.00 nominal
Dimensions millimeters
165-ball (ball grid array)
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Ordering information
Package Width
-250 AS7C33512NTD32A250TQC
-225 AS7C33512NTD32A225TQC AS7C33512NTD32AA225TQI AS7C33512NTD36A225TQC AS7C33512NTD36A225TQI AS7C33512NTD32A225BC AS7C33512NTD32A225BI AS7C33512NTD36A225BC AS7C33512NTD36A225BI
-200 AS7C33512NTD32A200TQC AS7C33512NTD32A200TQI AS7C33512NTD36A200TQC AS7C33512NTD36A200TQI AS7C33512NTD32A200BC AS7C33512NTD32A200BI AS7C33512NTD36A200BC AS7C33512NTD36A200BI
-166 AS7C33512NTD32A166TQC AS7C33512NTD32A166TQI AS7C33512NTD36A166TQC AS7C33512NTD36A166TQI AS7C33512NTD32A166BC AS7C33512NTD32A166BI AS7C33512NTD36A166BC AS7C33512NTD36A166BI
TQFP
TQFP
AS7C33512NTD36A250TQC
AS7C33512NTD32A250BC
AS7C33512NTD36A250BC
Part numbering guide
AS7C 32/36 -XXX
Alliance Semiconductor SRAM prefix Operating voltage: 3.3V Organization: 512k NTD= Turn-Around Delay. Pipelined/flow-through mode (each device works both modes) Organization: Production version: first production version Clock speed (MHz) Package type: TQFP; Operating temperature: commercial industrial (-40°
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Copyright Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights, mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components life-supporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such life-supporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use.

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