C35B3 (0.35um) DESCRIPTION ADC1220 high-speed pipeline core

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C35B3 (0.35um) DESCRIPTION ADC1220 high-speed pipeline core

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ANALOG BLOCK ADC1220 CMOS 12-Bit Pipelined CONVERTER
C35B3 (0.35um)
DESCRIPTION
ADC1220 high-speed pipeline core cell achieving sampling rates MS/s. circuit built-in provide jitter noise fully differential input. reference voltages internally generated from bandgap reference that must supplied cell must supplied externally cell. power down capability included very power dissipation stand-by mode.
FEATURES
Small Area: 3.87 Size 2261.5 1711.55 Supply Voltage Junction Temp. Range: +125 Resolution 12-Bit Maximum Sampling Rate MS/s Sample Hold Input Stage Input Signal Range Fully Differential Input Power Dissipation Power Down Mode
VDDA SWIB
VDDA2
SVDDA
SVDDD
VDDD2
VDDD IB_EXT
Bias Current Generation ONADC
ONREF VBYSHP VBYSHN VINP VINN CTRSH EN8, EN16 LWJIT CLKIN GNDA GNDA2 SGNDA SGNDD GNDD2 GNDD Timing Generation Pipeline Digital Error Correction Output Register REF. GEN.
VREFP VREFN
CLKOUT
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Datasheet ADC1220
TECHNICAL DATA
(Tjunction VDDA +3.0 +3.6 fclk MHz, VDDA/2, VREFP VREFN specified, unless otherwise specified)
ACCURACY
Symbol GAINERR Parameter Resolution missing Code) Differential Linearity Error Integral Linearity Error Offset Error Gain Error Conditions -0.9 -2.0 ±0.5 ±0.5 +2.0 Units
REFERENCE CHARACTERISTICS
Symbol VREFP VREFN VREF Rrefp Crefp Rrefn Crefn Parameter ext. Bandgap Reference Voltage Common Mode Voltage Pos. Reference Voltage Neg. Reference Voltage Difference between VREFP VREFN ext. Bandgap Ref. Impedance ext. Bandgap Ref. Input Current Comm. Mode Impedance Pos. Reference Impedance (For external VREF generation) Neg. Reference Impedance (For external VREF generation) Op.Mode Op.Mode Op.Mode Op.Mode Op.Mode Conditions Op.Mode 1.25 VDDA/2 VCM+0.4VBG VCM-0.4VBG
1.875
Units
48.0 239.0
ANALOG INPUT
Symbol Vind Finmax Max. Input Signal Frequency Parameter Diff. Input Voltage Range, related Input Impedance Conditions -VREF VREF Units
input signal range. input signal range. 1.25 VDDA 1.875 VDDA strongly recommended overdrive inputs ADC1220.
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Datasheet ADC1220
ACCURACY input signal range)
Symbol SFDR SFDR SFDR SINAD SINAD SINAD ENOB ENOB ENOB TT-IMD TT-SFDR FPBW Parameter Total Harmonic Distortion Total Harmonic Distortion Total Harmonic Distortion Spurious Free Dynamic Range Spurious Free Dynamic Range Spurious Free Dynamic Range Signal Noise Ratio Signal Noise Ratio Signal Noise Ratio Signal (Noise+Dist.) Ratio Signal (Noise+Dist.) Ratio Signal (Noise+Dist.) Ratio Effective Number Bits Effective Number Bits Effective Number Bits Two-Tone third order Intermodulation Distortion Two-Tone Spurious Free Dynamic Range Full Power Bandwidth Conditions fin1 fin2
-83.00 -83.00 -81.50 80.50 80.00 76.00 68.80 67.50 66.00 68.70 67.40 65.85 11.10 10.90 10.65 -80.00 77.80
Units
fin1 fin2
ACCURACY input signal range)
Symbol SFDR SFDR SFDR SINAD SINAD SINAD ENOB ENOB ENOB TT-IMD TT-SFDR FPBW Parameter Total Harmonic Distortion Total Harmonic Distortion Total Harmonic Distortion Spurious Free Dynamic Range Spurious Free Dynamic Range Spurious Free Dynamic Range Signal Noise Ratio Signal Noise Ratio Signal Noise Ratio Signal (Noise+Dist.) Ratio Signal (Noise+Dist.) Ratio Signal (Noise+Dist.) Ratio Effective Number Bits Effective Number Bits Effective Number Bits Two-Tone third order Intermodulation Distortion Two-Tone Spurious Free Dynamic Range Full Power Bandwidth Conditions fin1 fin2 =4.5
-82.60 -78.90 -76.40 82.40 80.30 76.60 70.40 68.50 66.50 70.10 68.10 66.00 11.35 11.00 10.67 -75.50 75.50
Units
fin1 fin2
Both signals, fin1 fin2, have amplitude full scale
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Datasheet ADC1220
DIGITAL INPUTS OUTPUTS
Symbol B[11:0] Parameter Pos. digital Supply Voltage Neg. digital Supply Voltage Digital Input Level Digital Output Level Output Code Vind -VREF Vind VREF Conditions VDDA GNDA Units
POWER REQUIREMENTS
Symbol VDDA VSSA IDDD IDDA Psup Pdiss_tot
Parameter Pos. analog Supply Voltage Neg. analog Supply Voltage Supply Current Digital Supply Current Analog Supply Power Consumption Total Power Dissipation Powerup Mode Supply Current Digital Supply Current Analog Supply Power Consumption Reference Current Total Power Dissipation Powerup Mode Power Consumption Power Down Mode
Conditions VDDA GNDA Mode Mode Mode Mode
111.7
223.4
Units
IDDD IDDA Psup IREF
Mode Mode Mode Mode Mode
Pdiss_tot
Pdiss_pd
Mode
TIMING CHARACTERISTICS
Symbol fclk 1/Ts Jclk Tclkd Parameter Frequency Sampling Rate Clock Jitter Clock falling edge sampling instant delay Clock falling edge data delay Input Clock falling edge output Clock delay Clock duty cycle Data Latency Power Delay 10.5 47.5 52.5 Conditions fclk Units MS/sec psec nsec nsec nsec cycle cycle
Mode (internal references) with VREF clock frequency. Mode (external references) with VREF clock frequency. After power down. digital output codes valid during first clock cycles after power
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Datasheet ADC1220
TYPICAL PERFORMANCE CHARACTERISTICS
VDDA +3.3 fclk MHz, 1.25 VDDA/2, Mode unless otherwise specified)
[LSB]
Digital Code
[LSB]
Digital Code
[dBc]
Input Signal Frequency [Hz]
[dBc]
Input Signal Frequency [Hz]
Spectrum
Spectrum
Input Signal Frequency [Hz]
ENOB [Bit]
[dBc]
Input Signal Frequency [Hz]
Two-Tone
ENOB Input Signal Frequency
spectrum consists 16384 pins. Measured with band-pass filter Measured with low-pass filter.
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Datasheet ADC1220
SYMBOL
PINLIST
VINP VINN VBYSHP VBYSHN VREFP VREFN IB_EXT Function Pos. Input Voltage Neg. Input Voltage Bypass Pos. Input Voltage Bypass Neg. Input Voltage Input Common Mode Voltage Output bypass Internal Pos. Reference Voltage Output bypass Internal Neg. Reference Voltage Input Bandgap Reference Voltage Output monitoring internal bias current generation when SWIB input injection external bias current (10µA) when SWIB CLKIN CLKOUT ONADC ONREF Clock Input Clock Output Digital Output Bits (B11 MSB, LSB) Power Down Input (ONADC normal operation) Power Down Input Reference Generator (ONREF normal operation) CTRSH SWIB Power Down Bypass (CTRSH normal operation) Bias current control pin; High, uses internal bias current; otherwise enables external current input. Jitter Reduction (LWJIT normal operation) EN16 VDDA GNDA VDDA2 VGNDA2 SVDDA SGNDA VDDD GNDD VDDD2 GNDD2 SVDDD SGNDD Enables Decimation factor (EN8 normal operation) Enables Decimation factor (EN16 normal operation) Analog pos. Power Supply Analog neg. Power Supply Secondary pos. Analog Power Supply Secondary neg. Analog Power Supply Substrate pos. Analog Power Supply Substrate neg. Analog Power Supply Digital pos. Power Supply Digital neg. Power Supply Secondary Digital pos. Power Supply Secondary Digital neg. Power Supply Substrate Digital pos. Power Supply Substrate Digital neg. Power Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Digital Digital Digital Digital Digital Digital Digital Digital Digital Type Analog Analog Analog Analog Analog Analog Analog Analog Analog
THEORY OPERATION
ADC1220 low-power 12-bit capable sampling MS/s. uses fully differential pipelined architecture with first 3.5-bit stage, followed seven 1.5-bit stage digital error correction achieve improved linearity performance. dedicated wide-band input sampleand-hold amplifier (S/H) built-in provide lowjitter, sub-sampling capability with inherent frequency down-conversion fully differential input. digital words synchronized chain delay stages overlapped processed digital error correction logic produce 12-bit digital output code.
LWJIT
Digital
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Datasheet ADC1220
OPERATING MODES
modes operation summarized table bellow, described detail follows.
Configuration
Mode Objective Complete Power Down Normal conversion Normal conversion with external VREF Normal conversion with external Ibias Normal conversion with external VREF Ibias Modes with bypass Modes with decimation factor Modes with decimation factor Modes with clock jitter reduction ONADC SWIB ONREF CTRSH EN16 LWJIT
Mode Power Down
this mode circuitry power-down. power dissipation reduced minimum value.
Mode Normal Conversion
This normal conversion mode converter. external bandgap reference voltage determines values reference voltages VREFP VREFN. bias current internally generated reference voltages internally buffered. common mode voltage must supplied externally.
Mode through Mode Conversion Mode with different Bypassing options
These conversion modes allow different bypassing options bias current generator, buffer reference voltage S&H. case bypass input signal must fully differential because pipeline fully differential architecture.
Modes Conversion Mode with different Decimation factors
These conversion modes allow output data decimation factors with previous modes, order reduce digital Output Pads switching noise.
Mode Conversion Mode with Clock jitter reduction
This conversion mode allows test internal clock with reduced jitter with previous modes.
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Datasheet ADC1220
POWER SUPPLIES
converter requires single +3.3 power supply. supplies analog digital separated. maximum noise immunity recommended wire them chip separated pins, especially when block embedded large digital circuit. supplies then connected together PC-board level. proper blocking capacitors application important!
REFERENCE VOLTAGES
ONREF high converter needs external bandgap reference that defines dynamic range input signal described technical data section. ONREF external voltage references VREFP VREFN define dynamic range input signal. proper blocking capacitors application important!
SYSTEM REQUIREMENTS
sensitive ground noise. parts whole system except should quiet during conversions. minimize ground noise coming from digital output pads connection series resistor should used limit switching current. test circuit series resistor used digital output bus.
CONVERSION MODE
Fully Differential Mode
recommended ADC1220 Fully Differential Converter. Both inputs VINP VINN should balanced around VCM.
CODE TABLES
digital representation data both conversion modes described following table.
VREF VREFP VREFN
1LSB
VREFP VREFN 4096
Offset Binary
Output Code 1111 1111 1111
Input Voltage: VIN-VINB 2047 VREF
1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000
2046 2047 -2047 -2046 -VREF -2047
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Datasheet ADC1220
FUNCTIONAL BLOCK DIAGRAM
MDAC
MDAC
MDAC
MDAC
MDAC
MDAC
MDAC
MDAC
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
Digital Error Correction Logic
TIMING DIAGRAM ADC1220
sampling rate ADC1220 defined frequency signal. input signal voltage sampled falling edge CLK. conversion stages operate staggered fashion alternate phases CLK, duty-cycle this signal must 50%. results latched output register falling edge CLK, with latency periods. conversion timing shown Diagram
Cycle
Stage (S&H) Stage Stage
Sample X0(1)
Hold X1(1)
Sample X0(2)
Hold X1(2)
Sample X0(8)
Hold X1(8)
Sample X0(9)
Hold X1(9)
Sample Quant. X1(1)
Amplification X2(1) Sample Quant. X2(1)
Sample Quant. X1(2) Amplification X3(1)
Amplification X2(7) Sample Quant. X2(7)
Sample Quant. X1(8) Amplification X3(7)
Amplification X2(8) Sample Quant. X2(8)
Sample Quant. X1(9) Amplification X3(8)
Stage Digital Output
Latency cycles
Sample Quant. X9(1)
Sample Quant. X9(2)
b[X(1)]
Diagram Timing pipelining operation
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Datasheet ADC1220
Diagram presents timing CLKOUT signal normal operation (mode with decimation factors (mode (mode test modes that have decimation factor specified, CLKOUT signal identical that normal operation mode.
Timing Diagram Timing CLKOUT signal operation normal operation with decimation factor
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Datasheet ADC1220
TYPICAL APPLICATION
ADC1220 targeted general purpose sampling functions where high-speed conversion rates medium precision critical importance.
1)2)3)4)
APPLICATION
VDDD CPK1
Video Imaging Data acquisition systems High-speed data transmission Communications
VDDA VDDD
+3.3V
+3.3V VDDA
CPK1
10uF
100nF
100pF
CPK1
VSSA
VSSD
CPK2
3.3uF
100nF
100pF
B<11:0>
VDDD
1.65V
CPK2
200pF
200pF
1.25V
CPK2
20MHz
VSSA GROUND
VSSD
Configuration: Mode MS/sec, input signal range
+3.3V
+3.3V VDDA VDDD CPK1
CPK2
3.3uF
100nF
100pF
CPK1
10uF
100nF
100pF
VDDA VDDD
CPK1
VSSA
VSSD 10uA
CPK2
B<11:0>
VDDD
2.4V
CPK2
0.9V
CPK2
1.65V
CPK2
200pF
200pF
CPK2
20MHz
VSSA
VSSD
GROUND
Configuration: Mode MS/sec, input signal range
value capacitor depends input frequency. capacitors type normal capacitors type best performance. capacitors type normal capacitors type best performance. accuracy both reference voltages must higher than retion ADC. typical applications both voltages filtered second order pass filter buffered with AD711. accuracy both input voltages must higher than resolution ADC. typical applications both voltages filtered. inncies input voltages buffered with AD8138 high frequencies transformer used.
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Datasheet ADC1220
Contact
austriamicrosystems 8141 Schloss Austria 3136 5333 3136 5755 support@austriamicrosystems.com
Copyright
Copyright 2002 austriamicrosystems. Trademarks registered rights reserved. material herein reproduced, adapted, merged, translated, stored, used without prior written consent copyright owner. best knowledge, austriamicrosystems asserts that information contained this publication accurate correct.
Revision 08.09.02
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C35B3 (0.35um) DESCRIPTION ADC1220 high-speed pipeline core

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