C35B3 (0.35um) DESCRIPTION AD1020 high-speed pipeline core c

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C35B3 (0.35um) DESCRIPTION AD1020 high-speed pipeline core c

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ANALOG BLOCK ADC1020 CMOS 10-Bit Pipelined CONVERTER
C35B3 (0.35um)
DESCRIPTION
AD1020 high-speed pipeline core cell achieving sampling rates MS/s. circuit built-in provide jitter noise optional singleended fully differential conversion. reference voltages internally generated from bandgap reference that must supplied cell must supplied externally cell. power down capability included very power dissipation stand-by mode.
FEATURES
Small Area: 1.57mm2 Size 2189.7µm 717.4µm Supply Voltage 2.7-3.6 Junction Temp. Range +85°C Resolution 10-Bit Maximum Sampling Rate MS/s Sample Hold Input Stage Input Signal Range Single Ended Fully Differential Input Power Consumption Power Down Mode
SWIB ONADC ONREF
VDDA1
VDDA2
VDDD1 IBIAS
Bias Current Generation
VREFP VREFN ONCM DOUT VINP VINN Pipeline Output Register
VCMU
Digital Error Correction
Timing Generation VSSA1 VSSAD VSSD1
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Datasheet ADC1020
TECHNICAL DATA
(Tjunction=-40 85°C, VDDA=VDD=+2.7V +3.6V, fclk=20MHz, VREFP VREFN specified, unless otherwise specified)
ACCURACY
Symbol GAINERR GAINERR Parameter Resolution missing Code) Differential Linearity Error Integral Linearity Error Offset Error Gain Error Internal Ref.
Conditions
-0.9
±0.4 ±0.6
Units
Mode Mode
Gain Error External Ref.
REFERENCE CHARACTERISTICS
Symbol VCMU VREFP VREFN VREF Ccmu Rrefp Crefp Rrefn Crefn Parameter ext. Bandgap Reference Voltage Unbuffered Mode Voltage Buffered Mode Voltage Pos. Reference Voltage Neg. Reference Voltage Difference between VREFP VREFN ext. Bandgap Ref. Impedance ext. Bandgap Ref. Input Current Unbuff. Comm. Mode Imped. Comm. Mode Impedance (Op. Modes Pos. Reference Impedance (Op. Modes Neg. Reference Impedance (Op. Modes Conditions 1.35 1.25 VDDA/2 VCMU VCM+0.4VBG VCM-0.4VBG 22.5
Units
ANALOG INPUT
Symbol Vind Finmax Max. Input Signal Frequency Parameter Diff. Input Voltage Range, related VCMU Input Impedance Conditions -VREF VREF Units
Offset Gain Error correspond measured reference voltages. This measured reference voltage VREF value 960mV instead 1000mV 1950mV instead 2000mV VREF=1V VREF=2V, respectively. This because additional trop bandgap voltage caused it's pad-resistor. Offset Gain Error correspond measured reference voltages outside chip. real voltage reference VREF macro cell value 972mV instead 1000mV 1945mV instead 2000mV VREF=1V VREF=2V, respectively. This because voltage trop caused pad-resistors. Only fully differential mode. VBG=1.25V VDDA=3.3V VBG=2.5V VDDA=3.3V
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Datasheet ADC1020
ACCURACY (VREF=1V)
Symbol SFDR SFDR SFDR SINAD SINAD SINAD ENOB ENOB ENOB TT-IMD TT-SFDR FPBW Parameter Total Harmonic Distortion Total Harmonic Distortion Total Harmonic Distortion Spurious Free Dynamic Range Spurious Free Dynamic Range Spurious Free Dynamic Range Signal Noise Ratio Signal Noise Ratio Signal Noise Ratio Signal (Noise+Dist.) Ratio Signal (Noise+Dist.) Ratio Signal (Noise+Dist.) Ratio Effective Number Bits Effective Number Bits Effective Number Bits Two-Tone third order Intermodulation Distortion Two-Tone Spurious Free Dynamic Range Full Power Bandwidth Conditions fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin1=4MHz fin2=4.5MHz fin1=4MHz fin2=4.5MHz
Units
ACCURACY (VREF=2V)
Symbol SFDR SFDR SFDR SINAD SINAD SINAD ENOB ENOB ENOB TT-IMD TT-SFDR FPBW Parameter Total Harmonic Distortion Total Harmonic Distortion Total Harmonic Distortion Spurious Free Dynamic Range Spurious Free Dynamic Range Spurious Free Dynamic Range Signal Noise Ratio Signal Noise Ratio Signal Noise Ratio Signal (Noise+Dist.) Ratio Signal (Noise+Dist.) Ratio Signal (Noise+Dist.) Ratio Effective Number Bits Effective Number Bits Effective Number Bits Two-Tone third order Intermodulation Distortion Two-Tone Spurious Free Dynamic Range Full Power Bandwidth Conditions fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin1=4MHz fin2=4.5MHz fin1=4MHz fin2=4.5MHz
Units
Measurements Fully Differential Mode Measurements Single Ended Mode Both signals, fin1 fin2, have amplitude -7dB full scale.
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Datasheet ADC1020
DIGITAL INPUTS OUTPUTS
Symbol B[9:0] Output Code Vind=-VREF Vind=VREF Digital Output Level Parameter Pos. digital Supply Voltage Neg. digital Supply Voltage Digital Input Level Conditions VDD=VDDA GND=GNDA 0.7VDD 0.3VDD Units
POWER REQUIREMENTS
Symbol VDDA VSSA
Parameter Pos. analog Supply Voltage Neg. analog Supply Voltage Supply Current Digital Supply Current Analog Supply Power Consumption
Conditions VDD=VDDA GND=GNDA Mode Mode Mode Mode Mode Mode Mode Mode Mode Mode
Units
IDDA
Psup Pdiss_tot
Total Power Dissipation Powerup Mode Supply Current Digital Supply Current Analog Supply Power Consumption Reference Current
IDDA Psup IREF Pdiss_tot Pdiss_pd
Total Power Dissipation Powerup Mode Power Consumption Power Down Mode
TIMING CHARACTERISTICS
Symbol fclk 1/Ts Jclk Parameter Frequency Sampling Rate CLOCK Jitter Clock falling edge sampling instant delay Clock falling edge data delay Clock duty cycle Data Latency Power Delay
Conditions
fclk
Units MS/sec psec nsec nsec
cycle cycle
Mode (internal references) with VREF=1V 20MHz clock frequency. Mode (external references) with VREF=1V 20MHz clock frequency. After 10us power down. digital output codes valid during first clock cycles after power
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Datasheet ADC1020
TYPICAL PERFORMANCE CHARACTERISTICS
(T=25deg, VDDA=VDD=+3.3V, fclk=20MHz, VREFP=2V, VREFN=1V, Mode Fully Differential Mode, unless otherwise specified)
[LSB]
Digital Code
[LSB]
Digital Code
@180kHz
@180kHz
[dBc]
Input Signal Frequency [Hz]
[dBc]
Input Signal Frequency [Hz]
Spectrum @180kHz
Spectrum @9.8MHz
Input Signal Frequency [Hz]
ENOB [Bit]
[dBc]
Input Signal Frequency [Hz]
Two-Tone @4.0MHz 4.5MHz
ENOB Input Signal Frequency
spectrum consists 16384 pins. Measured with 12MHz pass filter frequencies.
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Datasheet ADC1020
SYMBOL
PINLIST
VINP VINN VREFP VREFN VCMU B[9:0] ONADC ONREF ONCM DOUT SWIB Description Pos. Input Voltage Neg. Input Voltage Input Bandgap Reference Voltage Output bypass Internal Pos. Reference Voltage Output bypass Internal Neg. Reference Voltage Input Unbuffered Common Mode Voltage Analog Signals Output bypass internally buffered Clock Input Digital Output Bits MSB, LSB) Power Down Input (ONADC normal operation) Power Down Input Reference Generator (ONREF=1 normal operation) Power Down Input buffer (ONCM=1 normal operation) Input digital test mode; must tied VSSD1 Input flash output data test mode; must tied VDDD1 Bias current control pin; High, uses internal bias current; otherwise enables external current input. Output monitoring internal bias current generation when SWIB="1" input injection external bias current (10µA) when SWIB="0" VDDA1 VDDA2 VDDD1 VSSA1 VSSA2 VSSD1 VSSD2 Analog Power Supply Analog Power Supply Digital Power Supply Bottom Analog Power Supply Biasing voltage N-Well shielding from substrate Bottom Digital Power Supply Bottom Digital Power Supply Shielding Supply Supply Supply Supply Supply Supply Supply Digital Digital Digital Digital Type Analog Analog Analog Analog Analog Analog Analog Digital Digital Digital Digital
IBIAS
Analog
THEORY OPERATION
AD1020 10-bit capable sampling MS/s. uses fully differential pipelined architecture with 1.5-bit stage digital error correction achieve improved linearity performance. dedicated wide-band input sample-and-hold amplifier (S/H) built-in provide low-jitter, sub-sampling capability with inherent frequency down-conversion and, optionally,
single-ended fully differential signal conversion. digital words synchronized chain delay stages overlapped processed digital error correction logic produce 10-bit digital output code.
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Datasheet ADC1020
OPERATING MODES
modes operation summarized table bellow, described detail follows. Mode Description Complete Power Down Normal conversion with internally buffered VCM, VREF Ibias generation Normal conversion with internal VREF Ibias generation, externally buffered Normal conversion with internal Ibias generation, external VREF Normal conversion with internally buffered VCM, VREF external Ibias Normal conversion with internal VREF generation, external Ibias Normal conversion with external VCM, VREF Ibias ONADC ONREF ONCM SWIB
Mode Power Down
this mode circuitry power-down. power dissipation reduced minimum value.
Mode Normal Conversion
This normal conversion mode converter. bias current internally generated reference common mode voltages internally buffered. external bandgap reference voltage determines values reference voltages.
Mode through Mode Conversion Mode with different Bypassing options
These conversion modes allow different bypassing options bias current generator, reference generation buffer common mode voltages.
POWER SUPPLIES
converter requires single +3.3V power supply. supplies analog digital separated connected together. However, maximum noise immunity recommended wire them chip separated pins, especially when block embedded large digital circuit. supplies then connected together PC-board level. proper blocking capacitors application important!
REFERENCE VOLTAGES
ONREF high converter needs external bandgap reference which defines dynamic range input signal described technical data section. ONREF external voltage references VREFP VREFN define dynamic range input signal. additional series resistor cell causes wrong reference voltage generation modes with internal reference generation footnotes technical data section. external reference generation additional resistor cells VREFP VREFN causes voltage drop. This results smaller reference difference VREF. proper blocking capacitors application important!
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Datasheet ADC1020
SYSTEM REQUIREMENTS
sensitive ground noise. parts whole system except should quiet during conversions. minimize ground noise coming from digital output pads connection series resistor should used limit switching current. test circuit series resistor used digital output bus.
CONVERSION MODES
converter operates with fully-differential single-ended inputs. best performance this reached fully-differential inputs.
Single Ended Mode
ADC1020 Single Ended Converter input VINN must connected VCM. this case performs single-ended fully-differential conversion. second input VINP should balanced around VCM.
Fully Differential Mode
ADC1020 Fully Differential Converter both inputs VINP VINN should balanced around VCM.
CODE TABLES
digital representation data both conversion modes described following table.
VREFP VREFN
VREF VREFP VREFN
1LSB
Offset Binary
Output Code 1111 1111 Input Voltage: VIN-VINB 511LSB VREF
1111 1110 0000 0001 0000 0000 1111 1111 1111 1110 0000 0001 0000 0000
510LSB 511LSB 1LSB 2LSB 1LSB -1LSB -2LSB -1LSB -511LSB -510LSB -VREF -511LSB
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Datasheet ADC1020
FUNCTIONAL BLOCK DIAGRAM
MDAC MDAC MDAC MDAC
FLASH
FLASH
FLASH
FLASH
FLASH
Digital Error Correction Logic
TIMING DIAGRAM
sampling rate AD1020 defined frequency signal. input signal voltage sampled falling edge CLK. conversion stages operate staggered fashion alternate phases CLK, duty-cycle this signal must 50%. results latched output register falling edge CLK, with latency periods. conversion timing shown Diagram
Cycle
Stage Stage
Sample 0(1)
Hold 1(1)
mple 0(2)
Hold 1(2)
Sample 0(8)
Hold 1(8)
mple 0(9)
Hold 1(9)
mple Quant. 1(1)
Amplific ation 2(1) mple Quant. 2(1)
mple Quant. 1(2) Amplific ation
Amplification 2(7) mple Quant. 2(7)
mple Quant. 1(8) Amplific ation 3(7)
Amplific ation 2(8)
mple Quant. 1(9)
Stage
Sample Quant. Amplific ation 2(8)
Stage
Sample Quant.
mple Quant. 9(2)
Digital Output Latency CLKcycles
q[x(1)]
Diagram Timing pipelining operation
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Datasheet ADC1020
TYPICAL APPLICATION
ADC1020 targeted general purpose sampling functions where high-speed conversion rates medium precision critical importance.
APPLICATION
1)2)3)4)
+3.3V VDDA VDDD VDDA VDDD
Video Imaging Data acquisition systems High-speed data transmission Communications
+3.3V
10uF
100nF
100pF
VSSA
VSSD
B<9:0>
VDDD
1.65V
200pF
200pF
1.25V
20MHz
GROUND
Configuration: Mode 20MS/sec, fully differential with VREF=1V
+3.3V
+3.3V VDDA VDDD VDDA VDDD VDDA
10uF
100nF
100pF
VSSA
VSSD
10uA
B<9:0>
VDDD
2.65V
0.65V
1.65V
200pF
200pF
20MHz
GROUND
Configuration: Mode 20MS/sec, fully differential with VREF=2V
value capacitor depends input frequency. capacitors type normal capacitors type best performance. capacitors type normal capacitors type best performance. accuracy both reference voltages must higher than resolution ADC. typical applications both voltages filtered second order pass filter (fc=5Hz) buffered with AD711. accuracy both input voltages must higher than resolution ADC. typical applications both voltages filtered third order pass filter (fc=12MHz) buffered with THS3001.
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Datasheet ADC1020
Contact
austriamicrosystems 8141 Schloss Austria 3136 5333 3136 5755 support@austriamicrosystems.com
Copyright
Copyright 2002 austriamicrosystems. Trademarks registered rights reserved. material herein reproduced, adapted, merged, translated, stored, used without prior written consent copyright owner. best knowledge, austriamicrosystems asserts that information contained this publication accurate correct.
Revision 07.09.02
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C35B3 (0.35um) DESCRIPTION AD1020 high-speed pipeline core c

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