August 2001; ver. 1.01 Data Sheet Full-duplex processing capabili

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August 2001; ver. 1.01 Data Sheet Full-duplex processing capabili

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Packet Processor Mbps MegaCore Function (PP622)
August 2001; ver. 1.01 Data Sheet
Full-duplex processing capability Octet-synchronous mode operation High-level data link control (HDLC)-type framing 622.08 megabits second (Mbps) transmission rate 32-bit frame check sequence (FCS) Single-channel processor interleaving) Optimized Altera® APEX20KE device architecture Quartus® software OpenCore® feature allow place-and-route, static timing analysis designs prior licensing Secure register transfer level (RTL) simulation models allow simulation with user design third-party simulators Compliant with industry standards, including: Internet Request Comments (RFC) 1662 (some sections implemented) Internet Request Comment (RFC) 2615 Altera Corporation, AtlanticInterface Functional Specification.
Typical Applications
Figure shows example system implementation PP622 interfacing with other Altera MegaCore® variants achieve over SONET. Midbus Atlantic interfaces allow PP622 connect several other devices including:
carrier processor Ethernet media access controller (MAC) Direct memory access (DMA) controller Packet switch router Ethernet over SONET multiplexer
Figure Typical Application
Midbus rxclk Fiber Optic Module Clock Data Recovery txclk External Processor Interface AIRbus SONET/SDH STS-12c/ STM-4 Framer (STS12CFRM) Packet Processor Mbps (PP622) POS-PHY Interface (POSPHY/P2) Atlantic
PoS-PHY Level 1/2/3/
Serializer Deserializer
APEX Boundary
Altera Corporation
A-DS-IPPP622-1.01
Packet Processor Mbps MegaCore Function (PP622) Data Sheet
Functional Description
PP622 capable performing HDLC-type framing. operates full-duplex mode, comprises blocks, illustrated Figure
following list functions based full-feature PP622. High-level data link control receiver (RXHDLC) Inputs packets from Midbus interface Aligns receive bytes (software programmable) Descrambles receive frame between-frame flags using self-synchronizing scrambler (software programmable) Detects start frame (SOF) Decodes removes byte stuffing Checks receive FCS, removes from frame (software programmable) Outputs packets Atlantic interface High-level data link control transmitter (TXHDLC) Takes packets from Atlantic interface Byte stuffs control bytes data transparency Calculates packet data (before stuffing), appends packet Sends more HDLC flag(s) after until packet available Scrambles transmit frame between-frame flags using self-synchronizing scrambler (software programmable) Outputs frames Midbus interface
Interfaces Protocols
Three interfaces support PP622: middle interface (Midbus), access internal registers (AIRbus) interface, Atlantic interface.
Midbus Interface
Midbus interface simple synchronous full-duplex data path bus. PP622 Midbus runs 77.76 over single byte lane each direction. receive direction (RX), data transferred from Midbus master slave (PP622). transmit direction (TX), data transferred from slave (PP622) master. each direction, Midbus carry eight bits clock cycle. includes Midbus receive data (mrxdat[7:0]) Midbus receive enable (mrxena) lines indicate valid data transfers direction, Midbus transmit data (mtxdat[7:0]) Midbus transmit enable (mtxena) lines indicate valid data requests direction. Since PP622 slave Midbus work with Midbus master.
Altera Corporation
Packet Processor Mbps MegaCore Function (PP622) Data Sheet
AIRbus Interface
AIRbus interface provides access internal registers using simple synchronous internal protocol. This consists separate read data (rdata[15:0]) write data (wdata[15:0]) buses, data transfer acknowledge (dtack) signal, select (sel) signal. address (addr[4:1]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking) meaning AIRbus cross clock domain boundaries. PP622 AIRbus slave with data width bits.
Atlantic Interface
Atlantic interface full-duplex synchronous protocol supporting both packets cells. PP622 Atlantic interface master using 8-bit wide data path deliver packets slave. example slave POS-PHY MegaCore variant shown Figure POS-PHY MegaCore variant includes first-in first-out (FIFO) buffer crossing clock domain.
More detailed information Midbus, AIRbus, Atlantic interfaces available from Altera site http://www.altera.com.
Altera Corporation
Packet Processor Mbps MegaCore Function (PP622) Data Sheet
Figure Block Diagram
PP622
rxclk
rxreset_n
RXHDLC
arxena arxdav arxdiv arxdat[7:0] arxsop arxeop arxerr atxena TXHDLC atxdiv atxdav atxval atxdat[7:0] atxeop atxsop atxerr
Midbus Interface
mrxdat[7:0] mrxena
txclk txreset_n
Atlantic Interface
Midbus Interface
mtxdat[7:0] mtxena
read
dtack
wdata[15:0]
addr[4:1]
AIRbus Interface
Signals
following lists ports PP622. signal direction indicated input output. Clock Domain Signal: rxclk (I); Midbus Signals: mrxdat[7:0] (I), mrxena (I); Atlantic Signals: arxena (O), arxdav (I), arxdiv (O), arxdat[7:0] (O), arxsop (O), arxeop (O), arxerr (O). AIRbus Signals: (I), read (I), addr[4:1] (I), wdata[15:0] (I), rdata[15:0] (O), dtack (O), (O). Clock Domain Signals: txclk (I), txreset_n (I); Midbus Signals: mtxdat[7:0] (O), mtxena (I); Atlantic Signals: atxena (O), atxdiv (I), atxdav (I), atxval (I), atxdat[7:0] (I), atxsop (I), atxeop (I), atxerr (I).
rdata[15:0]
Altera Corporation
Packet Processor Mbps MegaCore Function (PP622) Data Sheet
Performance
Table shows required speed estimated gate count PP622 APEX 20KE device.
Table Performance
1,197 Note:
Note
ESBs
fMAX (MHz)
77.76 required support 622.08 Mbps
numbers logic elements (LEs) embedded system blocks (ESBs) approximate August 2000.
Licensing
license required perform following trial operations using your custom logic:
Instantiation Place-and-route Static timing analysis Simulation third-party simulator
Only when ready generate programming files, need obtain licenses through your local Altera sales representative.
current variants single license with ordering code: PLSM-PP622.
Deliverables
following elements provided with PP622 package:
Data sheet User guide AIRbus, Midbus, Atlantic interface functional specifications MegaWizard Plug-In Encrypted gate level netlist Place-and-route constraints (where necessary) Secure simulation model Demo testbench Access problem reporting system
Altera Corporation
Packet Processor Mbps MegaCore Function (PP622) Data Sheet
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Copyright 2001 Altera Corporation. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation

August 2001; ver. 1.01 Data Sheet Full-duplex processing capabili

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