November 2001; ver. 1.02 Data Sheet Encoders decoders used physic

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November 2001; ver. 1.02 Data Sheet Encoders decoders used physic

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8b10b Encoder/Decoder MegaCore Function (ED8B10B)
November 2001; ver. 1.02 Data Sheet
Encoders decoders used physical layer coding Gigabit Ethernet, Fibre Channel, other applications. 8b/10b encoder takes byte inputs, generates direct current (DC) balanced stream (equal number with maximum length Some individual 10-bit codes will have equal number while others will have either four four latter case, disparity between used input next 10-bit code generation, that disparity reversed, maintain overall balanced stream. this reason, some 8-bit inputs have valid 10-bit codes, depending input disparity. Altera® 8b10b Encoder/Decoder MegaCore® Function (ED8B10B) compact, high performance core capable encoding decoding Gigabit Ethernet rates (125 MHz: Gbps). ED8B10B optimized APEX20K, FLEX 10K®, Mercurydevices.
Features
Look-up table (LUT)-based implementation encoder Industry compatible special character coding Complies with applicable standards, including: Institute Electrical Electronics Engineers, IEEE 802.3z, Media Access Control (MAC) Parameters, Physical Layer, Repeater Management Parameters 1000 Mb/s Operation, 1998, paragraphs 36.2.4.1 36.2.4.6. Quartus® software, OpenCore® feature allow place-and-route static timing analysis designs prior licensing Secure register transfer level (RTL) simulation models allow simulation with user design third-party simulators
Functional Description
ED8B10B encode 8-bit byte data into 10-bit transmission code, decode 10-bit code into 8-bit byte data. Figure illustrates bidirectional conversion process. eight input bits named least significant (LSB), most significant (MSB). They split into groups: five-bit group three-bit group coded bits named (the order alphabetical). These bits also split into groups: six-bit group four-bit group
Altera Corporation
A-DS-IPED8B10B-1.02
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Figure 8b10b Conversion
8b10b
Conversion
sent last
sent first
serial transmission, usually transmitted first, while usually transmitted last.
Character Codes
addition data characters, 8b/10b code defines twelve out-ofband indicators, also called special control characters. data characters named Dx.y, special control characters named Kx.y. value corresponds five-bit group, value three-bit group. special control characters indicate, example, whether data idle, test data, data delimiters. applications where encoded characters transmitted bit-serially, comma character (K28.5) usually used alignment purposes 10-bit code guaranteed occur elsewhere encoded stream, except after K28.7 which normally only sent during diagnostic.
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Table lists special codes used ED8B10B.
Table Character Codes
10-Bit Special Codes
K28.0 K28.1 K28.2 K28.3 K28.4 K28.5 K28.6 K28.7 K23.7 K27.7 K29.7 K30.7 Note:
K28.5 comma character used alignment purposes, represent IDLE code.
Equivalent 8-Bit Codes
8'b000_11100 8'b001_11100 8'b010_11100 8'b011_11100 8'b100_11100 8'b101_11100 8'b110_11100 8'b111_11100 8'b111_10111 8'b111_11011 8'b111_11101 8'b111_11110
Disparity
Disparity difference between number encoded word.
Neutral disparity indicates number equal. Positive disparity indicates more than Negative disparity indicates more than
ED8B10B designed maintain neutral average disparity. Average disparity determines component serial line. Running disparity record cumulative disparity every encoded word, tracked encoder. guarantee neutral average disparity, positive running disparity must followed neutral negative disparity; negative running disparity must followed neutral positive disparity. these conditions met, decoder flags error asserting rderr output.
details running disparity rules, IEEE 802.3z specification, paragraph 36.2.4.4.
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Encoder
encoder uses innovative, proprietary, non-partitioned, memorybased implementation convert data identified special 8-bit codes from bits bits. Figure page illustration conversion process. encode 8-bit word, 8-bit value must applied datain inputs enable input must asserted (active high). When twelve special 10-bit codes inserted, equivalent 8-bit code placed datain lines input asserted. core performs error checking ensure out-of-band 8-bit code valid. not, kerr output asserted. Table page list valid codes. Idle (K28.5) characters automatically inserted when enable asserted asserting idle_ins input. Figure shows block diagram encoder.
Figure ED8B10B Encoder
kerr reset_n enable idle_ins datain [7:0] rdin rdforce rdout rdcascade dataout [9:0] valid
Disparity
running disparity forced positive negative, allowing user insert special resynchronization pattern, disparity errors. When rdforce input asserted, value rdin port assumed current running disparity. Setting rdin forces encoder produce encoded word with positive neutral disparity. Setting rdin forces encoder produce encoded word with negative neutral disparity.
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Cascaded Encoding
encoders cascaded allow 16-bit word encoding. encoders cascaded connecting rdcascade output most significant byte (MSByte) encoder rdin input least significant byte (LSByte) encoder, connecting rdout output LSByte encoder rdin input MSByte encoder. These connections ensure proper running disparity computation. rdforce inputs must asserted (active high) encoders take into account value rdin inputs, rather than their internally generated running disparity. Both enable inputs must high same time. signal relates datain[15:8], kin[0] relates datain[7:0]. Figure shows encoders connected together perform cascaded encoding.
Figure Cascaded Encoding
Note
reset_n [1:0] enable idle_ins
datain [15:0] datain [15:8]
kerr dataout [9:0] valid rdout rdcascade
rdin rdforce
reset_n enable idle_ins datain [7:0] rdin rdforce
kerr dataout [9:0] valid rdout
rdcascade
Note:
enable, idle_ins, rdforce signals high (logic
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Encoding Latency
encoder pipelined, thus takes three clock cycles character encoded. encoded value-corresponding values datain sampled encoder rising edge n-is output shortly after rising edge n+2, available sampled rising edge clock cycle n+3. (See Figure page enable cascaded encoding, data paths rdforce rdin inputs pipelined. Since rdforce rdin normally only used cascaded configurations, this should problem. cases where rdforce rdin inputs used noncascaded configurations, they should delayed clock cycles with respect their corresponding datain values. This achieved inserting registers series with each inputs delayed, following example Verilog code shows implement required delay registers. Example: Adding delay rdforce rdin non-cascaded applications: _pre2 registers same time datain kin. rdforce_pre2; rdin_pre2; _pre1 registers provide extra clock tick delay rdforce_pre1; rdin_pre1; always (posedge clk) begin rdforce rdforce_pre1; rdforce_pre1 rdforce_pre2; rdin rdin_pre1; rdin_pre1 rdin_pre2;
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Figure Encoder Timing Diagram
datain, kin, enable
dataout
rdforce, rdin
Decoder
Data identified 10-bit special codes converted from bits bits; Table page list valid codes, Figure page illustration conversion process. When special 10-bit codes received, special codes translated 8-bit values, kout signal asserted. decoder also checks invalid 10-bit codes, asserts kerr signal when invalid codes detected. When idle_del signal asserted, deletes 10-bit words identified special IDLE character K28.5. When receiver detects disparity error, rderr signal asserted. Figure shows block diagram decoder.
Figure ED8B10B Decoder
reset_n idle_del enable datain [9:0] rdin rdforce valid dataout [7:0] kout kerr rderr rdout rdcascade
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
CASCADED DECODING
decoders cascaded decode words simultaneously. decoders cascaded-in similar fashion encoders-by connecting rdcascade output first decoder rdin input second decoder, connecting rdout output second decoder rdin input first decoder. rdforce inputs both decoders must tied high. enable cascaded decoding, data paths rdin rdforce inputs cascaded. these inputs used noncascaded decoders, they should delayed clock cycle with respect their corresponding datain inputs.
Decoding Latency
decoder pipelined, thus takes clock cycles character decoded. decoded value-corresponding value datain sampled decoder rising edge n-is output shortly after rising edge n+1, available sampled rising edge clock cycle n+2. (See Figure page
Figure Decoder Timing Diagram
datain, enable
dataout, kout, kerr, rdout, rderr
rdforce, rdin
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Signals
Tables list input/output signals encoder, decoder.
Table Encoder Signals
Signal Name
reset_n enable idle_ins datain[7:0] rdin
Direction
Input Input Input Input Input Input Input
Description
Clock. input latched, result output this clock. There three clock cycle latency between input output. Active low, reset. Asynchronously resets registers core. Command byte indicator. When high, indicates that input command byte, data byte. Enable encoder signal. When high, indicates that data currently present datain input encoded. Idle character insert. When high, idle (K28.5) characters inserted when enable asserted. Data input. This 8-bit input word, data command. Running disparity input. When rdforce high, value this used current running disparity instead internally generated one. Force running disparity. When high, rdin value overrides internally generated running disparity. Special character error. This signal high when enable high value datain valid special character. Data output. This 10-bit encoded output. Valid signal. When high, indicates that valid encoded word present dataout output. Running disparity output. current running disparity (after encoding word present dataout output). Cascaded Running disparity. Used when encoders cascaded.
rdforce kerr dataout[9:0] valid rdout rdcascade
Input Output Output Output Output Output
Table Decoder Signals
Signal Name
reset_n idle_del enable datain[9:0]
Direction
Input Input Input Input Input
Description
Clock. input latched, result output this clock. There three clock cycle latency between input output. Active low, reset. Asynchronously resets registers core. Idle delete signal. When high, idle words (K28.5) removed from stream (i.e. valid when idle words received). Enable decoder signal. When high, indicates that data currently present datain input decoded. Data input. This 10-bit encoded input word.
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Table Decoder Signals
Signal Name
rdin
Direction
Input
Description
Running disparity input. When rdforce high, value this used current running disparity instead internally generated one. Force running disparity. When high, rdin value overrides internally generated running disparity. Valid signal. When high, indicates that valid decoded word present dataout output. Data output. This 8-bit decoded data command. Command output. When high, indicates that output command byte, data byte. Special error. Asserted high when invalid 10-bit word received. Running disparity error. When high indicates running disparity rules have been violated. Running disparity output. current running disparity (after decoding word present dataout output). Cascaded Running disparity. Used when decoders cascaded.
rdforce valid dataout[7:0] kout kerr rderr rdout rdcascade
Input Output Output Output Output Output Output Output
Resources
Table Resources
Device
APEX Family EP20K30ETC144-1 Mercury Family EP1M120F484C7AES Flex Family EPF10K30ETC144-1 Note:
Table shows required speed estimated gate count ED8B10B possible target devices.
Note
Mode
Encoder Decoder Encoder Decoder Encoder Decoder
LEs/LCs
ESBs/EABs
fMAX (MHz)
173(2) 216(2) 138(2)
numbers logic elements/logic cells (LEs/LCs) embedded system blocks/embedded array blocks (ESBs/EABs) approximate November 2001. fMAX non-cascaded encoder/decoder.
Altera Corporation
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Licensing
license required perform following trial operations using your custom logic:
Instantiation Place-and-route Static timing analysis Simulation third-party simulator
When ready generate programming files, need obtain licenses through your local Altera sales representative.
current 8b10b Encoder/Decoder MegaCore functions single license with ordering code: IP-ED8B10B.
Deliverables
following elements provided with package:
Data sheet Encrypted gate level netlist file Place-and-route constraints (where necessary) Secure simulation model Demo testbench Access problem reporting system
Refer Readme file included with package installation customization instructions.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Copyright 2001 Altera Corporation. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation

November 2001; ver. 1.02 Data Sheet Encoders decoders used physic

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