Universal Asynchronous Receiver/Transmitter November 2002, ver. D
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a6402
Universal Asynchronous Receiver/Transmitter
November 2002, ver. Data Sheet
Optimized StratixGX, CycloneTM, Stratix, APEX®, APEX FLEX® device families Uses approximately logic elements (LEs) Programmable word length, stop bits, parity Full duplex operation Includes status flags parity, framing, overrun errors Functionally based Harris HD-6402 device, except noted "Variations Clarifications" page
General Description
a6402 function implements universal asynchronous receiver/transmitter (UART), which provides interface between microprocessor serial communications channel. Figure shows a6402 symbol. Figure a6402 Symbol
A6402
en_rx en_tx cls1 cls2 ndrr ntbrl tbr[7.0]
rbr[7.0] tbre
Altera Corporation
DS-A6402-1.1
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Signals
Table shows input output signals a6402.
Table a6402 Signals (Part Name
en_rx en_tx
Type
Input
Polarity
High
Description
Clock enables. en_rx en_tx signals allow UART remain fully synchronous with system high-speed clock, while operating receive transmit enable frequencies. en_rx en_tx signals pulses that high system clock period rate times rate desired receive transmit data rates. Character length select bits. These bits determine length data word. 5-bit word format 6-bit word format 7-bit word format 8-bit word format Control register load. Controls data word loaded into control register. Data received reset. Clears output. Master reset. Clears outputs, asserts tbre outputs. Parity inhibit. When asserted, parity neither generated checked. Receiver register clock. Operates times receive data rate. Receiver register input. Serial input data.
cls1 cls2
Input
ndrr
Input Input Input Input Input Input Input Input
High High High
High/low Even parity enable. When high, even parity; when low, parity.
High/low Stop select. When high, generates stop bits (1.5 stop bits 5-bit format); when low, generates stop bit. High High High Transmitter buffer register load. Enables load transmitter buffer register. Transmitter buffer register input bus. Transmitter register clock. Operates times transmit data rate. Data received. Indicates that data word been transferred receiver buffer register. Framing error. Asserted when expected stop bit(s) detected. Overrun error. Asserted when data receiver buffer register overwritten while output still asserted.
ntbr1 tbr[7:0] rbr[7:0] tbre
Input Input Output Output Output Output Output Output Output
High/low Parity error. when calculated parity does match received parity. When asserted, low. High Receiver buffer register bus. Transmitter buffer register empty. Indicates that transmitter buffer register empty.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Table a6402 Signals (Part Name
Type
Output Output
Polarity
High
Description
Transmitter register empty. Indicates that data word completely transmitted transmitter register. Transmitter register output. Serial output data.
Configurations
a6402 receives transmits data variety configurations, including 8-bit data words; odd, even, parity; 1.5, stop bits. Table shows available configuration options. Table a6402 Available Configurations (Part Character Format Data bits
Control Word Stop Bits
Parity
Even Even None None
Start
cls2
cls1
Even Even None None
Even Even None None
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Table a6402 Available Configurations (Part Character Format Data bits
Control Word Stop Bits
Parity
Even Even None None
Start
Note:
cls2
cls1
indicates "don't care."
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Functional Description
Figure shows block diagram a6402.
Figure a6402 Block Diagram
cls2 cls1 tbre Transmitter Control
Control Register
Transmitter
ntbrl
Start Transmitter Buffer Register Transmitter Register Parity Generator Transmitter Multiplexer
Stop
ndrr Receiver Control
Receiver
Receiver Buffer Register
Receiver Register
Parity Check Stop Check
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Master Reset
When input asserted, outputs asynchronously cleared tbre asserted. assertion also sets state machines default idle state. This condition does affect receiver buffer register. input must pulsed high least once after power-up. When deasserted, normal operation resumes next rising edge rrc.
Once outputs set, only exit condition available through asserting
Control Register
control register contains configuration data word, including number bits, calculated parity, number stop bits. input, active high register enable, controls data word loaded into control register. When asserted, cls2, cls1, epe, inputs loaded next rising edge input.
Transmitter
transmitter consists following elements: Transmitter control-The transmitter control contains three interconnected state machines. first state machine regulates baud rate performing divide-by-16 operation input. second state machine detects low-to-high transition ntbrl, starts serial transmission through tro, transfers data from transmitter buffer register transmitter register, generates status signals tbre tre. third state machine controls multiplexing data bits output. Transmitter buffer register-The transmitter buffer register loaded ntbrl, active-low register enable, that causes tbr[7.0] loaded from microprocessor next clock edge. Transmitter register-The transmitter register loads data from transmitter buffer register holds that data until transmission complete. Parity generator-The parity generator calculates appropriate parity value depending input (even parity) inputs (data word length). Transmitter multiplexer-The transmitter multiplexer selects single-bit data value drives output. Inputs transmitter multiplexer include start bit, eight bits from transmitter register, parity bit, stop idle bit.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Receiver
receiver consists following elements: Receiver control-The receiver control contains three interconnected state machines. first state machine performs divide-by-16 operation clock determine when sample serial input. second state machine detects high-to-low transition rri, determines valid start been received, transfers data from receiver register receiver buffer register, generates status signals third state machine loads individual bits receiver register outputs. Receiver register-The receiver register loads number data bits determined inputs. data word less than eight bits, data right-justified with MSBs filled with logic lows. When stop detected, receiver register transfers contents receiver buffer register. Parity check-The parity check calculates parity data word parity bit. error occurs, output asserted. Once asserted, output only cleared asserting input. Stop check-The stop check samples middle first expected stop bit. error occurs, output asserted. Once asserted, output only cleared asserting input.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Timing Waveforms
Figure shows timing waveforms a6402. Figure a6402 Functional Timing Waveforms
Data Input Cycle tbr[7.0] ntbr Control Register Input Cycle cls[2.1], Serial Data Format Bits, Parity Bit, Stop Bit)
Start Data Data Parity Stop
Valid Data
Valid Data
Variations Clarifications
following characteristics distinguish Altera® a6402 from Harris HD-6402: a6402 does contain inputs, outputs tri-stated. a6402, control transmitter buffer registers implemented registers clock source; these registers implemented latches HD-6402 device. a6402, after deasserted, normal operation resume next rising clock edge. HD-6402 device, normal operation does resume clock cycles. synchronization process a6402, tbre deasserted clock cycles after low-to-high transition ntbrl. HD6402 device, tbre deasserted immediately after low-to-high transition ntbrl. a6402, output registered remove glitches. This register uses clock source. Once outputs asserted, HD-6402 device exit condition other than through asserting
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Directory Structure
Figure shows directory structure a6402. Figure Directory Structure
a6402-<version> clear_wrappers Contains both Verilog VHDL wrapper file that show core pinouts. Contains documentation. Contains encrypted core. sim_lib Contains simulation libraries. native Contains VHDL model. testbench Contains testbench files. visualip Contains precompiled libraries Visual software.
Simulate with Models
Altera provides VHDL model that simulate function your system. Altera also provides Visual models, which with Visual software supported other simulators. VHDL model supplied pre-compiled libraries ModelSim simulation tool installed sim_lib\native\vhdl\modelsim directory. integrate this model into your system, speeding simulation process. following instructions describe your system simulate VHDL model using ModelSim simulation tool. Within sim_lib\native\vhdl\modelsim directory precompiled library, auk_a6402, which required. also ModelSim graphical user interface (GUI) create logical map. Refer ModelSim online help details.
ModelSim simulation tool create logical called auk_a6402 directory containing compiled library typing following command ModelSim software: vmap auk_a6402 <Drive:>/<Core Path>
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
must refresh compiled library typing command: vcom -work auk_a6402 -refreshr
Using VHDL Testbenches
addition model, Altera provides sample VHDL testbench sim_lib\testbench\ directory). VHDL testbench lets easily simulate function. compile these files ModelSim software, follow steps below: sample VHDL testbench, VHDL model must available setup ModelSim described earlier.
Open ModelSim simulation tool. Choose Change Directory (File menu) change directory your working directory. Select Create Library (Design Menu). Select library logical mapping Library type work. Select Compile (Design menu), Compile Source Files dialog box, select \sim_lib\testbench directory Look drop-down list box. Select a6402_tb.vhd click Compile; select tippytop.vhd click Compile. file tippytop.vhd top-level file, which required simulation (see Figure
Figure Tippytop.vhd Block Diagram
Tippytop a6402 Testbench a6402 Clear Wrapper
When compilation finishes, click Done. ready simulation.
Visual Models
Follow instructions below obtain Visual software Internet. have Internet access, obtain Visual software from your local Altera representative.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Point your browser Follow online instructions download software save your hard disk.
Visual model, perform following steps: your system Visual software, detailed Visual documentation (Simulating Visual Models with ModelSim Simulator White Paper, Simulating Visual Models with NC-Verilog, Verilog-XL, VCS, ModelSim (UNIX) Simulators White Paper). Compile wrapper core model into auk_a6402 library. Verilog version wrapper visualip\<operating system>\a6402\interface\pli directory; corresponding VHDL version visualip\<operating system>\a6402\interface\mti directory. Compile either your testbench open-source VHDL testbench model, a6402_tb, which sim_lib\testbench directory. Compile appropriate wrapper file from \clear_wrappers directory.
Visual model ready your simulator.
Synthesis, Compilation Place Route
After have verified that your design functionally correct, ready perform synthesis place-and-route. Synthesis performed Quartus® development tool. Before compile place-and-route, must create Quartus project your chosen file project. With Project wizard, specify working directory project, assign project name, designate name top-level design entity. will also specify a6402 user library. create project, perform following steps: Choose Altera Quartus <version> (Windows Start menu) Quartus software. also Quartus Edition software prefer. Choose Project Wizard (File menu).
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Click Next introduction (the introduction will display turned previously). Specify working directory your project. Specify name project. Click Next. Click User Library Pathnames. Type <path>\a6402-<version>\lib\ into Library name box, where <path> directory which installed a6402 UART. default installation directory c:\MegaCore. Click Add.
Click Click Next. Click Finish. finished creating your Quartus project. your chosen file project, perform following steps: This walkthrough adds example instantiation from \clear_wrappers directory.
Choose Add/Remove File (Project menu). Browse examples instantiations \clear_wrappers directory. Choose either VHDL Verilog file.
Quartus software compile place-and-route your design, perform following steps: Select Compile mode (Processing menu). Specify Compiler settings Compiler Settings dialog (Processing menu) Compiler Settings wizard. Compile your design. Quartus compiler synthesizes performs place-and-route your design.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Refer Quartus Help further instructions performing compilation.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com
Copyright 2002 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, mask work rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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