a16450 MegaCore® function implementing universal asynchronous receiver

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

a16450 MegaCore® function implementing universal asynchronous receiver

Datasheet Thumbnail

Top Searches for this datasheet

a16450 Universal Asynchronous Receiver/Transmitter
a16450 MegaCore® function implementing universal asynchronous receiver/transmitter (UART) Supports Altera® StratixTM, APEXTM, FLEX® device architectures Programmable word length, stop bits, parity Full duplex operation Programmable baud rate generator Prioritized interrupt control Internal diagnostic/loopback capabilities Functionally based National Semiconductor Corporation NS16450 device, except noted "Variations Clarifications" page
General Description
a16450 MegaCore function implements universal asynchronous receiver/transmitter (UART), which provides interface between microprocessor serial communications channel. a16450 receives transmits data variety configurations, including 8-bit data words; odd, even, parity; 1.5, stop bits. a16450 includes internal baud rate generator interrupt control. Figure Figure a16450 Symbol
A16450
nADS nCS2 nBAUDOUT nCTS CSOUT nDCD DDIS nDSR nDTR INTR RCLK nOUT1 nOUT2 nRTS SOUT DOUT[7.0] A[2.0] DIN[7.0]
Altera Corporation
DS-A16450-1.1
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table describes input output ports a16450.
Table a16450 Ports (Part
Name
nads
Type
Input
Polarity
Description
Address strobe. Enable signal address input receiver. positive edge nads latches register address into address input register. Clock. Provides master timing reference a16450. Chip select a16450 selected when cs0, cs1, ncs2 asserted, which permits read write transactions internal registers. Chip select a16450 selected when cs0, cs1, ncs2 asserted, which permits read write transactions internal registers. Chip select a16450 selected when cs0, cs1, ncs2 asserted, which permits read write transactions internal registers. Clear send. Indicates that modem ready exchange data. change input state from high recorded modem status register. modem status interrupt enabled when ncts changes state, interrupt generated. This input's complement recorded modem status register. Data carrier detect. Indicates that modem data detected data carrier. change input state recorded modem status register. modem status interrupt enabled when ndcd changes state, interrupt generated. This input's complement recorded modem status register. Data ready. Indicates that modem data ready establish communications link with a16450. change input state recorded modem status register. modem status interrupt enabled when ndsr changes state, interrupt generated. This input's complement recorded modem status register. Master reset. Clears registers (except receiver buffer, transmitter holding, divisor registers) their initial state. Resets control logic initial state. Receiver clock. Operates times baud rate clock. Read control. When asserted a16450 selected, read transactions from internal registers possible. Read control. When asserted a16450 selected, read transactions from internal registers possible. Ring indicator. Indicates that modem data detected ring signal. change input state recorded modem status register. modem status interrupt enabled when changes state, interrupt generated. This input's complement recorded modem status register.
ncs2 ncts
Input Input Input Input Input
High High
ndcd
Input
ndsr
Input
Input
High
rclk
Input Input Input Input
High
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table a16450 Ports (Part
Name
a[2.0] din[7.0] nbaudout csout ddis
Type
Input Input Input Input Input Output Output Output
Polarity
High High High
Description
Serial data input. Receives data a16450. Write control. When asserted a16450 selected, write transactions internal registers possible. Write control. When asserted a16450 selected, write transactions internal registers possible. Register address bus. Selects internal registers. Table Data input bus. microprocessor writes internal registers din[7.0] bus. Baud out. Transmitter clock that controlled programmable baud rate generator. Operates times baud rate clock. Chip select output. Indicates that a16450 been selected (i.e., cs0, ncs2 inputs asserted). Driver disable. Indicates that microprocessor reading data from a16450. This output intended disable direction control between a16450 microprocessor. Data terminal ready. Indicates that a16450 ready exchange data. This output controlled writing modem control register. Interrupt. Indicates that enabled interrupt condition been met. User-programmable output This output controlled writing modem control register. User-programmable output This output controlled writing modem control register. Request send. Indicates that a16450 ready exchange data. This output controlled writing modem control register. Serial data out. Serial (transmitter) data out. When asserted, sout output asserted. Data output bus.
ndtr intr nout1 nout2 nrts sout dout[7.0]
Output Output Output Output Output Output Output
High High
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Functional Description
Figure shows a16450 block diagram.
Figure a16450 Block Diagram
rclk din[7.0] a[2.0] ncs2 nads ddis csout Receiver Buffer Register Decode Control Logic Line Control Register Output Data Multiplexer dout[7.0] Receiver Register Control
Divisor Register (MSB) Divisor Register (LSB) Baud Generator nbaudout
Line Status Register
Transmitter Register Control
sout
Transmitter Holding Register nrts ndtr nout1 nout2 ncts ndsr ndcd
Modem Control Register
Modem Control Logic
Modem Status Register
Interrupt Enable Register
Interrupt Register
Interrupt Control Logic
intr
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Register Address
state a[2.0] inputs determines which internal register microprocessor addresses. Table divisor register access (drab) allows access divisor register. drab line control register.
Table Register Address
drab
Note:
indicates "don't care."
Register
Receiver buffer register-read only Transmitter holding register-write only Divisor register (LSB) Interrupt enable register Divisor register (MSB) Interrupt register Line control register Modem control register Line status register Modem status register Scratchpad register
Registers
a16450 MegaCore function contains following registers:
Receiver buffer Transmitter holding Divisor Interrupt enable Interrupt identification Line control Modem control Line status Modem status Scratchpad
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Receiver Buffer Register
receiver buffer register read-only register that contains last complete data word sample received a16450.
Transmitter Holding Register
transmitter holding register write-only register that loads next data byte transmitted a16450.
Divisor Register
divisor register controls programmable baud rate generator. 16-bit divisor performs integer frequency divide input clock. nbaudout output becomes transmitter clock that operates times baud rate clock. example, input clock divisor register binary (0000000000000010), nbaudout will 5-MHz output with 50/50 duty cycle. effective baud rate will 1/16th MHz, 312,500 baud. addition, nbaudout output wrapped receiver section input clock (rclk) provide receiver clock that operates times baud rate clock. a16450 does support divide-by-0 operation, which produces same results divide-by-1 operation nbaudout output. However, divide-by-0 operation prevents transmitter from functioning because internal signal, baud_en, generated. baud_en signal enables clock transmitter.
Interrupt Enable Register
a16450 supports interrupts from four different sources; interrupt enable register selectively enables disables interrupts from each these sources. When reset logic low, a16450 will recognize interrupts from that source. Table shows interrupt enable register format.
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table Interrupt Enable Register Format
Signal
Description
Received data available. When logic high, enables interrupts when receive data loaded receiver buffer register.
thre Transmitter holding register empty. When logic high, enables interrupts when transmitter holding register empty. Receiver line status. When logic high, enables interrupts when receiver line status register changes state. Modem status. When logic high, enables interrupts when modem status register changes state. Read-only bits that always logic low.
Interrupt Identification Register
a16450 priority encoding scheme four interrupt sources. Table shows encoding scheme each interrupts, their priority, reset mechanism each interrupt source. When logic low, indicates that interrupt pending. Bits indicate interrupt priority, bits through read-only bits that always logic low. Clearing interrupt source does affect lower priority interrupts that might pending. When interrupt identification register accessed, highest priority interrupt beginning access recorded register. Other interrupts, including those higher priority, recorded recognized until current register access complete.
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table Interrupt Identification Register Format
Note
Interrupt Source
Bits
Interrupt Type
interrupt Receiver line status Receiver data available Transmitter holding register empty Modem status
Reset Mechanism
Priority
Overrun, parity, Read receiver line Highest framing errors; break status register interrupt Receiver data available Transmitter holding register empty Read receiver buffer Read interrupt register write transmitter holding register
cts, dsr, Read modem change state status register
Note:
indicates "don't care."
Line Control Register
line control register sets data communication formats used a16450. Table
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table Line Control Register Format
Description
Word length control. Sets length word associated with each transmitted received word. Table Stop control bit. Controls number stop bits generated transmitter section. receiver circuitry checks first stop only, regardless state Table Parity enable. When logic high, parity generation transmitter section parity checking receiver section enabled. parity inserted between last word first stop bit. Parity even/odd. When logic high, even parity enabled; when logic low, parity enabled. Stick parity. Forces parity known value. parity enabled even parity selected, transmitter section will transmit parity logic low. Then, receiver section checks that incoming parity logic low. Break control. When set, forces a16450 transmit break condition. sout output forced logic state longer than full word transmission. Disable break clearing which causes sout return logic high. sout output logic high upon master reset. Divisor register access (drab). This must high access divisor registers. enables access receiver buffer transmitter holding registers.
Table lists word length associated with bits
Table Word Length Control Format
Word Length
bits bits bits bits
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table lists number stop bits word length associated with
Table Stop Control Format
Note:
indicates "don't care."
Word Length Note
bits bits bits bits
Number Stop Bits
Modem Control Register
modem control register controls modem interface outputs. Table describes modem control register format.
Table Modem Control Register Format
Signal
out1 out2
Description
Data terminal ready. user program control ndtr output. Request send. user program control nrts output. Output user program out1 control nout1 output. Output user program out2 control nout2 output. Enable loopback. When high, causes following: sout output logic high. input disconnected (i.e., ignored). output transmitter shift register internally connected (loopbacked) receiver shift register input. modem control inputs disconnected (i.e., ignored). modem control outputs used internally place modem control inputs. used. These read-only bits always logic low.
Line Status Register
line status register enables host processor examine data transfers. Table describes line status register format.
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table Line Status Register Format
Signal
Description
Receiver data ready. Indicates that incoming word been received transferred receiver buffer register. When logic high, receive data available interrupt generated. cleared reading receiver buffer register. Overrun error. Indicates that data wrote over unread data receiver buffer register. When logic high, receiver line status interrupt generated. cleared reading line status register. Parity error. Indicates that newly received data incorrect parity. When logic high, receiver line status interrupt generated. cleared reading line status register. Framing error. Indicates that newly received data invalid stop bit. When logic high, receiver line status interrupt generated. cleared reading line status register. Break interrupt. Indicates that break condition detected serial input. break condition occurs when serial data (sin) held logic longer than full word transmission. When logic high, receiver line status interrupt generated. cleared reading line status register.
thre Transmitter holding register empty. Indicates that a16450 ready accept data word from microprocessor transmission. When logic high, transmitter holding register empty interrupt generated. cleared reading interrupt register writing transmitter holding register. Transmitter empty. Indicates that transmitter holding register transmitter shift register both empty. used. This read-only always logic low.
Modem Status Register
modem status register enables microprocessr examine condition modem interface inputs. Table shows modem status register format.
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table Modem Status Register Format
Signal
dcts
Description
Delta clear send. Indicates that ncts input changed state since processor last read modem status register. When logic high, modem status interrupt generated. Delta data ready. Indicates that ndsr input changed since processor last read modem status register. When logic high, modem status interrupt generated. Trailing edge ring indicator. Indicates that trailing edge occurred input since processor last read modem status register. When logic high, modem status interrupt generated. Delta data carrier detect. Indicates that ndcd input changed state since processor last read modem status register. When logic high, modem status interrupt generated. Clear send. This complement ncts input. Data ready. This complement ndsr input. Ring indicator. This complement input. Data carrier detect. This complement ndcd input.
ddsr
teri
ddcd
Scratchpad Register
scratchpad register general-purpose register provided convenience user.
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Timing Waveforms
Figure shows read write cycle waveforms a16450 megafunction.
Figure Read Write Cycle Waveforms
Write Cycle
nads a[2.0] ncs2, cs1, csout nwr, din[7.0]
Active Valid Valid Valid
Read Cycle
nads a[2.0] ncs2, cs1, csout nrd, ddis dout[7.0]
Valid Active Valid Valid
Figure shows functional timing waveforms a16450.
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Figure a16450 Functional Timing Waveforms
Baudout Timing
nbaudout (divide-by-1) nbaudout (divide-by-2) nbaudout (divide-by-3) nbaudout (divide-by-n)
cycles (n-2) cycles
Receiver Timing
Sample intr (data ready receiver error) nrd,
Active Start Parity Stop
Transmitter Timing
sout thre nwr, nrd,
Start Data (5-8) Parity Stop (1-2) Start
Modem Control Timing
nwr, rts, dtr, out1, out2 cts, dsr, intr nrd,
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Variations Clarifications
a16450 differs from National NS16450 device following ways:
bidirectional d[7.0] NS16450 split into input din[7.0] output dout[7.0] a16450. dout[7.0] direct output output data multiplexer, tri-stated otherwise affected inputs. a16450 megafunction, address registers implemented registers, opposed latches NS16450 device. These registers clock source nads clock enable. a16450 megafunction uses single input primary clock source. NS16450 device uses crystal oscillator interface (xin input xout output) primary clock source.
Altera Corporation
Copyright 1995, 1996, 1997, 1998 Altera Corporation, Innovation Drive, Jose, 95134, USA, rights reserved. accessing this information, agree bound terms Altera's Legal Notice.

a16450 MegaCore® function implementing universal asynchronous receiver

Top Searches for this datasheet

Other recent searches