PulseC P2040A Panel Reduction Features approved method

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PulseC P2040A Panel Reduction Features approved method

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PulseC
P2040A
Panel Reduction Features
approved method attenuation Provides suppression Generates spread spectrum clock input frequency 110-MHz input frequency range Optimized VGA, SVGA, higher resolution panels Internal loop filter minimizes external components board space selectable high spread ranges selectable modulation rates cycle-to-cycle jitter SSON# SSON# control spread spectrum enable disable options Wide operating range (3V) output drives CMOS compatible outputs power CMOS design Supports most mobile graphic accelerator specifications Products available automotive temperature range. (See Spread Spectrum Range Selection tables.) Available 8-pin SOIC TSSOP
Block Diagram
CLKIN
Modulation Frequency divider Feedback divider Phase detector Loop filter
Output divider
ModOUT
Product Description
P2040A selectable spread spectrum frequency modulator designed specifically digital flat panel applications. P2040A reduces electromagnetic interference (EMI) clock source which provides system wide reduction clock dependent signals. P2040A allows significant system cost savings reducing number circuit board layers shielding that traditionally required pass regulations. P2040A uses most efficient optimized modulation profile approved implemented proprietary all-digital method. P2040A modulates output single order spread bandwidth synthesized clock and, more importantly, decreases peak amplitudes
harmonics. This results significantly lower system compared typical narrow band signal produced oscillators most frequency generators. Lowering increasing signal's bandwidth called spread spectrum clock generation. P2040A targeted toward digital flat-panel applications notebook PCs, palm-size PCs, office automation equipment, monitors.
Diagram
CLKIN ModOUT SSON#
12/9/02,
Alliance Semiconductor
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Modulation Selection (Commercial)
Spreading range 1.125 1.75 0.75 1.25 1.25 2.00 Reserved Reserved Modulation rate (Fin/40) 34.72 (Fin/40) 34.72 (Fin/40) 34.72 (Fin/40) 34.72 (Fin/40) 20.83 (Fin/40) 20.83 Reserved Reserved
Spread Range Selection (Automotive)
Spreading range 1.25 2.00 1.00 1.50 1.25 2.00 1.25 2.00 Modulation rate (Fin/40) 34.72 (Fin/40) 34.72 (Fin/40) 34.72 (Fin/40) 34.72 (Fin/40) 20.83 (Fin/40) 20.83 (Fin/40) 20.83 (Fin/40) 20.83
Spread Range Selection (Automotive)
Spreading range 1.00 1.50 0.70 1.00 1.15 2.00 1.15 1.75 Modulation rate (Fin/40) 34.72 (Fin/40) 34.72 (Fin/40) 34.72 (Fin/40) 34.72 (Fin/40) 20.83 (Fin/40) 20.83 (Fin/40) 20.83 (Fin/40) 20.83
12/9/02,
Alliance Semiconductor
Description
Name CLKIN SSON# ModOUT Type Description External reference frequency input. Connect externally generated reference signal. Digital logic input used select modulation rate. This internal pullup resistor. Digital logic input used select spreading range. This internal pullup resistor. Ground connection. Connect system ground. Digital logic input used enable spread spectrum function (active low). Spread spectrum function enabled when low. This internal pull-low resistor. Spread spectrum clock output. Digital logic input used select spreading range. This internal pullup resistor. Connect +3.3
Spread Spectrum Selection
"Modulation Selection" table defines possible spread spectrum options. optimal setting should minimize system fullest without affecting system performance. spreading described percentage deviation center frequency. (Note: center frequency frequency external reference input CLKIN, example, P2040A designed high resolution flat panel applications able support (1024 768) flat panel operating (Fin) clock speed. spreading selection provides percentage deviation ±0.75% from (see "Modulation selection" table). This results frequency ModOUT being swept from 64.51 65.49 modulation rate 56.24 (see "Modulation selection" table). example following illustration common reduction method notebook panel already been implemented most leading mobile graphic accelerator manufacturers.
Application Schematic Mobile Graphics Controllers
Modulated signal with ±0.75% deviation modulation rate 56.24 KHz. This signal connected back spread spectrum input (SSIN) graphics accelerator.
from graphics accelerator
CLKIN
ModOUT
0.1uF
SSON# X2040A
Digital control enable disable
12/9/02,
Alliance Semiconductor
Software Simulation
using PulseCore® EMI-Lator®1 electromagnetic interference simulation software, radiated system-level analysis made easier allow quantitative assessment reduction products. simulation engine this software already been characterized correlate electrical characteristics PulseCore reduction ICs. following illustration example simulation result. Please visit site www.alsc.com information obtain free copy demonstration EMI-Lator simulation software.
PulseCore® EMI-Lator® registered trademarks Alliance Semiconductor Corporation.
12/9/02,
Alliance Semiconductor
Absolute Maximum Ratings
Symbol VDD, TSTG Parameter Voltage with respect Storage temperature Operating temperature Commercial Operating temperature Automotive Rating -0.5 +7.0 +125 +125 Unit
Electrical Characteristics
Symbol Parameter ZOUT Input voltage Input high voltage Input current (pull-up resistor inputs SR0, MRA) Input high current (pull-down resistor input SSON#) Output voltage (VDD Output high voltage (VDD Static supply current Dynamic supply current (3.3 loading) Operating voltage Power-up time (first locked clock cycle after powerup) Clock output impedance 0.18 Unit
Electrical Characteristics
Symbol Parameter fOUT
Unit
Input frequency Output frequency Output rise time (0.8 Output fall time (2.0 Jitter (cycle cycle) Output duty cycle
measured into capacitive load
12/9/02,
Alliance Semiconductor
Mechanical Package Outline (8-Pin SOIC)
Inches
Millimeters 0.071 0.010 0.069 0.020 0.001 0.202 0.164 0.248 0.028 1.45 0.10 1.35 0.31 0.10 4.72 3.75 5.70 0.30 1.63 0.18 1.55 0.41 0.15 4.92 3.95 1.27 6.00 0.50 6.30 0.70 1.80 0.25 1.75 0.51 0.25 5.12 4.15
Symbol
0.057 0.004 0.053 0.012 0.004 0.186 0.148 0.224 0.012
0.064 0.007 0.061 0.016 0.006 0.194 0.156 0.236 0.020
P2040A
NUMBER YYWW
0.050
Note: Controlling dimensions millimeters. SOIC 0.074 grams unit weight
Mechanical Package Outline (8-Pin TSSOP)
Inches Symbol
Millimeters 0.047 0.006 0.041 0.012 0.008 0.122 0.177 0.260 0.030 0.05 0.80 0.19 0.09 2.90 4.30 6.20 0.45 1.00 3.00 4.40 0.65 6.40 0.60 6.60 0.75 1.10 0.15 1.05 0.30 0.20 3.10 4.50
0.002 0.007 0.004 0.114
0.118
YYWW
2040A
0.031 0.039
0.169 0.173 0.244 0.252 0.018 0.024
0.026
Note: Controlling dimensions millimeters. SOIC 0.034 grams unit weight
12/9/02,
Alliance Semiconductor
P2040A
Ordering Information
Part number A2040A-08ST A2040A-08SR A2040A-08TT A2040A-08TR I2040A-08ST I2040A-08SR I2040A-08TT I2040A-08TR P2040A-08ST P2040A-08SR P2040A-08TT P2040A-08TR Marking A2040A A2040A A2040A A2040A I2040A I2040A I2040A I2040A P2040A P2040A P2040A P2040A Package type 8-pin SOIC, tube 8-pin SOIC, tape reel 8-pin TSSOP, tube 8-pin TSSOP, tape reel 8-pin SOIC, tube 8-pin SOIC, tape reel 8-pin TSSOP, tube 8-pin TSSOP, tape reel 8-pin SOIC, tube 8-pin SOIC, tape reel 8-pin TSSOP, tube 8-pin TSSOP, tape reel 2,500 2,500 2,500 2,500 2,500 2,500 Quantity reel Temperature -40° 125° -40° 125° -40° 125° -40° 125° -40° -40° -40° -40°
Part Numbering Guide
Flow prefix: 2040
automotive temperature range (-40° 125° industrial temperature range (-40° commercial temperature range
Device number Deviation spread option identifier Device count Package identifier: SOIC tube SOIC tape reel TSSOP tube TSSOP tape reel
Licensed under U.S. patent numbers 5,488,627 5,631,920.
12/9/02,
Alliance Semiconductor
Copyright Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights, mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components life-supporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such life-supporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use.

PulseC P2040A Panel Reduction Features approved method

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