HMMC-3128 Wide Frequency Range: High Input Power Sensitivity: On-

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HMMC-3128 Wide Frequency Range: High Input Power Sensitivity: On-

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Packaged High Efficiency Divide-by-8 Prescaler Technical Data
HMMC-3128
Wide Frequency Range: High Input Power Sensitivity: On-chip pre- post-amps GHz) GHz) GHz) Pout (0.5 Vp-p) Phase Noise: -153 dBc/Hz Offset Single Supply Bias Operation Wide Bias Supply Range: volt operating range Differential with on-chip matching Package Type: Package Dimensions: Package Thickness: Lead Pitch: Lead Width: 8-lead SSOP Plastic Typ. 1.55 Typ. 1.25 Nom. 0.42 Nom.
Absolute Maximum Ratings[1]
25°C, unless otherwise indicated) Symbol |VCC VEE| VLogic Pin(CW) VRFin TBS[2] TSTG Tmax Parameters/Conditions Bias Supply Voltage Bias Supply Voltage Bias Supply Delta Logic Threshold Voltage Input Power Input Voltage RFin RFin Ports) Backside Operating Temp. Storage Temperature Maximum Assembly Temp. seconds max.) Units volts volts volts volts volts -1.5 -1.2 +165 Min. Max.
Description
HMMC-3128 packaged GaAs MMIC prescaler which offers frequency translation communications systems incorporating high-frequency oscillator circuits signal-path down conversion applications. prescaler provides large input power sensitivity window phase noise.
Notes: Operation excess parameter limit (except TBS) cause permanent damage device. MTTF hours 85°C. Operation excess maximum operating temperature (TBS) will degrade MTTF.
HMMC-3128 Specifications/Physical Properties,
25°C, unless otherwise listed) Symbol |ICC| |IEE| VRFin(q) VRFout VLogic Parameters Test Conditions Operating Bias Supply Difference[1] Bias Supply Current Quiescent Voltage appearing Ports Nominal Logic Level (VLogic contact self-bias voltage, generated on-chip) Units volts volts Min. Typ. Max.
volts 1.45 1.32 1.25
Note: Prescaler will operate over full specified supply voltage range. exceed limits specified Absolute Maximum Ratings section.
Specifications, 25°C,
Symbol in(max) in(min) Self-Osc. Parameters Test Conditions Maximum input frequency operation Minimum input frequency operation[1] (Pin dBm) Output Self-Oscillation Frequency[2] (Square-wave input) MHz, (Sine-wave input) Small-Signal Input/Output Return Loss GHz) Small-Signal Reverse Isolation GHz) Phase Noise dBm, offset from Carrier) Input Signal Time Variation Zero-Crossing GHz, dBm) Output Transition Time (10% rise/fall time) power level appearing RFin RFin GHz, Unused RFout RFout unterminated) power level appearing RFin RFin GHz, Both RFout RFout terminated) Power level appearing RFout RFout GHz, dBm, Referred Pin(in)) Second harmonic distortion output level GHz, Referred Pout (out)) Units dBc/Hz volts volts volts -2.0 -3.5 -4.5 Min. Typ. >-25 >-20 >-20 >-15 >-10 -153 -1.5 -2.5 0.42 0.37 Max.
Jitter Pout[3]
|Vout(p-p)|[4]
PSpitback
Pfeedthru
Notes: sine-wave input signal. Prescaler will operate down D.C. square-wave input signal. Minimum divide frequency limited input slew-rate. Prescaler exhibit this output signal under bias absence input signal. This condition eliminated input offset technique described page Fundamental output square wave's Fourier Series. Square wave amplitude calculated from Pout.
Applications
HMMC-3128 designed high frequency communications, microwave instrumentation, radar systems where phase-noise control circuitry broad-band frequency translation required.
properly divide. device will operate frequencies down when driven with squarewave. coupling (RFin) recommended most applications. device operated from either single positive single negative supply. positive supply operation pins nominally biased voltage +4.5 +6.5 volt range with (VEE) grounded. negative bias operation pins typically grounded negative voltage between -4.5 -6.5 volts applied (VEE).
Input Offset
prevent false triggers selfoscillation conditions, apply offset voltage between RFin RFin ports. This prevents noise spurious level signals from triggering divider.
GaAs MMICs sensitive. Proper precautions should used when handling these devices.
Operation
device designed operate when driven with either singleended differential sinusoidal input signal over bandwidth. Below prescaler input "slew-rate" limited, requiring fast rising falling edge speeds
150p
Bypass
Vpwr
SOIC w/Backside
Figure HMMC-3122 Simplified Schematic.
RFin RFin
5.80/6.20 3.80/4.00
Notes: dimensions MIN./MAX. millimeters. Refer JEDEC Outline MS-012 additional tolerances. Exposed heat slug area bottom 2.67 1.65
RFout RFout
4.80/5.00
1.35/1.75 0.10/0.25 1.27 0.33/0.51
0°/8°
0.19/.025 0.40/1.27
Figure Package Dimensions.
(+4.5 +6.5 volts) Monoblock Capacitor operate component from negative supply, ground each connection supply with negative voltage (-4.5 -6.5 bypassed ground with capacitor.
RFin RFin
RFout RFout
RFout should terminated ground blocking capacitor required positive bias configuration.)
Figure Assembly Diagram. (single-supply, positive-bias configuration shown)
HMMC-3128 Supplemental Data
25°C
25°C
High Power Mode
-0.2 -0.4
VLogic
INPUT POWER, (dBm)
ISupply (mA)
-0.6 -0.8
Power Mode
-1.0 -1.2 -1.4 -1.6 -1.8 -2.0
INPUT FREQUENCY, (GHz)
-VEE
Figure Typical Input Sensitivity Window.
Figure Typical Supply Current VLogic Supply Voltage.
25°C
-110 -115 -120 -125 -130 -135 -140 -145 -150 -155 -160 100K
Pout dBm) (dBm)
0.25 0.75
1.25 1.75
[dBc/Hz
OUTPUT FREQUENCY (GHz)
Figure Typical Phase Noise Performance.
Figure Typical Output Power Output Frequency, (GHz).
PSpitback (dBm)
-VEE dBm, 25°C
Unterminated RFout Port
-100 INPUT FREQUENCY, (GHz)
Both RFout Ports Terminated
Figure Typical "Spitback" Power. P(out) appearing input port.
Supplemental Information
Input Offset
long signal always present within input power specifications, there will problems with false triggering self-oscillations. this case, ground from unused input this, when combined with on-chip resistor will offset between inputs (i.e., RFin 10KQ ground, will 4.975 RFin will 5V). want offset note page resistor value ground will 12.45K 2.45K when
Biasing DC-Blocking
backside divider chip gold plated attached heat slug package. Also package capacitor connected between chip's topside rail heat slug making heat slug ground. majority cases, would exposed heat slug bottom package ground. typical positive bias setup with ground
along with package's heat slug. input output nodes each tied through will floating nominally that bias level (depending, course, input drive level appropriate output state) blocking capacitors will usually required. typical negative bias setup with ground along with package's heat slug. some cases, such level shifting subsequent stages, might want "float" package apply bias difference between VEE. such applications, package's heat slug must attached point that both good heat sink good ground.
Heat Slug/Bonding
exposed area package's backside heat slug pad) measures 2.67 1.65 (0.105" 0.065"). Anything larger than this would customer's preference convenience. test PCBs, 0.200" 0.082" with eight 0.020" diameter solder-filler thermal vias.
This data sheet contains variety typical performance data. information supplied should interpreted complete list circuit specifications. this data sheet term typical refers 50th percentile performance. additional information contact your local Agilent sales representative.
www.semiconductor.agilent.com Data subject change. Copyright 1999 Agilent Technologies 5968-4890E (11/99)

HMMC-3128 Wide Frequency Range: High Input Power Sensitivity: On-

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