T7633 Dual T1/E1 Terminator consists independent, highly integrated, s

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T7633 Dual T1/E1 Short-Haul Terminator
T7633 Dual T1/E1 Terminator consists independent, highly integrated, software-configurable, full-featured short-haul transceiver/framers. T7633 provides glueless interconnection from T1/E1 line digital system. Minimal external clocks needed. Only system clock/frame sync phase-locked line rate clock required. System diagnostic performance monitoring capability with integrated programmable test pattern generator/detector loopback modes provided.
Alarm reporting performance monitoring AT&T, ANSI, ITU-T standards. Programmable, independent transmit receive system interfaces 2.048 MHz, 4.096 MHz, 8.192 data rate. System interface master mode generation system frame sync from line source. Internal phase-locked loop (with external VCXO) generation system clock from line source.
Facility Data Link
Power Requirements Package
HDLC transparent modes. Automatic transmission detection ANSI T1.403 performance report message bitoriented codes. 64-byte FIFO both transmit receive directions.
Single supply. power: channel maximum. 144-pin TQFP package. Operating temperature range:
T1/E1 Line Interface
Microprocessor Interface
Full T1/E1 pulse template compliance. Receiver provides equalization loss. Digital clock data recovery. Line coding: B8ZS, HDB3, ZCS, AMI. Line interface coupling matching networks (120
MHz, 8-bit data interface, wait-states.
Intel Motorola interface modes with multiplexed demultiplexed buses. Directly addressable control registers.
Applications
T1/E1 Framer
Supports framing modes ESF, SLC*-96, T1DM DDS.
Customer Premises Equipment-CSU/DSU, routers, digital PBX, channel banks (CB), base transceiver stations (BTS-picocell), small switches, digital subscriber loop access multiplexers (DSLAM). Loop/Access-DLC/IDLC, DCS, (microcell/ macrocell), DSLAMs, multiplexers (terminal, synchronous/asynchronous, drop). Central Office-Digital switches, DCS, access concentrators, remote switch modules (RSM), DSLAMs. Test Equipment-Transmission/BERT tester.
Supports G.704 basic CRC-4 multiframe format framing procedures consistent with G.706. Supports unframed transmission format. signaling modes: transparent; 2-state, 4state, 16-state; 2-state 4-state; SLC-96 2-state, 4-state, 9-state, 16-state. signaling modes: transparent, CAS, CCS, IRMS.
registered trademark Lucent Technologies, Inc. Intel registered trademark Intel Corporation. Motorola registered trademark Motorola, Inc.
T7633 Dual T1/E1 Short-Haul Terminator
T1/E1 Framer
Feature Descriptions
independent T1/E1 channels each consisting T1/E1 short-haul line interface T1/E1 framer with HDLC formatting facility data link interface. Memory-mapped read write registers. Maskable interrupt events. Hardware software resets. Onboard software-selectable pseudorandom test pattern generator detector line performance monitoring. 3-state outputs. Single supply. tolerant inputs. power consumption: max.
T1/E1 Line Interface
Transmitter includes transmit encoder (B8ZS HDB3), pulse shaping, line driver. Five pulse equalization settings template compliance cross connect. Receive includes equalization, digital clock data recovery (immune false lock), receive decoder. CEPT/E1 interference immunity required G.703. Transmit jitter <0.02 Receive generated jitter <0.05 Jitter attenuator selectable transmit receive path. Jitter attenuation characteristics data pattern independent. with twisted-pair, twisted-pair, coaxial cable. Common transformer transmit/receive. Analog alarm signals less than greater than 10-bit 255-bit symbol periods (selectable). Digital alarm zeros (DS1) zeros (E1). Diagnostic loopback modes. Compliant with AT&T CB119(10/79); G.703(88), G.732(88), G.735-9(88), G.823-4(3/93), I.431(3/93); ANSI T1.102(93), 408(90); ETSI ETS-300-011(4/92), ETS-300-166(8/93), ETS-300-233(5/94, 3/95), TBR12(12/93, 1/96), TBR13(1/96); TR-TSY000009(5/86), TSY-000170(1/93), GR-253CORE(12/95), GR-499-CORE(12/95), GR-820CORE(11/94), GR-1244-CORE(6/95).
Framing formats: Compliant with standards ANSI T1.231 (1997), AT&T TR54016, AT&T TR62411 (1998). Unframed, transparent transmission formats. extended superframe (ESF). superframe (SF): SLC-96; T1DM DDS; T1DM with access. independent transmit receive framing modes when using formats. Compliant with CEPT framing recommendation: G.704 G.706 basic frame format. G.704 Section 2.3.3.4 G.706 Section 4.2: CRC-4 multiframe search algorithm. G.706 Annex CRC-4 multiframe search algorithm with timer interworking CRC-4 non-CRC-4 equipment. G.706 Section 4.3.2 Note monitoring CRC-4 checksum errors loss frame state. Framer line codes: DS1: alternate mark inversion (AMI); binary eight zero code suppression (B8ZS); per-channel zero code suppression; decoding bipolar violation monitor; monitoring eight fifteen intervals without positive negative pulses error indication. independent transmit receive path line code formats when using AMI/ZCS B8ZS coding. ITU-CEPT: AMI; high-density bipolar (HDB3) encoding decoding bipolar violation monitoring, monitoring four intervals without positive negative pulses error indication. Single-rail option.
Agere Systems Inc.
T7633 Dual T1/E1 Short-Haul Terminator
Feature Descriptions (continued)
T1/E1 Framer Features (continued)
Signaling: DS1: extended superframe 2-state, 4-state, 16-state per-channel robbed bit. DS1: superframe 2-state 4-state perchannel robbed bit. DS1: SLC-96 superframe 2-state, 4-state, 9-state, 16-state per-channel robbed bit. DS1: channel-24 message-oriented signaling. CEPT: channel associated signaling (CAS) T7230A mode common channel signaling (CCS). CEPT: international remote switching module (IRMS). Transparent (all data channels). Alarm reporting, performance monitoring, maintenance: ANSI T1.403-1995, AT&T 54016, G.826 standard error checking. Error status counters: Bipolar violations. Errored frame alignment signals. Errored checksum block. CEPT: received Errored, severely errored, unavailable seconds. Selectable errored event monitoring errored severely errored seconds processing with programmable thresholds errored severely errored second monitoring. CEPT: Selectable automatic transmission line. CEPT: coded remote CRC-4 error events. Programmable automatic on-demand alarm transmission: Automatic transmission remote frame alarm line while loss frame alignment state. Automatic transmission alarm indication signal (AIS) system while loss frame alignment state. Multiple loopback modes. Optional automatic line payload loopback activate deactivate modes. CEPT nailed-up connect loopback CEPT nailed-up broadcast transmission TS-X TS-0 transmit mode. Selectable test patterns line transmission. Detection framed unframed pseudorandom quasi-random test patterns. Programmable squelch idle codes.
System interface: Autonomous transmit receive system interfaces. Independent transmit receive frame synchronization input signals. Independent transmit receive system interface clock. 2.048 Mbits/s, 2.048 concentration highway interface (CHI) default mode. Optional 4.096 Mbits/s 8.192 Mbits/s data rates. Optional 4.096 MHz, 8.192 MHz, 16.384 frequency system clock. Programmable clock edge latching frame synchronization signals. Programmable clock edge latching transmit receive data. Programmable byte offset. Programmable master mode generation transmit from internal logic with timing derived from receive line clock signal. Digital phase comparator clock generation receive transmit paths.
Facility Data Link
HDLC transparent mode. Automatic transmission performance report messages (PRM). Detection PRM. Detection ANSI bit-oriented codes. 64-byte FIFO both transmit receive directions. Programmable FIFO full- empty-level interrupt.
SLC-96: transmit receive register access bits.
User-Programmable Microprocessor Interface
read write access with wait-states. 12-bit address, 8-bit data interface. Programmable Intel Motorola interface modes. Demultiplexed multiplexed address data bus. Directly addressable internal registers. clock required.
Agere Systems Inc.
T7633 Dual T1/E1 Short-Haul Terminator
Functional Description
RECEIVE CHANNEL [1-2] RTIP_RPD[1-2] RECEIVE LINE INTERFACE UNIT (RLIU) RECEIVE FRAMER UNIT RECEIVE ELASTIC STORE FRAMES)
TRANSMIT CONCENTRATION HIGHWAY INTERFACE (TCHI)
TCHICK[1-2] TCHIFS[1-2] TCHIDATA[1-2] TCHIDATAB[1-2]
RRING_RND[1-2]
SYSCK[1-2] RLCK[1-2] TCHICK RLCK RECEIVE CHANNEL DIGITAL PHASE DETECTOR
RFRMCK[1-2], RFRMDATA[1-2], RFS[1-2], RSSFS[1-2], RCRCMFS[1-2] RFDL[1-2], RFDLCK[1-2]
RECEIVE FACILITY DATA LINK MONITOR (HDLC TRANSPARENT FRAMING)
RECEIVE SIGNALING UNIT (DS1: ROBBED-BIT CEPT: TS16)
DIV-RLCK[1-2], DIV-TCHICK[1-2], TCHICK-EPLL[1-2]
TRANSMIT CHANNEL [1-2] TRANSMIT FACILITY DATA LINK MONITOR (HDLC TRANSPARENT FRAMING) PLLCK[1-2] TRANSMIT SIGNALING UNIT (DS1: ROBBED-BIT CEPT: TS16) RCHICK TRANSMIT CHANNEL DIGITAL PHASE DETECTOR
DIV-PLLCK[1-2], DIV-RCHICK[1-2], PLLCK-EPLL[1-2]
TFDL[1-2], TFDLCK[1-2] XMIT FRAMER TCLK TTIP[1-2] TRANSMIT LINE INTERFACE UNIT (XLIU) TRANSMIT ELASTIC STORE FRAMES)
TRING[1-2] TND[1-2], TPD[1-2], TLCK[1-2]
TRANSMIT FRAMER UNIT
RECEIVE CONCENTRATION HIGHWAY INTERFACE (RCHI)
RCHICK[1-2] RCHIFS[1-2] RCHIDATA[1-2] RCHDATAB[1-2]
TFS[1-2], TSSFS[1-2], TCRCMFS[1-2]
MICROPROCESSOR INTERFACE
MPMODE MPMUX
A[11:0]
AD[7:0]
ALE_AS
RD_R/W
WR_DS
RDY_DTACK
INTERRUPT
MPCK
5-4512(F).cr.2
Figure T7630 Block Diagram (One Channels)
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com AMERICA: Agere Systems Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18109-3286 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 3210-12, 32/F, Tower Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, (44) 1344
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liab ility assumed result their application. Agere, Agere Systems, Agere logo trademarks registered trademark Agere Systems Inc.
Copyright 2002 Agere Systems Inc. Rights Reserved
1998 PN98-146TIC

T7633 Dual T1/E1 Terminator consists independent, highly integrated, s

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