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Section line overhead termination/generation: line-side SFI-4 interfac


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MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD) SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Section line overhead termination/generation: line-side SFI-4 interface, either: STS-192/STM-64 Four STS-48/STM-16 system interface, either: STS-192/STM-64 Four STS-48/STM-16 Low-voltage differential signal (LVDS) line system interfaces operating (T-Pro TD-Pro). differential system interfaces operating (T-Pro). Path processing: Full receive1 transmit path processing valid2 STS-1 concatenated payloads from STS-3c STS-48c. Flexible (hitless switching) interfaces (most DWDM applications will require backplane interface3): MARS10G T-Pro system transmit (add) interface consists four input ports which operate simultaneously. system transmit data path includes selection function which select input data STS-1 granularity. maximum bandwidth selected transmit signals Gbits/s: Mbits/s ports backplane redundancy/mate-port with clock data recovery. Gbits/s ports backplane redundancy/mate-port with clock data recovery.
MARS10G TD-Pro system transmit (add) interface consists input port. maximum bandwidth transmit signals Gbits/s: 16/4 Mbits/s secondary line interface (SFI-4) port allowing optics-to-optics (OEO) applications (forward contraclocked STS-192/STM-64/STS-48/STM-16). MARS10G T-Pro system receive (drop) data path provides splitter function following four output interfaces (each line Mbits/s backplane port STS-12. line Gbits/s backplane port either aggregate four STS-12s single STS-48): Mbits/s ports backplane redundancy/mate-port with clock data recovery generation. Gbits/s ports backplane redundancy/mate-port with clock data recovery. MARS10G TD-Pro system receive (drop) data path provides: 16/4 Mbits/s secondary line interface (SFI-4) port (forward contraclocked STS-192/STM-64/STS-48/STM-16).
Gbits/s cross connect: Independent Gbits/s cross connect each data path (transmit receive) with dual connection maps synchronized switching. Mate-port mate interface: Interconnects MARS10G T-Pros different line cards supporting 1:1, UPSR, BLSR ring applications. Reduces size cross connect hardware some protection switching architectures. Loopbacks: Terminal facility loopbacks line interface. Terminal loopbacks each system backplane interfaces. Regenerator loopback facility line interface.
Receive used indicate line interface system data flow direction, while transmit used indicate system line interface data flow direction. Valid means concatenated payloads must begin STS-3 boundary. DWDM version (MARS10G TD-Pro) product does support backplane drivers. applications where backplane required, recommended MARS10G T-Pro, SONET/SDH version. Mbits/s groups lines grouped together parallel line speed Special case: shortened forms follows: 622, 622.
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD) SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Features (continued)
General (continued)
regenerator loopback mode, generates AIS-L receive LOS, LOF, clock failure. Synchronizes receive data frames detects severely errored framing (SEF) loss frame (LOF). also inserts framing bytes (A1, transmit data. Supports enhanced framing (A1, A2). Performs frame synchronous scrambling descrambling STS-192/STM-64/STS-48/STM-16 data. Detects loss signal (LOS) with provisionable window from Extracts 64-byte 16-byte section trace message (J0) from receive data optionally stores compares internal register bank. Unstable mismatched messages detected. Optionally inserts 64-byte 16-byte section trace message fixed pattern byte transmit data. Extracts outputs serial link transport overhead (TOH) bytes incoming data (both receive transmit paths) inserts transport overhead bytes outgoing data (both receive transmit paths) using corresponding serial input. Extracts, integrates, stores automatic protection switch (APS) channel bytes (K1, receive data detects protection switch failure alarms. Inserts bytes transmit data from internal registers from overhead bytes data. Detects line alarm indication signal (AIS-L) remote defect indication (RDI-L) based byte receive data. Inserts AIS-L RDI-L transmit data. Optionally inserts RDI-L automatically LOS, LOF, line defects. Extracts, integrates, stores synchronization status byte (S1) receive data. Inserts synchronization status byte into transmit data from internal register from value encoded transmit frame sync input. Calculates, detects, counts section line BIP-8 errors (B1, receive data inserts BIP-8 transmit data. Supports either (B1, block (B1) error accumulation, each separately provisionable. Extracts counts line remote errors (REI-L) receive data (M1) inserts REI-L transmit data based errors (provisionable based block errors). Agere Systems Inc.
Transparency: Full bidirectional transparency support with timing independence (pointer processor) enabled disabled transmit receive directions, optionally, with steps stacked overhead transparency. Tandem connection maintenance (TCM) receive transmit data paths, STS-1 granularity, originate terminate tandem connection. Built-in PRBS generator monitor with STS-12 granularity self test system diagnostics. microprocessor interface configured operate with most commercial microprocessors MHz. IEEE 1149.1 port with memory BIST boundary scan (JTAG). Low-power operation with tolerant1) inputs outputs. Selectable powerup only required system ports. power given configuration determined number active ports/lines many internal functions active. MARS10G T-Pro version, approximately line line. MARS10G TD-Pro version, approximately sixteen-wire secondary line SFI-4 STS-192/STS-48/STM-64/STM-16 interface. 1724-pin FCBGA (flip-chip ball grid array) package. temperature range.
Line Interface
Supports maximum Gbits/s data bandwidth composed either following: 16-bit parallel Mbits/s STS-192), forward clocked interface. four 4-bit parallel Mbits/s STS-48), forward clocked interfaces. Optional AIS-L regeneration receive line interface.
Tolerant means inputs will safely survive application input voltages should exceed normal operation.
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD) SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor Path Processing
Features (continued)
System Interface
MARS10G T-Pro version, clock/data recovery (CDR) 64-byte buffer skew compensation direction. Path overhead timing drop direction. Port selection-data selected (groomed) STS-1 granularity, selected maximum bandwidth Gbits/s from following system ports: redundant Mbits/s parallel backplane interfaces (T-Pro only). redundant Gbits/s backplane interfaces (T-Pro only). Secondary line SFI-4 interface consisting 4-bit wide Mbits/s) 16-bit parallel port Mbits/s) forward contraclocked STS-192/STM-64/STS-48/STM-16 (TD-Pro only): secondary line interface functions identically complementary line interface (see Line Interface page MARS10G T-Pro version, mate-port functionality used connect MARS10G T-Pro devices different line cards using either Mbits/s Gbits/s backplane interface port, while other backplane interface ports continue redundant data operations. Independent Gbits/s cross connect with STS-1 granularity transmit receive data paths, with dual connection maps. MARS10G T-Pro version, port selection (4:1) transmit/receive cross connects switched independently mutually synchronized either software, external, overhead byte trigger. Optional generation external trigger drop direction. Outputs path alarm information each receive overhead bytes drop data (E1/F1). Alarms TFRM out-of-buffer range interface.
Implements hardware portion TIM-P TIM-S code processing section user channel (F1) orderwire channels (E1, receive data transmit data. Interprets pointer bytes (H1, each incoming detects loss pointer (LOP) path AIS. Supports STS-1 level provisioning bits inclusion/exclusion value detection. Generates pointer bytes each outgoing adapt incoming data drop frequency phase. Supports STS-1 level provisioning pass through overwriting generated bits. Pointer generation bypassed synchronous applications. Optionally inserts path outgoing pointer bytes during LOS, LOF, SEF, TIM-S, line defects. Optionally inserts path each outgoing LOP, TIM-P, path defects corresponding incoming under software control. Extracts 64-byte 16-byte path trace message (J1) from sixteen selectable receive channels (one STS-12) stores internal register bank. Optionally compares message expected message stored internal register bank detects unstable mismatched message. Calculates, detects, accumulates path BIP-8 errors (B3) each receive (provisionable based block errors). Provides signal fail detection with provisionable BER. Optionally inserts path transmit byte based receive errors. Extracts counts path (provisionable block basis) each receive (G1). Detects path unequipped, payload label mismatch (PLM), optionally, payload defect indication (PDI) byte each receive STS. Optionally inserts AIS-P downstream ERDI-P upstream PLM-P UNEQ-P. Inserts unequipped signal each transmit under software control. Detects 1-bit enhanced path each receive (G1). Path overhead insertion/extraction through serial ports both transmit receive data paths.
Agere Systems Inc.
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD) SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Features (continued)
Mate-Port-Mate-to-Mate Interface
OC-48 OC-48 SYSTEM INTERFACE LINE INTERFACE OC-12 OC-12 OC-12 OC-12 TDCS6440G TDCS6440G TDCS6440G TDCS6440G
mate interface MARS10G T-Pro device mate-port function using dual redundant system ports. mate-to-mate backplane interface allows MARS10G T-Pro device, different line cards, connected each other using (LVDS) (CML) backplane signals support 1:1, UPSR, BLSR ring applications. Concurrently, other ports (2.5 MHz, respectively) will continue able carry redundant data. Advantages mate interface follows: This feature will enable switching software reside line cards instead switch cards UPSR BLSR applications. This will help reduce software development costs streamlining software architecture switch cards partitioning software switch cards line cards. feature will enable more than reduction size cross connect hardware protection switching case. These savings will apply following architectures: Redundant architectures with framer cross connect same card. Simplex equipment protection duplex network protection architectures.
OC-48
MARS10G T-Pro
REDUNDANT CROSS-CONNECT CARDS
Figure SONET/SDH with Redundant System Connections
OC-48 OC-48 OC-48 OC-12 OC-12 OC-12 OC-12 LINE INTERFACE SYSTEM INTERFACE
MARS10G TD-Pro
OC-192
Figure DWDM/OADM Concentrator
Sample Applications
OC-12
LINE INTERFACE SYSTEM INTERFACE
SONET/SDH add-drop multiplex equipment. SONET/SDH terminal equipment. SONET/SDH digital cross-connect equipment. SONET/SDH digital line-card with mate-port connect. SONET/SDH test equipment. packet over SONET/SDH equipment. SONET/SDH DWDM equipment.
OC-12 OC-12 TOTAL) OC-12 OC-12 OC-12
MARS10G T-Pro TD-Pro
OC-192
Figure Transparent
Agere Systems Inc.
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD) SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Sample Applications (continued)
MARS10G T-Pro
LINE
SYSTEM
OC-192
EAST LINE CARD
REDUNDANT CROSS-CONNECT SWITCH CARDS
TRIB CARD
MATE
OC-192
LINE
SYSTEM
WEST LINE CARD
MARS10G T-Pro
TRIB CARD
Figure Mate-Port Connect using Interface with Cross Connect Connections using Redundant Interfaces
Agere Systems Inc.
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD) SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Description
MARS10G T-Pro MARS10G TD-Pro devices Agere Systems' next generation system-on-a-chip MARSfamily framers. MARS10G T-Pro/MARS10G TD-Pro used terminate transport overhead STS-192 (STM-64) signal four STS-48 (STM-16) signals, maximum bandwidth Gbits/s. performs path pointer processing synchronize incoming data streams outgoing frequency phase. MARS10G T-Pro/MARS10G TD-Pro provisioned support STS-1 (AU-3) STS-Nc (AU-4-Xc) payloads from single STS-192c (AU-4-64c) channel STS-1 (AU-3) channels. MARS10G T-Pro version, system interface four port interfaces which operate concurrently with redundant backplane interfaces (622 GHz). backplane interface performs clock data recovery transmit data. drop data accompanied with clock, therefore assumes clock data recovery destination. backplane interfaces support port selection incoming data, splitter capability drop data. backplane interface system side, port selector permits STS-1 level selection from redundant sets independently timed incoming STS-12s/STS-48s. duplicated sets outgoing STS-12s/STS-48s created. receive transmit cross connects provide STS-1 level grooming both directions. port selector configured modes. backplane interface mode, port selector acts work/protect switch. space switch mode, programable configuration maps allow hitless space switching STS-1 level granularity between A_DATA1, A_DATA2, A2488DATA1, A2488DATA2. Also, space switch backplane selector) synchronized switch conjunction with cross connect. MARS10G TD-Pro version, secondary line interface provides connection second fiber used terminate transport overhead STS-192/STS-48/STM-64/STM-16 signal (bandwidth Gbits/s). performs path pointer processing synchronize incoming data streams outgoing frequency phase. provisioned support STS-1 (AU-3) STS-Nc (AU-4-Xc) payloads from single STS-192c (AU-4-64c) channel STS-1 (AU-3) channels. secondary line interface equivalent features (primary) line interface functions. Overall block diagrams shown Figure page Figure page microprocessor interface allows external processor access MARS10G T-Pro/MARS10G TD-Pro configuration maintenance. microprocessor interface designed support various 16-bit microprocessors with minimal glue logic. MARS10G T-Pro/MARS10G TD-Pro includes IEEE 1149.1 compliant JTAG port support boundary scan memory BIST.
Agere Systems Inc.
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD) SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Description (continued)
TRANSMIT DATA FLOW SYSTEM INTERFACE LINE INTERFACE
TXSYNC_N_[1-4]
TPPBYP_[1-4] ETPOHVALID ETPOHSYNC ETPOHDAT_[7:0] ETPOHFP ETPOH_CLK ITPOHVALID ITPOHSYNC ITPOHDAT_[7:0] ITPOHEN ITPOHFP ITPOH_CLK
ETTOHVALID ETTOHSYNC ETTOHDAT_[7:0] ETTOHFP ETTOH_CLK
ITTOHVALID ITTOHSYNC ITTOHDAT_[7:0] ITTOHEN ITTOHFP ITTOH_CLK
Agere Systems Inc.
TRANSMIT LINE INTERFACE RECEIVE LINE INTERFACE
RST_N
HIZ_N
TFRM_[1,5,9,13] T_CLK_[1-16] Insertion INTERFACE
TRANSMIT LINE (TX)
TRANSMIT SECTION/LINE OVERHEAD GENERATION
AFRM
TD_[1:16]
PATH OVERHEAD INSERTION/ EXTRACT INTERFACE TRANSMIT POINTER GENERATOR TRANSMIT PATH OVERHEAD TRANSMIT POINTER
(48:12) TRANSMIT CROSS CONNECT
Extraction INTERFACE TRANSMIT SECTION/LINE OVERHEAD TERMINATOR (Rx)
T_CLKO_[1,5,9,13]
INTERFACE SYSTEM TERMINAL LOOPBACK LINE FACILITY LOOPBACK
PROCESSOR
INTERPRET
TRANSMIT ALIGNMENT FIFO
TRANSMIT PATH PROCESSOR
TRANSMIT SYSTEM INTERFACE
SECTION TRACE BUFFER
PART_L
SECTION TRACE BUFFER
PATH TRACE BUFFER PATH TRACE BUFFER
RECEIVE PATH PROCESSOR
TRANSPARENCY
A_CLKL ADATA1_[16:1] A2488DATA1_[4:1] ADATA2_[16:1] A2488DATA2_[4:1] TADCC1_[1-4] TADCC2_[1-4] TADCK_[1-4] TADSYN_[1-4] AFRMO
TRANSMIT SYSTEM INTERFACES
LINE TERMINAL LOOPBACK
REGEN LOOPBACK
REGEN LOOPBACK
TRANSPARENCY RECEIVE DROP CROSS CONNECT
MATE ALIGNMENT FIFO
SYS_LINE
RECEIVE SYSTEM INTERFACES
RECEIVE SECTION/LINE OVERHEAD GENERATOR (Tx) Insertion INTERFACE
RECEIVE LINE (Rx)
INTERFACE
RECEIVE SECTION/LINE OVERHEAD TERMINATION Extraction INTERFACE
RECEIVE RECEIVE RECEIVE PATH POINTER POINTER OVERHEAD INTERPRET PROCESSOR GENERATOR
PATH OVERHEAD INSERT/ EXTRACT INTERFACES
RECEIVE SYSTEM DROP INTERFACE
R_CLK_[1-16] RD_[1:16]
RDDSYN_[1-4] RDDCK_[1-4] RDDCC_[1-4] DDATA1_[16:1] D2488DATA1_[4:1] DDATA2_[16:1] D2488DATA2_[4:1] DFRM D_CLKL
R_CLKO_[1,5,9,13]
RFRMO_[1,5,9,13]
MICROPROCESSOR INTERFACE
JTAG INTERFACE
PM_CLK INT_N TEA_N TA_N RW_N DS_N TS_N CS_N ADDRESS_[15:0] DATA_[15:0] PARITY_[1:0] PCLK IRPOHVALID IRPOHSYNC IRPOHDAT_[7:0] IRPOHEN IRPOHFP IRPOH_CLK ERPOH_CLK ERPOHVALID ERPOHSYNC ERPOHDAT_[7:0] ERPOHFP RPPBYP_[1-4]
ERTOHVALID ERTOHSYNC ERTOHDAT_[7:0] ERTOHFP ERTOH_CLK
RECEIVE DATA FLOW LINE INTERFACE SYSTEM INTERFACE
Figure MARS10G T-Pro (TSOT1610GP) Block Diagram
PARITY_MODE PARITY_EN MPMODE_[1:0]
RXSYNC_N_[1-4]
IRTOHVALID IRTOHSYNC IRTOHDAT_[7:0] IRTOHEN IRTOHFP IRTOH_CLK
TRST_N
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD) SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Description (continued)
TRANSMIT DATA FLOW SECONDARY LINE INTERFACE LINE INTERFACE
TXSYNC_N_[1-4] TPPBYP_[1-4] ETPOHVALID ETPOHSYNC ETPOHDAT_[7:0] ETPOHFP ETPOH_CLK ITPOHVALID ITPOHSYNC ITPOHDAT_[7:0] ITPOHEN ITPOHFP ITPOH_CLK
ETTOHVALID ETTOHSYNC ETTOHDAT_[7:0] ETTOHFP ETTOH_CLK
ITTOHVALID ITTOHSYNC ITTOHDAT_[7:0] ITTOHEN ITTOHFP ITTOH_CLK
RST_N
HIZ_N
TRANSMIT LINE INTERFACE RECEIVE LINE INTERFACE
TFRM_[1,5,9,13] T_CLK_[1-16] Insertion INTERFACE TRANSMIT LINE (TX) INTERFACE
SYSTEM TERMINAL LOOPBACK LINE FACILITY LOOPBACK
TRANSMIT SECTION/LINE OVERHEAD GENERATION
TRANSMIT SECONDARY LINE INTERFACE
TD_[1:16] T_CLKO_[1,5,9,13]
PATH OVERHEAD INSERTION/ EXTRACT INTERFACE (48:12) TRANSMIT TRANSMIT PATH POINTER OVERHEAD GENERATOR PROCESSOR TRANSMIT POINTER TRANSMIT CROSS CONNECT
Extraction INTERFACE TRANSMIT SECTION/LINE OVERHEAD TERMINATOR (Rx)
INTERPRET
TRANSMIT SECONDARY LINE (Rx) INTERFACE
SYSTEM FACILITY LOOPBACK
A_CLK_[1-4] A_RD_[16:1] AFRMO_[1-4] A_CLKO_[1-4]
REGEN LOOPBACK SECTION TRACE BUFFER
TRANSMIT PATH PROCESSOR PATH TRACE BUFFER PATH TRACE BUFFER RECEIVE PATH PROCESSOR RECEIVE RECEIVE RECEIVE PATH POINTER POINTER OVERHEAD INTERPRET PROCESSOR GENERATOR PATH OVERHEAD INSERT/ EXTRACT INTERFACES MICROPROCESSOR INTERFACE RECEIVE DROP CROSS CONNECT TRANSPARENCY
REGEN LOOPBACK
PART_L
SECTION TRACE BUFFER
SYS_LINE
TRANSPARENCY
RECEIVE SECONDARY LINE INTERFACE
RECEIVE LINE (Rx) INTERFACE
RECEIVE SECTION/LINE OVERHEAD TERMINATION Extraction INTERFACE
RECEIVE SECTION/LINE OVERHEAD GENERATOR (Tx) Insertion INTERFACE
RECEIVE SECONDARY LINE (Tx) INTERFACE
D_CLKO_[1-4] D_TD_[1:16] D_CLK_[1-4] DFRM_[1-4]
R_CLK_[1-16] RD_[1:16]
R_CLKO_[1,5,9,13] RFRMO_[1,5,9,13]
JTAG INTERFACE
TRST_N
RECEIVE DATA FLOW LINE INTERFACE SECONDARY LINE INTERFACES
Figure MARS10G TD-Pro (TSOT1610GPD) Block Diagram
ERTOHVALID ERTOHSYNC ERTOHDAT_[7:0] ERTOHFP ERTOH_CLK
PM_CLK INT_N TEA_N TA_N RW_N DS_N TS_N CS_N ADDRESS_[15:0] DATA_[15:0] PARITY_[1:0] PCLK IRPOHVALID IRPOHSYNC IRPOHDAT_[7:0] IRPOHEN IRPOHFP IRPOH_CLK ERPOH_CLK ERPOHVALID ERPOHSYNC ERPOHDAT[7:0] ERPOHFP RPPBYP_[1-4]
PARITY_MODE PARITY_EN MPMODE_[1:0]
RXSYNC_N_[1-4]
IRTOHVALID IRTOHSYNC IRTOHDAT_[7:0] IRTOHEN IRTOHFP IRTOH_CLK
Agere Systems Inc.
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD) SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Ordering Information
Device Code MARS10G T-Pro (TSOT1610GP) MARS10G TD-Pro (TSOT1610GPD)
Maximum junction temperature
Package 1724-pin FCBGA 1724-pin FCBGA
Ambient Temperature
Comcode 700045919
Agere Systems Inc.
IEEE registered trademark Institute Electrical Electronics Engineers, Inc. SFI-4 registered trademark Westinghouse Electric Corporation.
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway Allentown, 18109-9138 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 3210-12, 32/F, Tower Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. Agere, Agere Systems, Agere Logo trademarks Agere Systems Inc. MARS trademark Agere Systems Inc.
Copyright 2003 Agere Systems Inc. Rights Reserved
June 2003 PB03-036SONT

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