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TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
documentation package TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1 system chip consists following documents:
Register Description. This document available password protected website. UltramapperLite Product Description (this document), System Design Guide, UltramapperLite Hardware Design Guide. These documents available public website shown below.
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622/155 Mbits/s SONET/SDH Front
LOPOH
DS3/E3/DS2/DS1/E1 Tributary Termination
High-Speed
Mb/STS-12/STM-4 Mb/STS-3/STM-1 Clock Data
LOPOH
(X3) x28/x21 DS1/J1/E1 TPG/TPM
TMUX STSPP
Clock/Sync
SPEMPR (x3) (3-5)
System Interfaces
Protection Link Mb/STS-12/STM-4 Mb/STS-3/STM-1 Clock Data
STS-12/ STM-4/ STS-3/ STM-1
MRXC SPEMPR (x3) (0-2) (x3) x28/x21 VTMPR
(x6) DS3/E3 (x3) STS-1 (x3) NSMI (x3) STS-1
(Total STS-1 Max)
DS1/J1/E1 VT/TU DS2/E2 DS3/E3
STS-1
Low-Speed
Transport Modes 4DS1/J1/E1 (x30): x28/x21 prot. 4DS2/E2 (X30): x21/x12 prot. 4VT/TU (X30): x28/x21 prot.
Miscellaneous
(x3)
(x3) (x3)
JTAG
MCDR
x28/x21 DS1/E1
DS3/E3
Power pins shown
JTAG
(x3) (x3) (x3) STS-3/STM-1 Mate DS3/E3 (Optional) Interconnect
DS2, VC12 VC11 Clocks
DS1XCLK, E1XCLK
TOAC POAC DS3XCLK, E3XCLK
Figure Block Diagram High-Level Interface Definition
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Table Contents
Contents Page
Introduction Features TMUX Features (x1) STS-12 Pointer Processor (STSPP) Features (x1) Cross Connect (STSXC) Features (x1) Mate Clock Data Recovery (MCDR) Features (x1) STS-1 Line Terminating (STS1LT) Features (x3) Synchronous Payload Envelope Mapper (SPEMPR) Features (x6) Test Pattern Generator/Monitor (TPG/TPM) Features (x1) Virtual Tributary Mapper (VTMPR) Features (x3) 2.10 M13/E13 Features (x3) 2.10.1 Features 2.10.2 Features 2.11 DS1/J1/E1 Framing Features (FRM) (3x28/21) 2.12 Multirate Cross Connect (MRXC) Features (x1) 2.13 DS1/E1 Digital Jitter Attenuation (DJA) Features (3x28/21) 2.14 DS3/E3 Digital Jitter Attenuation (DJA) Features (x1) 2.15 Microprocessor Unit (MPU) Features (x1) 2.16 JTAG Overview Application Diagrams STS-12/STM-4 Four Device Application STS-3/STM-1 to/from DS3/E3 Application UPSR HO/LO Application with STS-12/STM-4 Transport (Mixed DS3/E3 DS1/E1) Application Transport Unprotected Add/Drop Ring Application STS-12/STM-4 to/from DS3/E3 TransMUX Application Portless TransMUX Application STS-12/STM-4 to/from DS3/E3 Application STM-1 Protection Application Block Description TMUX/Clock Data Recovery (CDR) Blocks 5.1.1 Transmit Path Section/Line Overhead 5.1.2 Receive Path Section/Line Overhead 5.1.3 Pointer Interpreter 5.1.4 Path Termination Function STS-12/STM-4 Pointer Processor (STSPP) Block STS-1 Line Terminating (STS1LT) Block Cross Connect (STSXC) Block Mate Interconnect Clock Data Recovery (MCDR) Block SPE/AU-3 Mapper (SPEMPR) Block VT/TU Mapper (VTMPR) Block 5.7.1 Receive Direction 5.7.2 Transmit Direction M13/E13 Multiplexer (M13/E13 MUX) Blocks 5.8.1 5.8.2 Multirate Cross Connect (MRXC) Block 5.10 Digital Jitter Attenuator (DS1/E1 DJA) Block 5.11 Digital Jitter Attenuator (DS3/E3 DJA) Block Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Table Contents
5.12 Test Pattern Generator/Monitor (TPG/TPM) Block 5.13 Low-Order Path Over Head 5.14 Framer Block 5.14.1 Line Decoder/Encoder 5.14.2 Receive Frame Aligner/Transmit Frame Formatter 5.14.3 Receive Performance Monitor 5.14.4 Signaling Processor 5.14.5 Facility Data Link (FDL) Processor 5.14.6 HDLC Unit Glossary
Figure
Page
Figure Block Diagram High-Level Interface Definition Figure STS-12/STM-4 Four Device Configuration Figure STS-3/STM-1 to/from DS3s/E3s Configuration. Figure UPSR HO/LO with Configuration. Figure DS1s/42 Plus DS3s/E3s Mapped Multiplexed to/from STS-12/STM-4. Figure Three EC-1s, Plus Three DS3s/E3s, Plus DS1s/21 Add/Dropped from OC-12 Ring Figure DS3s/E3s Transmultiplexed to/from VT-Mapped STS-12/STM-4. Figure Translate M13/E13-Mapped STS-1s/STM-0s VT-1.5/TU-11/TU-12-Mapped STS-1s/STM-0s Conversely Translate VT-1.5/TU-11/TU-12-Mapped STS-1s/STM-0s M13/E13-Mapped STS-1s/STM-0s Figure Device Termination STS-12/STM-4 Figure STM-1 Protection Configuration.
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Multiplexes/demultiplexes three VC-3 signals to/from STM-1 (AU-4) signal TUG-3 construction. Provides STS-1-only mode receive transmit directions. Provides separate protection input support Provides SONET/SDH loss-of-signal (LOS), out-of-frame (OOF), loss-of-frame (LOF), loss-of-clock (LOC) detection. Provides STS-12/STM-4/STS-3/STM-1/STS-1 selectable scrambler/descrambler functions. Provides B1/B2/B3 generation/detection STS-12/ STM-4/STS-3/STM-1/STS-1. Provides STS-12/STM-4/STS-3/STM-1/STS-1 pointer interpretation. Complies with GR-253-CORE, T1.105, G.707, G.783, G.806, G.821, ETSI 417-1-1.
Features
Versatile supports SONET/SDH 622.08/ 155.52 Mbits/s interface solutions DS3/E3, DS2/E2, DS1/J1/E1 applications. Terminates DS1/J1 framed signals. popular framing formats supported. Terminates DS3/E3, DS2, channelized unchannelized signals with grooming channelized DS3/E3/DS2/E2. Mates with three other UltramapperLites provide 112/84 DS1/J1/E1 terminations. Terminated DS3/E3, DS2/E2, DS1/J1/E1 signals flexibly mapped into SONET/SDH interface using allowed MUXing structures. Supports 1:1, (DS2/DS1/E1) protection schemes with dedicated interfaces. I/O, CORE, power temperature range allows uncontrolled convection cooled environments. Built-in clock data recovery circuits with optional input forward clocking STS-3 input. Full SONET/SDH compliant alarm reporting. Supports full processing line/section/path overhead with inhibitable automatic generation AIS, RDI, REI, times filtering critical overhead. Allows extraction/insertion DCC-L, DCC-S, Mbits/s using specified overhead bytes data communications channel. data signal optionally framed routed to/from DS1/E1 I/Os. Provides full high-speed pointer processing synchronization frame/2 superframe system timing. Loopbacks, manual error insertion, internal pattern generator/monitor, internal cross connects simplify debugging diagnostics. Standard 700-pin ball grid array (PBGA). Complies with appropriate Telcordia®, ITU, ANSI ETSI, Japanese standards noted.
Receives data STS-12/STM-4 (622.08 Mbits/s) STS-3/STM-1 (155.52 MHz) data rate. 155.52 MHz/622.08 input reference clock on-chip PLL. On-chip clock synthesis, that requires only external resistor, generates phases, provides resolution approximately bypass mode functional test. Meets type jitter tolerance specification ITU-T recommendation G.783. output clock drift absence data transitions once lock acquired.
TMUX Features (x1)
STS-12 Pointer Processor (STSPP) Features (x1)
Multiplexes/demultiplexes twelve STS-1 signals four STS-3c signals to/from SONET STS-12 signal. Multiplexes three STS-1 signals into SONET STS-3 signal. Multiplexes/demultiplexes four STM-1 (AU-4 3xAU-3) signals to/from STM-4 signal. Multiplexes/demultiplexes three VC-3 signals to/from STM-1 (3xAU-3) signal.
SONET compliant. Configurable STS-3/STM-1 STS-12/STM-4 mode. Supports arbitrary STS-1 STS-3c tributaries, equivalents passthrough from receiver transmitter. Supports STS-n add/drop capability. Complies with GR-253-CORE, T1.105, G.707, G.783, G.806, G.821, ETSI 417-1-1.
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Features (continued)
Cross Connect (STSXC) Features (x1)
Provides STS-1 selectable scrambler/descrambler functions B1/B2/B3 generation/detection. Provides STS-1 pointer interpretation/processing. Complies with GR-253-CORE, T1.105, G.707, G.783, G.826, G.821, ETSI 417-1-1.
Internal clocks controls user transparent. STS-1 strictly nonblocking cross connect. following STSXC outputs sourced from subsequent list inputs without restriction STS-1/STM-0. Number STS-1s Number STS-1s Output Block TMUX SPEMPR STS1LT STS1LT Mate (from TMUX only) Input Block TMUX STS-12PP SPEMPR STS1LT Mate TMUX only)
Synchronous Payload Envelope Mapper (SPEMPR) Features (x6)
mapper accepts/delivers TUG-2 data from/to mapper. TUG-2 data mapped/demapped either to/from AU-3/STS-1 signal North American digital systems to/from TUG-3 signal ITUbased systems. Only available SPEMPR 0-2. mapper accepts/delivers channelized data from/to MUX/deMUX. data mapped/ demapped either to/from AU-3/STS-1 signal North American digital systems to/from TUG-3 signal ITU-based systems. Only available SPEMPR 3-5. mapper accepts/delivers channelized unchannelized signals 44.736 Mbits/s rate from external I/O. signals mapped/demapped same signal described above. mapper accepts/delivers channelized data from/to MUX/deMUX. data mapped/ demapped either to/from AU-3/STS-1 signal North American digital systems to/from TUG-3 signal ITU-based systems. Only available SPEMPR 3-5. mapper accepts/delivers channelized unchannelized signals 34.368 Mbits/s rate from external I/O. These signals mapped/demapped same signal described above. mapper DS3/E3 loopback circuit placed demap remap DS3/E3 signal. particularly useful cases where DS3/E3 signal, mapped AU-3/STS-1 signal, requires remapping TUG-3 signal vice versa. mapper supports path overhead access channel (POAC). Seven path overhead bytes (J1, inserted/dropped through this channel. This channel works master, meaning provides clock both transmit receive directions data inserted transmit side dropped receive side. Path overhead byte (BIP error) generation/detection programmable BIP-8 error rate insertion. Signal fail signal degrade indicators available report error rates above standard provisionable thresholds.
Mate Clock Data Recovery (MCDR) Features (x1)
Provides glueless capability connect UltramapperLites master/slave configuration. Loss-of-clock detection from three external 155.52 clock inputs. Loss-of-frame (LOF), out-of-frame (OOF), error detection three 155.52 Mbits/s interfaces. Also monitoring generation available. Manual error insertion debugging. Provisionable delay between output data frame sync accommodate variable length paths slave UltramapperLites.
STS-1 Line Terminating (STS1LT) Features (x3)
Supports standard mappings sub-STS-1 payloads (VT-mapped: DS1, signals). Supports standard mappings STS-1 payloads (DS3/E3). Detects STS-1 loss-of-signal (LOS), out-of-frame (OOF), loss-of-frame (LOF), AIS-P, conditions.
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Synchronizes VT/TU system-shelf-timing reference setting transmit VT/TU pointers fixed values asynchronous mapping dynamically changing transmit VT/TU pointers byte synchronous mapping. Supports asynchronous, byte synchronous, synchronous mappings. Supports automatic generation microprocessor overwrite RDI-V enhanced RDI-V, RFI-V. Supports applications with tributary loopback tributary pointer processing. Provides low-order path overhead access channel. Supports TIM-V generation termination 28/21 VT/TU signals. Supports BIP-V insertion detection. Supports fast generation downstream devices. Supports second error counter BIP-V REI-V. Allows grooming VTs/TUs granularity TUG-2s within STS-3/STM-1 signal. Configurable VT/TU slot selection DS1, insertion drop. Automatic receive monitor functions include VT/TU RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V. Supports UltramapperLite modes operation. Complies with O.150, T1.105, T1.107, T1.231, T1.403, G.703, G.704, G.707, G.783, GR-253-CORE, GR-499, JT-G707, 417-1-1.
Features (continued)
Capable detecting/inserting AIS, RDI, REI. Monitoring provided TUG-3 path overhead bytes. tandem connection support provided. TUG-3 pointer processor supports add/drop multiplexing. Provides control signals optional external DS3/E3 clock smoothing circuit. Complies with GR-253-CORE, T1.105, ITU-T G.707, ITU-T G.831, G.783, 417-1-1.
Test Pattern Generator/Monitor (TPG/TPM) Features (x1)
Configurable test pattern generator: DS1, DS3, STS-1 formats. Provisionable test pattern data from following options: quasirandom signal source (QRSS), pseudorandom stream length (PRBS15), PRBS20, PRBS23, alternating (ALT_01), ALL_ONES, user pattern bits, repeating). test patterns transmitted either unframed payload framed signal defined ITU-T. Under register control, single framing (DS1/E1 only) errors injected into test pattern. sink receiving channel replaced test pattern monitor, which detect count errors misconfigurations, and/or detect idle conditions AIS. Datalink (DS1-ESF multiframe fields read/writable. Supports UltramapperLite modes operation. Complies with T1.107, T1.231, T1.403, G.703, G.704, O.150.
2.10 M13/E13 Features (x3)
2.10.1 Features
Virtual Tributary Mapper (VTMPR) Features (x3)
Configurable multiplexer/demultiplexer signals, signals, seven signals to/from signal. Operates either C-bit parity mode. Provisionable time-slot selection DS1, insertion drop. Full alarm monitoring generation (LOS, BPV, EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit C-bit parity errors, FEBE).
Maps DS1/J1/E1 into VT/TU structures: into VT1.5/TU-11/TU-12. into VT1.5/TU-11/TU-12. into VT2/TU-12. Maps VC-11/VC-12 into VTG/TUG-2 structures: VC-11 into VT1.5/TU-11/TU-12/VTG/TUG-2. VC-12 into VT2/TU-12/VTG/TUG-2.
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Features (continued)
forced loopback DS2, DS1, forced loopback loopback request generation. Complies with T1.102, T1.107, T1.231, T1.403, T1.404, 499, G.747, G.775.
signaling modes: transparent; register system access entire TS16 multiframe structure G.732. Signaling debounce change state interrupt. V5.2 processing. Alarm reporting performance monitoring AT&T ANSI, ITU-T, ETSI standards. Facility data link features: HDLC transparent access either frame formats. Register/stack access SLC-96 transmit receive data. Extended superframe (ESF): automatic transmission performance report messages (PRM). Automatic transmission ANSI T1.403 performance report messages. Automatic detection transmission ANSI T1.403 bit-oriented codes. Register/stack access CEPT bits transmit receive data. HDLC features: HDLC transparent mode. Programmable logical channel assignment: timeslot, ISDN channel, also inserts/extracts C-channels V5.1, V5.2 interfaces. logical channels both transmit receive direction (any framing format). Maximum channel data rate kbits/s. Minimum channel data rate kbits/s (DS1/FDL bit). 128-byte FIFO channel both transmit receive directions. loopback supported.
2.10.2 Features
Configurable multiplexer/demultiplexer signals, four signals, to/from signal. Independently configurable four multiplexer/demultiplexers signals to/from four signals. Provisionable time-slot selection insertion drop multirate cross connect functional block. multiplexers capable generating alarm indication signal (AIS) remote alarm indicator (RAI) signals. Configurable HDB3 encoder/decoder output/input. transmit path monitors that detect loss-ofclock (LOC) AIS. receive path monitor that detects LOC, AIS, RAI. receive monitor that detects loss-of-signal (LOS), LOC, bipolar violation (BPV), AIS, RAI. loopback modes. Complies with G.703, G.742, G.751, G.775.
2.11 DS1/J1/E1 Framing Features (FRM) (3x28/21)
28/21 DS1/J1/E1 channels. Line coding: B8ZS, HDB3, ZCS, AMI, (JJ20-11). framing modes: ESF, ®-96, DDS, only). framing modes: G.704 basic CRC-4 multiframe consistent with G.706. framing modes: JESF (Japan). Supports transparent transmission format. signaling modes: transparent; register system access 2-state, 4-state, 16-state; 2-state, 4-state, 16-state; SLC-96 2-state, 4-state, 16-state; J-ESF handling groups maintenance signaling; 2-state, 4-state, 16state.
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
number loopbacks supported 84/63 channels DS1/E1 channels from mapper, M13/E13, framer functional blocks. One-to-one loopback supported DS1/E1 channels. One-to-one loopback supported DS3/E3 channels from M13/E13, mapper functional blocks. Loopbacks configured sectionalize circuit identifying faults misconfiguration during service maintenance. Fast alarm channels supported mapper, E13, framer interconnects alarm indication signal (AIS blue alarm) mapper only remote alarm indicator (RAI yellow alarm). This feature reduces propagation delay alarms eliminating multiple integration alarm conditions. TOAC outputs available DS1/E1 framed format destination. DS1/E1 channel used TOAC input. TOAC POAC also available dedicated pins device.
Features (continued)
2.12 Multirate Cross Connect (MRXC) Features (x1)
Configurable cross point interconnect 84/63 DS1/E1 signals to/from FRM, VTMPR, M13/E13, TPG/TPM, DS1/E1 DJA, external pins. Also supports 21/12 DS2/E2 to/from external pins from/to M13/E13 functional block. Connects three DS3/E3 signals from external pins M13/E13 MUX. Connects DS3/E3 signals between external pins DS3/E3 DJA, SPEMPR, three STS-1 signals from external pins STS1LT. Also connects three external NSMI interfaces SPEMPR, M13/E13, functional blocks. Three NSMI ports shared with three STS-1 line terminations. Provides grooming capability receive plus transmit) DS1/E1 connections between FRM, VTMPR, M13/E13, DS1/E1 DJA, bidirectional sets pins. This allows cross connect grooming block signal port other signal port different block output pin, same block case groomed loopback. Multicast operation (one many) supported sources destinations. DS2, DS3, signals interconnect. Multirate cross connect allows signals to/from modules from/to framer, mapper, TPG/TPM, external pins. There signals to/from from/to external pins.
2.13 DS1/E1 Digital Jitter Attenuation (DJA) Features (3x28/21)
bandwidth, damping factor, sampling rates programmable. Configurable meet jitter MTIE requirements. Supports each DS1/E1. (Note that cascaded.) 28/21 DJAs block.
2.14 DS3/E3 Digital Jitter Attenuation (DJA) Features (x1)
bandwidth, damping factor, sampling rates programmable. functional block accepts/delivers DS3/E3 clock data from/to multirate cross connect functional block. Supports each DS3/E3. (Note that cascaded.) DJAs block.
There three signals from/to functional block to/from external pins mapper. Jitter attenuation also inserted in-line DS3/ DS1/E1 channel. (Note that cascading jitter attenuators allowed.) Standard network loopback straight-away facility testing supported DS1/E1 DS3/E3. test-pattern generator capable injecting idle standards-based, pseudorandom sequence test patterns, (blue) alarm replace source transmitter. test-pattern monitor that detect/count errors pseudorandom test sequence, loss frame synchronization, replace sink receiver.
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Features (continued)
2.15 Microprocessor Unit (MPU) Features (x1)
Overview
SONET/SDH UltramapperLite device integrates SONET/SDH section, line, path, tributary termination functions with M13/E13 multiplex functions primary rate framing function. interfaces OC-3/STM-1 optical signal OC-12/STM-4 allow modular growth terminal add/drop applications. SONET/SDH UltramapperLite device provides versatile interface STS-12/STM-4, STS-3/STM-1, STS-1 termination applications point-to-point scenarios ring applications. Used tributary shelf applications, this chip enables (for total 112), (for total interfaces, provide various possible mappings into SONET/SDH. Mapping flexibility allows software upgrades from M13/ mapped connections VT/TU mapped connections. This device also used DS3/E3/DS2/E2 applications. single UltramapperLite terminate DS3s from STS-12/STM-4, STS-3/STM-1s. single UltramapperLite also function STS-12/STS-3/STM-4/ STM-1 add/drop multiplexer terminating three STS-1 channels AU-4 channel and, using internal pointer processors, forward nonterminated channel. connecting three other mate devices through serial STS-3/STM-1 mate interconnects, termination full STS-12/STM-4 payload possible.
21-bit address/16-bit data microprocessor interface (little endian). Synchronous MHz)/asynchronous microprocessor interface modes. Microprocessor data parity monitoring. Summary level priority interrupts from major functional blocks (maskable). Separate device interrupt outputs automatic protection switch UltramapperLite global interrupt. Global configuration network performance monitoring counters operation. Global software resets. Global enabling powerdown major functional blocks. Registers provisionable clear read/clear write. Compatible with most industry-standard processors.
2.16 JTAG
IEEE 1149.1 JTAG boundary scan.
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Application Diagrams
This section shows several typical UltramapperLite applications. Figure through Figure depict system-level diagrams.
STS-12/STM-4 Four Device Application
Network connections applications, where only network protection desired, handled UltramapperLites using protection link. STS1LT ports used transfer STS-3's worth terminated bandwidth between devices Useful applications that require only network protection, equipment protection. additional UltramapperLites connected master (shown) usual manner mate interfaces (RLS/TLSDATA mate interconnect pins master to/from RHSD/THSD pins slaves). protection switch accomplished with single write master device. master device provisioned source sync signal (master mode) three slaves provisioned receive sync (slave mode).
ULTRAMAPPERLITE HIGH-SPEED INTERFACE ULTRAMAPPERLITE HIGH-SPEED INTERFACE MATE OC-12 TRANSCEIVER STS-12 STM-4e ULTRAMAPPERLITE DS1/E1 DS3/E3 DS1/E1 DS3/E3 DS1/E1 DS3/E3
OC-12/STM-4o WORKING
HIGH-SPEED INTERFACE STS-1 (MASTER STS-12 MODE)
PROTECTION LINKS
STS-1
STS-1 OC-12 TRANSCEIVER PROTECTION STS-12 STM-4e
ULTRAMAPPERLITE DS1/E1 DS3/E3
HIGH-SPEED INTERFACE
TSWC01622
Figure STS-12/STM-4 Four Device Configuration
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Application Diagrams (continued)
STS-3/STM-1 to/from DS3/E3 Application
Three DS3s/E3s input from LIUs MUXed STS-3/STM-1 level. Similarly, STS-3/STM-1 input high-speed interface device deMUXed three DS3s/E3s. STS-3/STM-1 will received/transmitted device RHSD THSD pins. DS3s/E3s will received/transmitted device DS3DATAIN/OUT pins.
OC-3/STM-1o STS-3/STM-1e ULTRAMAPPERLITE HIGH-SPEED INTERFACE (MASTER) TSWC01622 DS3/E3 DS3/E3
OC-3 TRANSCEIVER
Figure STS-3/STM-1 to/from DS3s/E3s Configuration
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Application Diagrams (continued)
UPSR HO/LO Application with
TSOT/TADM performs high-order (HO) path UPSR/BLSR, grooms east/west VT-mapped STS-1s, allows dual ring interworking. Each TSOT/TADM provide twelve Mbits/s connections UltramapperLites. STS-1s from east from west groomed single master UltramapperLite. Each UltramapperLite device perform low-order (LO) path UPSR protected VT1.5s. VT1.5s add/ dropped DS1. UltramapperLites configured add/drop configurations interfaces. applications similar SONET application shown Figure
MBITS/S LINKS EAST OC-12 TRANSCEIVERS ULTRAMAPPERLITE ULTRAMAPPERLITE OC-12 TRANSCEIVERS ULTRAMAPPERLITE TSOT042G5 TADM042G5 ADDITIONAL I/Os USED DUAL RING INTERWORKING ULTRAMAPPERLITE ULTRAMAPPERLITE ULTRAMAPPERLITE ULTRAMAPPERLITE ULTRAMAPPERLITE WITH
RING WEST
TSWC01622
Figure UPSR HO/LO with Configuration
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Application Diagrams (continued)
STS-12/STM-4 Transport (Mixed DS3/E3 DS1/E1) Application
Figure shows 56/42 DS1/J1/E1s plus DS3/E3s mapped multiplexed STS-12/STM-4. following points describe this scenario:
devices interconnected provide full STS-12/STM-4 payload transport terminations. This application shows simultaneous physical terminations mixed low-speed DS1/E1 traffic DS3/E3 traffic. STS-12/STM-4 will received/transmitted RHSD THSD pins master device. DS3s/E3s will received/transmitted devices DS3DATAIN/OUT pins. DS1s/E1s will received/transmitted devices LINERX/TXDATA pins. STS-3/STM-1 routed from master slave device mate interconnect (RLS/TLSDATA mate interconnect pins master to/from RHSD/THSD pins slave). Three STS-1s/STM-0s routed from master slave device NSMI/STS-1 shared (NSMIRX/TXDATA pins). This application maps DS1s transport rate interfaces. remainder STS-12/STM-4 payload terminated DS3/E3.
OC-12/STM-4o STS-12/STM-4e HIGH-SPEED INTERFACE MATE INTERCONNECT (MASTER STS-12 MODE) NSMI/STS-1 STS-3/STM-1 STS-1 NSMI/STS-1 HIGH-SPEED INTERFACE ULTRAMAPPERLITE DS3/E3 (SLAVE STS-3 MODE) TSWC01622 DS3/E3 56/42 DS1/E1 ULTRAMAPPERLITE DS1/E1
OC-12 TRANSCEIVER
Figure DS1s/42 Plus DS3s/E3s Mapped Multiplexed to/from STS-12/STM-4
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Application Diagrams (continued)
Transport Unprotected Add/Drop Ring Application
Figure shows three EC1s, plus three DS3/E3s, plus 28/21 DS1/E1s add/dropped from OC-12 ring. following points describe this scenario:
Single device unprotected ring add/drop configuration. (Neither UPSR BLSR implemented this configuration.) High-speed STS-12/STM-4 interface OC-12 receiver OC-12 transmitter ring. STS-12/STM-4 will received/transmitted RHSD THSD pins master device. DS1s/ terminated rate interfaces (out 84/63). DS1s/E1s will received/transmitted device LINERX/TXDATA pins. Additionally STS-1/STM-0 payloads terminated three DS3s/E3s plus three EC-1s. DS3DATAIN/ NSMIRX/TXDATA pins would used. Unterminated traffic mapped through from west east. Low-order (VT) path overhead (LOPOH), path overhead (POAC), transport path overhead (TOAC) access ring maintenance functions. grooming well drop continue capabilities available. OC-3 unprotected add/drop ring configuration also possible.
OC-12/STM-4o WEST STS-12/STM-4e OC-12 RECEIVER HIGH-SPEED INTERFACE (RECEIVE)
DS1/E1 28/21 84/63 DS1/E1
DS3/E3 ULTRAMAPPERLITE DS3/E3/EC1
OC-12 TRANSMITTER
STS-12/STM-4e HIGH-SPEED INTERFACE (TRANSMIT) EC-1 DS3/E3/EC1
OC-12/STM-4o EAST
LOPOH TOAC
POAC
TSWC01622
Figure Three EC-1s, Plus Three DS3s/E3s, Plus DS1s/21 Add/Dropped from OC-12 Ring
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Application Diagrams (continued)
STS-12/STM-4 to/from DS3/E3 TransMUX Application
Figure shows twelve DS3s transmultiplexed to/from twelve STS-1s with VT-mapped DS1s four UltramapperLites. following points describe this scenario:
This application will transmultiplex between twelve M13/E13 DS3s/E3s STS-12/STM-4 with full VT-mapped DS1s/E1s. STS-12/STM-4 will received/transmitted master device RHSD THSD pins. DS3s/E3s will received/transmitted devices DS3DATA(IN/OUT) pins. Device configured master mode (interface STS-12/STM-4), while devices configured slave mode (interface STS-3/STM-1). mate interconnect (RLSDATA TLSDATA pins master) utilizes STS-3 connection between master each slave device (STS-3/STM-1 to/from slaves RHSD THSD pins). Each four devices converts three M13/E13 DS3s/E3s into three STS-1s/AU-3s with VT-mapped DS1s/E1s. Similarly, each four devices converts three STS-1s/AU-3s with VT-mapped DS1s/E1s into three M13/E13 DS3s/ E3s.
OC-12/STM-4o STS-12/STM-4e MATE INTERCONNECT ULTRAMAPPERLITE HIGH-SPEED INTERFACE (MASTER) DS3/E3 DS3/E3
OC-12 TRANSCEIVER
ULTRAMAPPERLITE HIGH-SPEED INTERFACE STS-3/STM-1 (SLAVE) ULTRAMAPPERLITE DS3/E3 HIGH-SPEED INTERFACE (SLAVE) ULTRAMAPPERLITE HIGH-SPEED INTERFACE TSWC01622 (SLAVE) DS3/E3 DS3/E3 DS3/E3 DS3/E3 DS3/E3
Figure DS3s/E3s Transmultiplexed to/from VT-Mapped STS-12/STM-4
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Application Diagrams (continued)
Portless TransMUX Application
Figure shows translate M13/E13-mapped STS-1s VT-1.5/TU-11/TU-12-mapped STS-1s conversely translate VT-1.5/TU-11/TU-12-mapped STS-1s M13/E13-mapped STS-1s. following points describe this scenario:
STS-12/STM-4 consists VT/TU-mapped STS-1s/STM-0s, M13/E3 mapped STS-1s/STM-0s. UltramapperLites required STS-1s/STM-0s (DS3/E3-mapped) to/from STS-1s/STM-0s (VT/TUmapped). STS-12/STM-4 will received/transmitted RHSD THSD pins master device. slave device receives sends total STS-1s/STM-0s; three STS-3 high-speed interface (RLSDATA TLSDATA mate interconnect pins master to/from RHSD THSD pins slave), three STS-1 system interface (NSMIRX/TXDATA DS3DATAIN/OUT pins devices). Each device translates three VT/TU-mapped signals three M13/E13-mapped signals three M13/E13 mapped signals three VT/TU-mapped signals.
M13/E13 MAPPED STS-1/STM-0 OC-12/STM-4o VT-1.5/TU-11/TU-12 MAPPED STS-1/STM-0 STS-3/STM-1e OC-12 TRANSCEIVER
ULTRAMAPPERLITE HIGH-SPEED INTERFACE MATE INTERCONNECT SYSTEM INTERFACE STS-1/STM-0 ULTRAMAPPERLITE SYSTEM INTERFACE HIGH-SPEED INTERFACE (MASTER STS-12 MODE)
TSWC01622
(SLAVE STS-3 MODE)
Figure Translate M13/E13-Mapped STS-1s/STM-0s VT-1.5/TU-11/TU-12-Mapped STS-1s/STM-0s Conversely Translate VT-1.5/TU-11/TU-12-Mapped STS-1s/STM-0s M13/E13-Mapped STS-1s/STM-0s
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TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Application Diagrams (continued)
STS-12/STM-4 to/from DS3/E3 Application
Figure shows UltramapperLites terminating STS-12/STM-4. following points describe this scenario:
Twelve DS3s/E3s input from LIUs MUXed STS-12/STM-4 level. Similarly, STS-12/STM-4 input high-speed interface master device deMUXed twelve DS3s/E3s. STS-12/STM-4 will received/transmitted RHSD THSD pins master device. DS3s/E3s will received/transmitted devices DS3DATA(IN/OUT) pins. Three DS3s/E3s routed from master slave device mate interconnect (RLS/TLSDATA mate interconnect pins master to/from RHSD/THSD pins slave). Three DS3s/E3s routed from master slave device NSMI/STS-1 shared (NSMIRX/TXDATA pins).
OC-12/STM-4o STS-12/STM-4e HIGH-SPEED INTERFACE MATE INTERCONNECT (MASTER STS-12 MODE) NSMI/STS-1 STS-3/STM-1 STS-1/STM-0 ULTRAMAPPERLITE NSMI/STS-1 HIGH-SPEED INTERFACE DS3/E3 (SLAVE STS-3 MODE) TSWC01622 DS3/E3 DS3/E3 ULTRAMAPPERLITE DS3/E3
OC-12 TRANSCEIVER
Figure Device Termination STS-12/STM-4
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Application Diagrams (continued)
STM-1 Protection Application
STM-1 applications that require cost effective solution employ SupermapperLite protection interface. protection scheme similar other applications uses protection link between devices. assumed that STM-1 application requires capabilities, which available UltramapperLite device, otherwise Supermapper solution possible.
ULTRAMAPPERLITE STM-1o WORKING (MASTER STM-1 MODE) PROTECTION LINKS OC-3 TRANSCEIVER STM-1e HIGH-SPEED INTERFACE
STM-1o PROTECTION
OC-3 TRANSCEIVER
STM-1e
SUPERMAPPERLITE
TSWC01622
Figure STM-1 Protection Configuration
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
entire value K2[2:0] inserted microprocessor control. Automatic insertion supported with individual inhibits each contributor. protection switch selects RDI-L value insertion from protection board rather than from working side. BIP-8 values calculated inserted. Both values inverted. 5.1.2 Receive Path Section/Line Overhead Receive path section/line overhead follows:
Block Description
TMUX/Clock Data Recovery (CDR) Blocks
TMUX blocks (one device) provide high-speed interface SONET/SDH line terminate section line signals. Several features incorporated these blocks allow variety system applications. First, redundant interface provided with appropriate selectors bridges allow easy implementation 1:1, ring protection schemes. Second, separate interface provided access selected overhead bytes. SONET applications, section DCC-S added/dropped kbits/s, while applications same adding/dropping DCC-L kbits/s. Alternately, bytes entire overhead added/dropped. third feature these blocks that they operate both 622.08 Mbits/s 155.52 Mbits/s, where 155.52 Mbits/s mode clock forwarded from external device. this mode, both receive transmit directions device operate asynchronously. Mbits/s mode, provided ease retiming data signal. fourth final function these blocks terminate/generate section, line, path overhead (only SONET/SDH STS-12/3 STM-4/1 signals). Automatic generation AIS/RDI/REI possible since protection path available device. Additionally, times filtering provided critical bytes such K1/K2. variations overhead processing between SONET also accommodated. summary overhead processing follows includes pointer interpretation function necessary detection. 5.1.1 Transmit Path Section/Line Overhead Transmit path section/line overhead follows:
Frame alignment (STS-12/STM-4 STS-3) BIP-8 check monitoring Descrambling monitoring BIP-8 check monitoring AIS-L RDI-L detection REI-L detection synchronization status monitoring
Framer states other state changes reported. These cause interrupt masked. parity check supports both block modes. counters count second's worth errors. These stay their maximum value case overflow rollover should read (and cleared) least once second. monitor supports nonframed, SONET-framed, SDH-framed 16-byte sequences, well single byte monitoring modes. monitoring performed K1[7:0] K2[7:3]. value stored, changes reported. Bits [2:0] byte monitored independently. alarm indication signal (AIS-L/MS-AIS) remote defect indication (RDI-L/MS-RDI) monitored separately, changes reported. This information also sent protection device applications. monitor operates either block mode allows access remote error indication (REI-L/MS-REI) errored count. byte monitored either entire 8-bit word 4-bit nibble (bits 7:4).
Synchronizing status byte (S1) insertion M0/M1 REI-L insertion; automatic insertion inhibited insertion, AIS-L insertion calculation insertion byte insertion generation error insertion Scrambler insert control error insertion
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TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Block Description (continued)
5.1.3 Pointer Interpreter TMUX pointer interpreter conforms 417-1-1: January 1996-Annex pointer interpreter evaluates current pointer state normal state, path state, (loss pointer) conditions, well pointer increments decrements. current pointer state changes pointer condition reported control system. number consecutive frames invalid pointer invalid concatenation indication fixed nine. 5.1.4 Path Termination Function STS-3/STM-1 mode, path termination performed either three STS-1s VC-4. STS-12/STM-4 mode, path termination performed either twelve STS-1s/four STS-3cs, four VC-4 POH. receive side, includes following:
STS-12/STM-4 Pointer Processor (STSPP) Block
pointer processor (one device) used move SONET/SDH payload from line clock domain system clock domain. UltramapperLite's STS-12 pointer processor SONET compliant offers configurable STS-3/STM-1 STS-12/STM-4 mode. supports arbitrary STS-1/STS-3c tributaries equivalents, complies with GR-253-CORE, T1.105, G.707, G.783, G.826, G.821, ETSI 417-1-1.
STS-1 Line Terminating (STS1LT) Block
STS-1 line terminating block (three device) allows termination STS-1 line signal routed from multirate cross connect. provides access section/line path overhead similarly TMUX. also source cross connect transport high-speed line interface.
monitoring BIP-8 checking signal label monitoring REI-P RDI-P detection multiframe monitoring automatic protection switch monitoring tandem connection monitoring Signal degrade signal fail detection Path overhead access channel (RPOAC) drop AIS-P/HO-AIS insertion Automatic generation (with individual inhibit)
Cross Connect (STSXC) Block
high-order cross connect connects SONET/SDH interfaces portion device. will permit connections that support variety applications. data paths, clocks, syncs internally configured appropriate different signal rates interconnects. significant portion STSXC block mate interconnect described Section 5.5.
Mate Interconnect Clock Data Recovery (MCDR) Block
UltramapperLite configured terminate STS-12/STM-4 signal connecting four devices together mate interconnect. Each interconnect operates Mbits/s connected between single UltramapperLite configured master three UltramapperLites with high-speed TMUX input configured slaves. mate interconnect uses SONET/SDH framing overhead there performance monitoring link between devices. addition, frame position slave's data signal adjustable allow variations application board delays.
monitor found TMUX block) provides following four modes operation byte byte):
SONET mode mode User mode Single byte mode
Note: additional functionality, please refer STS1-LT SPEMPR sections Register Description document. monitored either block mode. Provisionable N-times detection counters implemented bytes. byte byte monitored entire 8-bit word 4-bit nibbles.
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TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
applications supported tributary loopback, tributary pointer processing, low-order path overhead access channel. VT/TU mapper supports automatic generation microprocessor overwrite 1-bit RDI-V, enhanced RDI-V, 1-bit RFI-V, automatic downstream generation, five trace identifier modes. VT/TU mapper complies with GR-253-CORE, G.707, T1.105, G.704, G.783, JT-G707, GR-499, 417-1-1. 5.7.1 Receive Direction receive direction, mapper terminates data stream receives from mapper. demultiplexes AU-3/TUG-3 into VTs/TUs checks multiframe alignment. pointer interpreter VTs/TUs detects LOP, AIS, NDF, NORM, INC, each channel. low-order path termination includes byte termination, path trace, Z6/N2 tandem connection, Z7/K4 enhanced RDI-V low-order monitoring, payload termination asynchronous, byte- bit-synchronous signals. byte termination performs BIP-2 check (bit block mode), REI-V count, RFI-V, RDI-V detection, signal label monitoring, automatic AIS-V insertion (which inhibited). monitor supports following modes:
Block Description (continued)
SPE/AU-3 Mapper (SPEMPR) Block
mapper functional block (six device) operates either AU-3/STS-1 mapper TUG-3 mapper. either mode, maps/demaps data from/to either mapper, M13/E13 MUX/deMUX, DS3/E3 clear channel, DS3/E3 loopback channel. mapper supports numerous automatic monitoring functions provides interrupts control system, operated polled mode. mapping mode, mapper functional block accepts/delivers structured data from/to functional block clear channel signal 44.736 Mbits/s rate maps/demaps asynchronously to/from STS-1 TU-3. mapper generates fixed pointer value 522. receive side, pointer interpretation performed, detecting LOP, AIS, NDF, NORM, INC, DEC. loopback mode allows demapping remapping signal. particularly useful cases where signal mapped AU-3/STS-1 needs remapped TU-3 signal vice versa. B3ZS encoding/decoding included. mapping mode similar functionality that mapping mode just described. This functional block also connects path overhead access channel (POAC) insert/drop path overhead bytes into/from STS-1 VC-3. mapper functional block complies with GR-253CORE, T1.105, ITU-T G.707, ITU-T G.831, G.783, 417-1-1.
Cyclic check SONET framing mode framing mode Single byte check
VT/TU Mapper (VTMPR) Block
VT/TU mapper (three device) maps valid combination signals into stream rate 51.84 Mbits/s (STS-1 AU-3). mapping methods (VT1.5, VT2, group ANSI nomenclature; TU-11, TU-12, TUG-2 nomenclature) analogous. VT/VC mapper supports following mappings:
byte-synchronous mode, receive demapper generates frame synchronization signal indicate frame time slot Additionally, provides framer access received signaling bits. Output mapper DS1/J1/E1 signal with gapped clock. overwritten with automatically upon microprocessor request. 5.7.2 Transmit Direction transmit direction, mapper gets clock, data, frame synchronization signal from multirate cross connect. input retimed checked digital loss clock (LOC), condition, zeros density. byte-synchronous mode, input signal additionally checked loss-of-frame (LOF).
asynchronous, byte-, bit-synchronous signals mapped into seven groups TUG-2s. asynchronous, byte-, bit-synchronous signals mapped into seven groups TUG-2s. asynchronous, byte-, bit-synchronous signals mapped into seven groups TUG-2s. Maps into VT1.5/TU-11/TU-12, into VT1.5/TU-11/ TU-12, into VT2/TU-12.
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TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Block Description (continued)
transmit elastic store synchronizes incoming DS1/J1/E1 signals local STS-1 clock. asynchronous bit-synchronous mode, works bit-oriented (64-bit) FIFO, byte-synchronous mode, bytewide (8-byte) buffer using byte marker (8-bit). Overflow underflow conditions monitored reported. asynchronous bit-synchronous mode, fixed pointer (VT1.5/TU-11) (VT2/TU-12) generated payload mapped into container using positive/null/negative stuffing mechanism S-bits). bit-synchronous mode, stuffing mechanism disabled. byte-synchronous mode, dynamic pointer value generated using marker, implementing NORM, NDF, INC, pointers. generation comprises byte with BIP-2 generation, AIS-V, UNEQ-V insertion, automatic REI-V, RFI-V, RDI-V, enhanced RDI-V generation (Telcordia, ITU-T), path trace insertion microprocessor, Z6/N2 byte insertion, Z7/K4 byte insertion microprocessor low-order path overhead (LOPOH) access channel. data stream synchronized received internal synchronization pulse multiplexed form STS-1/AU-3 signal, which then output mapper. When operating byte-synchronous mode, phase signaling bits from framer stored inserted into mapped frame.
deMUXed DS2s. supports numerous automatic monitoring functions. provide interrupt control system, operate polled mode. complies with T1.102, T1.107, T1.231, T1.403, T1.404, GR-499, G.747, G.775. 5.8.1.1 Receive Direction receive monitored loss clock loss signal (LOS) according T1.231. B3ZS decoder accepts either unipolar clock data, unipolar clock positive negative data. also checks bipolar coding violations. transmit looped back into receive side after B3ZS decoding. demultiplexer checks valid framing finding frame alignment pattern (F-bits) then locating multiframe alignment signal (M-bits). During each frame, data stream checked presence (1010) idle (1100) pattern. Within demultiplexer, there four performance monitoring counters M-bit, P-bit, E-bit parity, FEBE errors. Each demultiplexer contains performance monitoring counters. 5.8.1.2 Transmit Direction incoming DS1/E1 clocks first checked activity loss-of-clock (LOC). data signals retimed checked activity. DS1/E1 loopback selectors allow individual DS1/E1 signals within received looped back toward DS2/DS3 input. This loopback performed automatically, user force loopback. four three signals each into single-bit, 16-word-deep FIFOs synchronize signals frame generation clock. fill level each FIFO determines need stuffing DS1/E1 input. handle DS1/E1 signals with nominal frequency offsets ±130 five unit intervals peak jitter. DS2/DS3 transmit clock used derive clock source frame generation. multiplexer generates transmit frame, fills information bits frame with data from seven select blocks.
M13/E13 Multiplexer (M13/E13 MUX) Blocks
M13/E13 block (three blocks device) highly configurable multiplexer/demultiplexer which each block configured operation. features described below. 5.8.1 operate C-bit parity mode, mixed M13/M23 mode. C-bit parity mode, provides far-end alarm control (FEAC) code generator receiver, HDLC transmitter receiver, automatic far-end block error (FEBE) generator. Each internal MUX/deMUX MUX/deMUX configured operate independent MUXs/deMUXs. inputs groups four) input signals groups three) feed into individual MUXs, while take signals from outputs MUXs, direct inputs, loopback
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TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Independent signal paths remote alarm indication (RAI), alarm indication signal (AIS), byte-synchronous frame synchronizing signals channels between mapper M13/E13 framer supported. Receive pointer adjustment information routed jitter attenuator functional block each channel originating mapper. multirate cross connect independent interfaces sub-blocks MUX. Full split access external device pins provides capability add, drop, rearrange signals within M13. DS3/E3 signals, multirate cross connect supports configuration interconnects between following:
Block Description (continued)
transmit output either form unipolar clock data, unipolar clock positive negative data. data B3ZS-encoded looped back from receive input. 5.8.2 functional block that performs MUX/deMUX from/to E1s, four E2s, signal compliant with G.742 G.751. functional block highly configurable multiplexer/demultiplexer. operate E12, E13, modes. Each internal MUX/deMUX MUX/deMUX independently configurable. inputs receive path HDB3encoded dual-rail (bipolar) signals already decoded single-rail signals with without indication input. inputs expected decoded prior functional block. transmit direction output configured HDB3-encoded dual rail (bipolar) single rail. provides status two-level priority maskable interrupt outputs microprocessor. This block also independently configurable multiplexer/demultiplexer signals to/from four signals, provisionable time-slot selection insertion drop multirate cross connect functional block. E12/E23 multiplexers capable generating alarm indicator signal (AIS) remote alarm indicator (RAI) signals. transmit path monitors detect loss clock (LOC) AIS. receive path monitor detects loss clock (LOC), AIS, RAI. receive monitor detects loss signal (LOS), loss clock (LOC), bipolar violations (BPV), AIS, RAI. loopback modes also available.
M13/E13 SPEMPR External interconnection M13/E13 SPEMPR Insertion/monitoring unframed test patterns from test-pattern generator/monitor functional block
test-pattern generator/monitor functional block (TPG/ TPM) provides test signals monitors inputs signals to/from multirate cross connect. generate test signals DS1, DS2, DS3, STS-1 rates. There only test pattern generator monitor signal rate. overhead, MRXC provides access channel connection (TOAC POAC) SPEMPR TMUX functional blocks. MRXC also provides interface external pins. external pins configured work modes: transport mode network serial multiplexed interface (NSMI) mode. first mode used provide dedicated access device DS3/E3/DS2/E2/DS1/E1 signals, NSMI mode described below.
Multirate Cross Connect (MRXC) Block
multirate cross connect (MRXC) functional block (one device) crosspoint switch DS1/J1/E1/DS2/E2, VT/TU, DS3/E3, path overhead I/O. multirate cross connect routes signals to/from major functional blocks external pins necessary each application. MRXC multicast, route test patterns, idles, alarm conditions channel, provide system loopbacks. DS1/E1 applications, multirate cross connect interconnect individual DS1/E1 channels between framer, M13/E13 multiplexer, mapper, jitter attenuator, external I/O. external pins support application-dependent DS1/E1 interfaces (two/ nine dedicated protection channels additional DS1/E1 channels), interfaces, available system interfaces. Agere Systems Inc.
Network serial multiplexed (NSMI): 8-pin serial interface. Transmit receive clock data 51.84 44.736/34.368 M13/E13). Accommodates STS-1 SPE. modes operation: M13/E13-proprietary transport format with DS3/ framing. SPE-proprietary transport format mapped into STS-1/AU-3.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
Block Description (continued)
5.10 Digital Jitter Attenuator (DS1/E1 DJA) Block
DS1/E1 digital jitter attenuator (DS1/E1 DJA) block (three device), contains copies digital jitter attenuator total 84/63 DS1/E1 DJAs. These digital jitter attenuator functional blocks operate different modes: jitter attenuator. both modes, digital jitter attenuator provisioned always operate second-order PLL, switch first-order during pointer adjustments help meet MTIE requirements. period time first-order mode provisionable. bandwidth provisionable between damping factor these bandwidths varies between accommodate number different system constraints. DS1/E1 allows automatic pass-through from both VTMPR M13/E13 blocks.
5.12 Test Pattern Generator/Monitor (TPG/TPM) Block
test pattern generator/test pattern monitor functional block (TPG/TPM) consists configurable test pattern generators monitors local self-test, maintenance, troubleshooting operations. feeds more DS1/E1/DS2 test signals (via data, clock, (DS1/E1 only) signal paths) multirate cross connect, which redistribute broadcast these signals valid channel framer, external I/O, M13/E13 MUX, mapper functional blocks. also generate DS3, STS-1 test signals. channel arriving multirate cross connect routed test monitor. test monitor automatically detect/count errors pseudorandom test sequence, loss frame (DS1/E1 only), loss synchronization situation. provide interrupt control system, operated polled mode. Simultaneous testing DS1, DS2, DS3, STS-1 signals supported with channel each. Supported test patterns quasirandom signal (QRSS), pseudorandom sequence (PRBS23, PRBS20, PRBS15), alternating zeros/ones, all-ones pattern, 16-bit user-provisionable pattern. test patterns transmitted either unframed payload framed signal, defined ITU-T Recommendation O.150. DS3, STS-1 patterns unframed only. Under register control, single bit-errors injected into test pattern.
5.11 Digital Jitter Attenuator (DS3/E3 DJA) Block
UltramapperLite device contains single DS3/E3 digital jitter attenuator block containing DS3/E3 digital jitter attenuators. These digital jitter attenuators operate different modes: jitter attenuator. bandwidth sampling ratio over wide range accommodate number different system constraints. functional block accepts/delivers DS3/E3 clock data from/to multirate cross connect functional block. bandwidth, damping factor, sampling rates programmable. Output programmable data only, B3ZS-coded, HDB3-coded.
5.13 Low-Order Path Over Head
This block shown Figure cannot addressed MPU. shown virtual block highlight that LOPOH bytes from TMUX, SPEMPR, VTMPR provisioned appear LOPOH device pins. Provisioning accomplished setting registers device MPU.
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
5.14.3 Receive Performance Monitor receive performance monitor detects following alarms:
Block Description (continued)
5.14 Framer Block
Functionalities each subcomponent DS1/J1/E1 framer block (three device) described following sections. 5.14.1 Line Decoder/Encoder line decoder/encoder supports either single-rail dual-rail transmission. dual-rail mode, line codes supported follows:
Loss receive clock Loss-of-signal Loss-of-frame Alarm indication signal (AIS) Remote frame alarms Remote multiframe alarms
Alternate mark inversion (AMI) binary zero code suppresion (B8ZS) ITU-CEPT high-density bipolar order three (HDB3)
These alarms detected defined appropriate ANSI, AT&T, ITU, ETSI standards. Performance monitoring, specified AT&T, ANSI, ITU, provided through counters monitoring following:
single-rail mode, line interface unit (LIU) decodes/ encodes data. dual-rail mode, loss-of-signal monitored. case coded mark inversion (CMI) coding (Japanese standard JJ-20.11), decodes data, listing both coding rule violations (CRVs) line coding violations bipolar violations. mode, framer signle-rail mode.) 5.14.2 Receive Frame Aligner/Transmit Frame Formatter receive frame aligner transmit frame formatter support following frame formats:
Bipolar violations Frame errors errors Errored events Errored seconds Bursty errored seconds Severely errored seconds
In-band loopback activation deactivation codes transmitted line payload facility data link. In-band loopback activation deactivation codes payload facility data link detected. 5.14.4 Signaling Processor signaling processor supports following modes:
superframe superframe: framing only J-D4 superframe with Japanese remote alarm SLC-96 J-ESF standard with different CRC-6 algorithm) Nonalign (193 bits-clear channel) CEPT basic frame (ITU G.706) CEPT CRC-4 multiframe with timer (ITU G.706) CEPT CRC-4 multiframe with timer (automatic CRC-4/non-CRC-4 equipment interworking) (ITU G.706 Annex Nonalign (256 bits-clear channel) 2.048 coded mark inversion (CMI) coded interface (TTC standards JJ-20.11)
Superframe (D4, SLC-96): 2-state, 4-state, 16-state SPE: 2-state, 4-state, 16-state Extended superframe: 2-state, 4-state, 16-state CEPT: common channel signaling (CCS) (TS-16) Transparent (pass through) signaling J-ESF handling groups
Signaling features supported channel follows:
Signaling debounce Signaling freeze Signaling interrupt upon change state Signaling inhibit Signaling stomp
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TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
CEPT frames, bits sourced from either stack within this functional block from system interface. data link functional block only responds with valid data when selected source control bits.
Block Description (continued)
Voice data channels programmable robbed-bit signaling modes. entire payload forced into data-only signaling channels) mode (i.e., transparent mode, achieved programming control bit). Signaling access occurs through on-chip signaling registers system interface. Data associated signaling information accessed through system either CEPT-E1 modes. 5.14.5 Facility Data Link (FDL) Processor receive facility data link processor monitors bit-oriented data-link messages defined ANSI T1.403. transmit facility data link unit overrides FDL-FIFO transmission bit-oriented data-link messages defined ANSI T1.403-1995. processor extracts stores data link bits from three different frame types follows:
5.14.6 HDLC Unit HDLC processor formats HDLC packets insertion into programmable channels. channel number bits from time-slot. maximum number channels maximum channel rate kbits/s. minimum channel rate kbits/s. Each channel allocated bytes storage. HDLC processing data facility data link (PRMs, Sa-bits, otherwise) implemented assigning position logical HDLC channel.
D-bits delineator bits from SLC-96 multi-superframe. Data link bits from frames (bit time slot 24). multiframes Sa[4:8] bits from timeslot CEPT basic CRC-4 multiframes.
respective bits always extracted from framealigned frames stored stack. processor controls notification stack updates through interrupt (maskable) registers. transmit functional block performs transmission D-bits into SLC-96 Superframes, Sa-bits CEPT frames, D-bits frames.
SLC-96 frames, delineator bits always sourced from this functional block when block enabled insertion. frames, data link bits always sourced from this functional block when this block enabled insertion. This functional block also provides capability transmit BOMs (bit-oriented messages) data link channel links.
Agere Systems Inc.
TMXL84622 UltramapperLite 622/155 Mbits/s SONET/SDH DS3/E3/DS2/DS1/E1
HDLC LOPOH MCDR MRXC NSMI PBGA POAC PRBS QRSS TOAC UPSR
High-level data link control Line interface unit Loss-of-clock Loss-of-frame Loss signal Low-order path overhead frame Mate clock data recovery Multirate cross connect Network serial multiplexed interface Plastic ball grid array Path overhead access channel Pseudorandom sequence Performance report message Quasirandom signal source Remote alarm indicator Remote defect indication Remote error indication Synchronous digital hierarchy Severely errored frame Tandem connection monitoring Transport overhead access channels Unidirectional path switch ring
Glossary
BLSR B8ZS DACS FEAC FEBE HDB3 Alarm indication signal Alternate mark inversion Automatic protection switch Associated signaling mode error rate Bidirectional line switching ring Bit-oriented message Bipolar violation Bipolar zero substitution Common channel signaling Clock data recovery Concentrated highway interface Coded mark inversion Cyclic redundancy check Coding rule violation Digital access cross connects Digital jitter attenuation Extended superframe Excessive zeros Frame check sequence Facility data link Far-end alarm control Far-end block error High-density bipolar order three
Agere Systems Inc.
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February 2003 DS03-074BBAC (Replaces DS02-382BBAC)
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