Basic Interface Industry Standard UART Controllers Embedded Systems Sh

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Basic Interface Industry Standard UART Controllers Embedded Systems Sh

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CoreUART
Basic Interface Industry Standard UART Controllers Embedded Systems Sharing Data between Devices with Limited Counts Using Standard UART Protocols
Features
Synthesis: Exemplar, Synplicity, Design Compiler, FPGA Compiler, FPGA Express Simulation: Vital-Compliant VHDL Simulators OVI-Compliant Verilog Simulators
Asynchronous (UART) Mode Fully Programmable Baud Rate 1/16th System Clock Frequency with Glitch Rejection Synchronous Mode Clock Cycles Required Byte Transfer Bits Data Parity (Odd, Even, None) Baud Rate Control Asynchronous Mode Both Receive Transmit Double Buffered Maximize Throughput
Simulation Testbench
Family Family SX-A Family Family RT54SX-S Family ProASIC/ProASICPLUS Family Axcelerator Family
CoreUART serial communication controller with flexible serial data interface that intended primarily embedded systems. controller operate either asynchronous (UART) synchronous mode. synchronous mode, same UART protocols used, baud rate equivalent input clock frequency. When employing CoreUART synchronous mode, interacting devices must operate same system clock. asynchronous mode, clocks same different, including different frequencies. main reason synchronous mode improve data bandwidth. asynchronous mode, CoreUART used directly interface industry standard UARTs. CoreUART intentionally subset full UART capabilities order make function cost effective programmable device. Figure page illustrates various usages CoreUART. Case Figure page represents interface industry standard UART like 8251 16550. this case, CoreUART must operate asynchronous mode baud rates UART must match standard UART. Case Figure page represents embedded system. case both CoreUARTs operate either asynchronously synchronously CLKA CLKB. clocks different, then UART must operate asynchronous mode. Users need ensure that baud rates equal proper data transfers.
Netlist Version Compiled Simulation Model, Compliant with Actel's Libero(IDE) Integrated Design Environment Netlist Compatible with Actel Designer Place-andRoute Tool (with without pads) Version VHDL Verilog Core Source Code Synthesis Scripts Actel-Developed Testbench (VHDL)
December 2002
*See Actel's website latest version datasheet.
2002 Actel Corporation
CoreUART
Case
CLKA UART Actel Device Industry Standard UART CLKB
CoreUART
Figure shows block diagram CoreUART core functionality. baud generator creates divided down clock enable that correctly paces transmit receive state machines. synchronous case, baud generator utilized. function receive transmit state machines affected control inputs bit8, parity_en, odd_n_even. These signals indicate state machines many bits should transmitted. addition, signals also suggest type parity, parity should generated checked. asynchronous operation, activity state machines paced outputs baud generator. transmit data, data first loaded into transmit data buffer. Data loaded into buffer until TXrdy signal driven inactive. transmit state machine will immediately begin transmit data will continue transmission until data buffer empty. state machine first transmits START bit, followed data (LSB first), then parity (optional), finally STOP bit. data buffer double buffered, there loading latency. receive state machine monitors activity signal. Once START detected, receive state machine begins store data receive buffer until transaction complete, which turn activates receive_full signal, indicating valid data available. Parity errors reported parity_err signal enabled), data overrun conditions reported overflow signal.
Case
CLKA UART Actel Device UART Actel Device CLKA
Figure System Block Diagram Depicting CoreUART Usage
baud_val
Baud Generator
TXrdy data_in[7:0]
Data Buffer
Transmit State Machine
Receive State Machine
Data Buffer
receive_full data_out[7:0] parity_err overflow
parity_en bit8 odd_n_even
Figure Block Diagram CoreUART Functionality
CoreUART
Signal descriptions CoreUART defined Table signals broken down into following classes: system signals, parallel data transfer signals, serial control status signals, serial data signals. System signals consist reset_n signals. Parallel data Table CoreUART Signals
Name* reset_n data_in[7:0] data_out[7:0] Type Input Input Input Output Input Mode Sync/Async Sync/Async Sync/Async Sync/Async Sync/Async
transfer signals include data_in[7:0], data_out[7:0], WEn, OEn, CSn. Control signals bit8, parity_en, odd_n_even, baud_val. Status signals TXrdy, receive_full, parity_err, overflow. serial data signals consist
Description Main system clock Active asynchronous reset Transmit write data Receive read data Active write enable. This signal indicates that data presented data_in[7:0] should registered transmit buffer logic. This signal should only active single clock cycle transaction should only active when TXrdy signal active Active read enable. This signal used indicate that data data_out[7:0] been read will reset receive_full error conditions (overflow parity_err) Active chip select. signal qualifies both signals. embedded applications, this signal should tied logical Control data width both receive transmit functions. When bit8 logical `1,' then data width eight bits; otherwise, data width seven bits data defined data_in[7] ignored data_out[7] don't care Control enable parity both receive transmit functions. Parity enabled when logical Control define even parity both receive transmit functions. When parity_en control set, this indicates parity indicates even parity 8-bit control used define baud rate Status bit, when logical `0,' indicating that transmit data buffer available additional transmit data Status bit, when logical `1,' indicating that data available receive data buffer read system logic. data buffer controller must notified reception simultaneous activation signals prevent erroneous overflow conditions Status bit, when logical `1,' indicating parity error during receive transaction. This synchronously cleared simultaneous activation signals Status bit, when logical `1,' indicating receive overflow occurred. This synchronously cleared simultaneous activation signals Serial receive data
Input
Sync/Async
Input
Sync/Async
bit8
Input
Sync/Async
parity_en odd_n_even baud_val TXrdy
Input Input Input Output
Sync/Async Sync/Async Async Sync/Async
receive_full
Output
Sync/Async
parity_err
Output
Sync/Async
overflow Note:
Output Input
Sync/Async Sync/Async
Output Sync/Async Serial transmit data *Active signals designated with trailing lower-case
CoreUART
Utilization statistics targeted devices listed Table Table Table CoreUART Utilization Asynchronous Mode
Cells Tiles Family Axcelerator SX-A RT54SX-S ProASICPLUS ProASIC 42MX Note: Sequential Combinatorial Device AX500 A54SX08A RT54SX32S APA150 A54SX08 A500K050 A42MX09 eX128 Utilization Total
Data this table achieved using typical synthesis layout settings
Table CoreUART Utilization Synchronous Mode
Cells Tiles Family Axcelerator SX-A RT54SX-S ProASICPLUS ProASIC 42MX Note: Sequential Combinatorial Device AX500 A54SX08A RT54SX32S APA150 A54SX08 A500K050 A42MX09 eX128 Utilization Total
Data this table achieved using typical synthesis layout settings
Parity
CoreUART supports performance Actel FPGAs devices >100 Actel's Axcelerator family devices.
Customization Options
Parity enabled/disabled with input parity_en. When parity enabled, then odd_n_even input defines type parity.
Baud Rate
versions core customized asynchronous synchronous operations. netlist versions, versions core provided: synchronous other asynchronous operation.
asynchronous mode, baud rate must specified. This done setting value 8-bit baud_val bus. This value function system clock desired baud rate. value should according following equation:
baudval baud
There four programmable inputs CoreUART: baud_val (baud rate), bit8 (number data bits), parity_en (parity enable), odd_n_even (odd even parity).
Where: baud frequency system clock hertz desired baud rate hertz.
input bit8 used define number valid data bits serial bitstream. most significant "don't care" seven case.
term baudval needs rounded nearest integer. example, system with system clock 9600 desired baud rate should have baud_value decimal hex.
CoreUART
CoreUART Transaction
UART's waveforms broken down into basic functions: transmit data, receive data, errors. Figure shows serial transmit signals, Figure page shows serial receive signals. Figure page Figure page show parity overflow error cycles, respectively. simplify waveform description, waveforms shown synchronous mode. Asynchronous
transfers similar; however, serial transmission (START bit, data bits, parity bit, STOP bit) require more than clock cycle complete. number clocks required equal clock frequency divided baud rate. waveforms assume that eight bits data parity enabled.
data_in TXrdy
DATA
DATA
START
STOP START
Notes: serial transmit initiated writing data into CoreUART. This accomplished providing valid data asserting signals. TXrdy signal will become inactive cycle, while data being transferred from transmit hold register transmit register that begins serial transfer. transmission begins with START bit, followed data bits zero through six, optional seventh bit, optional parity bit, finally STOP bit. Because UART double buffered, data queued transmit hold register (cycle TXrdy line indicates that more data transferred UART. Once previous serial transfer complete, data transmit hold register passed transmit register transfer begins. TXrdy line also asserted indicating that next data byte loaded.
Figure Serial Transmit
CoreUART
data_out receive_full parity_err overflow
DATA
START
STOP
Notes: CoreUART continuously monitors line polling START bit. Once START detected, CoreUART registers data stream. optional parity also registered checked. Then data loaded into receive hold buffer receive_full signal asserted. receive_full signal will remain asserted until data read externally, indicated simultaneous assertion OEn.
Figure Serial Receive
data_out receive_full parity_err overflow
DATA
START
STOP
Notes: When parity error occurs, parity_err signal asserted. error cleared same method that data read, simultaneous assertion OEn.
Figure Parity Error
CoreUART
DATA_OUT receive_full parity_err overflow
Previous Data
START
STOP
Notes: When data overflow error occurs, overflow signal asserted. previous data held, data lost. error cleared same method that data read, simultaneous assertion OEn.
Figure Overflow Error
Order CoreUART through your local Actel sales representative. following numbering convention when ordering: CoreUART-XX, where listed Table Table Ordering Codes
Description Evaluation Version Single-use Netlist Actel devices Netlist unlimited Actel devices unlimited Actel devices unlimited restricted Actel devices
CoreUART
following table lists critical changes that were made current version document.
Previous version v4.0 Changes current version (v5.1) Table page updated. Table Table page new. Page page page
This version datasheet definition product. prototype available. Data presented subject significant changes.
This version datasheet provides nearly complete information prototype product. Code fully operational, support features expected production release. prototype core preliminary testbench available.
This version datasheet contains complete information final core. components fully operational core been thoroughly verified.
Actel Actel logo registered trademarks Actel Corporation. other trademarks property their owners.
http://www.actel.com
Actel Europe Ltd. Maxfli Court, Riverside Camberley, Surrey GU15 United Kingdom Tel: (0)1276 401450 Fax: (0)1276 401490 Actel Corporation East Arques Avenue Sunnyvale, California 94086 Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 1-24-14 Ebisu Shibuya-ku Tokyo Japan Tel: +81-(0)3-3445-7671 Fax: +81-(0)3-3445-7668
5172143-3/12.02

Basic Interface Industry Standard UART Controllers Embedded Systems Sh

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