Low-Power 0.8µ CMOS Technology Highly Predictable Performance wit

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Low-Power 0.8µ CMOS Technology Highly Predictable Performance wit

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HiRel FPGAs
Low-Power 0.8µ CMOS Technology
Highly Predictable Performance with 100% Automatic Placement Routing Device Sizes from 1,200 20,000 Gates Fast, Low-Skew Clock Networks User-Programmable Pins More Than Macro Functions 1,276 Dedicated Flip-Flops Drive Devices Available DSCC CQFP CPGA Packaging Nonvolatile, User Programmable Logic Fully Tested Prior Shipment 100% Military Temperature Tested (-55°C +125°C) Certified Devices
System Logic Integration Highest Speed FPGA SRAM, kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Low-Power 0.6µ CMOS Technology
Compatible with System Performance over Military Temperature Low-Power 0.6µ CMOS Technology
Proven Reliability Data Available Successful Military/Avionics Supplier Over Years
Best-Value, High-Capacity FPGA Family System Performance over Military Temperature Low-Power 1.0µ CMOS Technology
Highest-Performance, Highest-Capacity FPGA Family System Performance over Military Temperature
Lowest-Cost FPGA Family System Performance over Military Temperature Low-Power 1.0µ CMOS Technology
(more devices page
Family Device Capacity System Gates Logic Gates SRAM Bits Logic Modules S-Modules C-Modules Decode Flip-Flops (Maximum) User I/Os (Maximum) Performance System Speed (maximum) Packages Count) CPGA CQFP 3200DX A32100DX 15,000 10,000 2,048 1,362 A32200DX 30,000 20,000 2,560 2,414 1,230 1,184 1,276 A1425A 3,750 2,500 A1460A 9,000 6,000 A14100A 15,000 10,000 1,377 1,493 1200XL A1280XL 12,000 8,000 1,232
208,
2000 Actel Corporation
Family Device Capacity System Gates Logic Gates SRAM Bits Logic Modules S-Modules C-Modules Decode Flip-Flops (maximum) User I/Os (maximum) Packages count) CPGA CQFP Performance System Speed (maximum) A1240A 6,000 4,000 A1280A 12,000 8,000 1,232 A1010B 1,800 1,200 A1020B 3,000 2,000
Actel builds most reliable field programmable gate arrays (FPGAs) industry, with overall antifuse reliability ratings less than Failures-In-Time (FITs), corresponding useful life more than years. Actel FPGAs have been production proven, with more than five million devices shipped more than trillion antifuses manufactured. Actel devices fully tested prior shipment, with outgoing defect level less than ppm. (Further reliability data available Actel Device Reliability Report, http://www.actel.com/hirel).
junction temperatures. Actel's non-PLD architecture delivers lower dynamic operating current. reliability tests show very failure rate FITs 90°C junction temperature with degradation performance. Special stress testing wafer test eliminates infant mortalities prior packaging.
ized
Reverse engineering programmed Actel devices from optical electrical data extremely difficult. Programmed antifuses cannot identified from photograph using SEM. antifuse cannot deciphered either electrically microprobing. Each device silicon signature that identifies origins, down wafer fabrication facility.
ized
With Actel's line development tools, designers produce many chips they choose just cost device itself. There will charges into development budget each time design tried.
After design entered, placement routing automatic, programming device takes only about minutes average design. Designers save time design entry process using tools with which they familiar.
iabi
Unprogrammed Actel parts extensively tested factory. Routing tracks, logic modules, programming, debug test circuits percent tested before shipment. performance ensured special speed path tests, programming circuitry verified test antifuses. During programming process, algorithm ensure that antifuses correctly programmed. addition, Actel's Silicon Explorer diagnostic tool uses ActionProbe circuitry, allowing percent observability internal nodes check debug design.
PLICE antifuse one-time programmable, nonvolatile connection. Since Actel devices permanently programmed, downloading from EPROM SRAM storage required. Inadvertent erasure impossible, there need reload program after power disruptions. Fabrication using low-power CMOS process means cooler
Actel families FPGAs offer variety packages, speed/performance characteristics, processing levels high reliability military applications. Devices implemented silicon gate, two-level metal CMOS process, utilizing Actel's PLICE antifuse technology. This
unique architecture offers gate array flexibility, high performance, quick turnaround through user programming. Device utilization typically percent available logic modules. Actel devices include on-chip clock drivers hard-wired distribution network. User-definable I/Os capable driving both CMOS drive levels. Available packages military Ceramic Quad Flat Pack (CQFP) Ceramic Grid Array (CPGA). "Product Plan" section page details.
family third-generation Actel FPGA family. This family offers highest-performance highest-capacity devices, ranging from 2,500 10,000 gates, with system performance over military temperature range. devices have four clock distribution networks, including dedicated array clocks. addition, family offers highest I/O-to-gate ratio available. devices manufactured using 0.8µ CMOS technology.
Actel achieved full certification, demonstrating that quality management, procedures, processes, controls place comply with MIL-PRF-38535, performance specification used Department Defense monolithic integrated circuits. certification good example Actel's commitment supplying highest quality products types high-reliability, military space applications. Many suppliers microelectronics components have implemented their primary worldwide business system. Appropriate this system only helps implementation advanced technologies, also allows quality, reliable cost-effective logistics support throughout products' life cycles.
3200DX 1200XL FPGAs were designed integrate system logic which typically implemented multiple CPLDs, PALs, FPGAs. These devices provide features performance required today's complex, high-speed digital logic systems. 3200DX family offers industry's fastest dual-port SRAM implementing fast FIFOs, LIFOs, temporary data storage.
family second-generation Actel FPGA family. This family offers best-value, high-capacity devices, ranging from 4,000 8,000 gates, with system performance over military temperature range. devices have routed array clock distribution networks. devices manufactured using 1.0µ CMOS technology.
HiRel devices fully supported Actel's line FPGA development tools, including Actel DeskTOP series Designer Advantage tools. Actel DeskTOP Series integrated design environment that includes design entry, simulation, synthesis, place route tools. Designer Advantage Actel's suite FPGA development point tools Workstations that includes ACTgen Macro Builder, Designer with DirectTime timing driven place route analysis tools, device programming software. addition, HiRel devices contain ActionProbe circuitry that provides built-in access every node design, enabling percent real-time observation analysis device's internal logic nodes without design iteration. probe circuitry accessed Silicon Explorer, easy integrated verification logic analysis tool that sample data (asynchronous) (synchronous). Silicon Explorer attaches PC's standard port, turning into fully functional channel logic analyzer. Silicon Explorer allows designers complete design verification process their desks reduces verification time from several hours cycle seconds.
family first Actel FPGA family first antifuse-based FPGA. This family offers lowest-cost logic integration, with devices ranging from 1,200 2,000 gates, with system performance over military temperature range. devices have routed array clock distribution network. devices manufactured using 1.0µ CMOS technology.
A14100
Application (Temperature Range) Commercial +70°C) Military (-55 +125°C) MIL-STD-883 Class Extended Flow (Space Level) Package Lead Count Package Type Ceramic Quad Flat Pack (CQFP) Ceramic Grid Array (CPGA) Speed Grade Standard Speed Approximately faster than Standard Device Revision Part Number A1010 A1020 A1240 A1280 A1425 A1460 A14100 A32100 A32200
1,200 Gates-ACT 2,000 Gates-ACT 4,000 Gates-ACT 8,000 Gates-ACT 2/1200XL 2,500 Gates-ACT 6,000 Gates-ACT 10,000 Gates-ACT 10,000 Gates-3200DX 20,000 Gates-3200DX
Actel Part Number (Gold Leads) A1010B-PG84B A1010B-1PG84B A1020B-PG84B A1020B-1PG84B A1020B-CQ84B A1020B-1CQ84B A1240A-PG132B A1240A-1PG132B A1280A-PG176B A1280A-1PG176B A1280A-CQ172B A1280A-1CQ172B A1425A-PG133B A1425A-1PG133B A1425A-CQ132B A1425A-1CQ132B A1460A-PG207B A1460A-1PG207B A1460A-CQ196B A1460A-1CQ196B A14100A-PG257B A14100A-1PG257B A14100A-CQ256B A14100A-1CQ256B A32100DX-CQ84B A32100DX-1CQ84B A32200DX-CQ256B A32200DX-1CQ256B A32200DX-CQ208B A32200DX-1CQ208B DSCC (Gold Leads) 5962-9096403MXC 5962-9096404MXC 5962-9096503MUC 5962-9096504MUC 5962-9096503MTC 5962-9096504MTC 5962-9322101MXC 5962-9322102MXC 5962-9215601MXC 5962-9215602MXC 5962-9215601MYC 5962-9215602MYC 5962-9552001MXC 5962-9552002MXC 5962-9552001MYC 5962-9552002MYC 5962-9550801MXC 5962-9550802MXC 5962-9550801MYC 5962-9550802MYC 5962-9552101MXC 5962-9552102MXC 5962-9552101MYC 5962-9552102MYC 5962-9875901QXC 5962-9857902QXC 5962-9952701QXC 5962-9952702QXC 5962-9952701QYC 5962-9952702QYC DSCC (Solder Dipped) 5962-9096403MXA 5962-9096404MXA 5962-9096503MUA 5962-9096504MUA 5962-9096503MTA 5962-9096504MTA 5962-9322101MXA 5962-9322102MXA 5962-9215601MXA 5962-9215602MXA 5962-9215601MYA 5962-9215602MYA
Speed Grade Application
A32100DX Device 84-pin Ceramic Quad Flat Pack (CQFP) A32200DX Device 208-pin Ceramic Quad Flat Pack (CQFP) 256-pin Ceramic Quad Flat Pack (CQFP)
A1425A Device 132-pin Ceramic Quad Flat Pack (CQFP) 133-pin Ceramic Grid Array (CPGA) A1460A Device 196-pin Ceramic Quad Flat Pack (CQFP) 207-pin Ceramic Grid Array (CPGA) A14100A Device 256-pin Ceramic Quad Flat Pack (CQFP) 257-pin Ceramic Grid Array (CPGA)
A1280XL Device 172-pin Ceramic Quad Flat Pack (CQFP) 176-pin Ceramic Grid Array (CPGA)
A1240A Device 132-pin Ceramic Grid Array (CPGA) A1280A Device 172-pin Ceramic Quad Flat Pack (CQFP) 176-pin Ceramic Grid Array (CPGA)
A1010B Device 84-pin Ceramic Grid Array (CPGA) A1020B Device 84-pin Ceramic Quad Flat Pack (CQFP) 84-pin Ceramic Grid Array (CPGA) Applications: Commercial Military MIL-STD-883 Extended Flow Availability: Available Planned *Speed Grade: Approx. faster than Standard
User I/Os FPGA Device Type A32100DX A32200DX Logic Modules 1,362 2,414 Gate Array Equivalent Gates 10,000 20,000 CQFP 84-pin 208-pin 256-pin
User I/Os FPGA Device Type A1425A A1460A A14100A Logic Modules 1,377 Gate Array Equivalent Gates 2,500 6,000 10,000 CQFP 132-pin 196-pin 256-pin 133-pin CPGA 207-pin 257-pin
User I/Os FPGA Device Type A1280XL Logic Modules 1,232 Gate Array Equivalent Gates 8,000 CQFP 172-pin CPGA 176-pin
User I/Os FPGA Device Type A1240A A1280A Logic Modules 1,232 Gate Array Equivalent Gates 4,000 8,000 CQFP 172-pin 132-pin CPGA 176-pin
User I/Os FPGA Device Type A1010B A1020B Logic Modules Gate Array Equivalent Gates 1,200 2,000 CQFP 84-pin CPGA 84-pin
Step Screen Internal Visual Temperature Cycling Constant Acceleration Seal Fine Gross Visual Inspection Pre-Burn-In Electrical Parameters Burn-in Test Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable Final Electrical Test Static Tests 25°C (Subgroup Table -55°C +125°C (Subgroups Table Functional Tests 25°C (Subgroup Table -55°C +125°C (Subgroups Table Switching Tests 25°C (Subgroup Table Note: External Visual Method 2010, Test Condition 1010, Test Condition 2001, Test Condition Orientation Only 1014 100% 100% 2009 accordance with applicable Actel device specification 1015, Condition hours 125°C hours 150°C accordance with applicable Actel device specification accordance with applicable Actel device specification, which includes 100% 5005 5005 100% 5005 5005 100% 5005 2009 100% 100% 100% 100% 100% Lots 883-Class Requirement 100% 100% 100%
When Destructive Physical Analysis (DPA) performed Class devices, step coverage requirement specified Method 2018 must waived.
Step Screen Wafer Acceptance2 Destructive In-Line Bond Pull Internal Visual Serialization Temperature Cycling Constant Acceleration Particle Impact Noise Detection Radiographic Pre-Burn-In Test Burn-in Test Interim (Post-Burn-In) Electrical Parameters Reverse Bias Burn-In Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test Static Tests 25°C (Subgroup Table1) -55°C +125°C (Subgroups Table Functional Tests 25°C (Subgroup Table -55°C +125°C (Subgroups Table Switching Tests 25°C (Subgroup Table Seal Fine Gross External Visual 2009 100% 1010, Condition 2001, Condition Orientation Only 2020, Condition 2012 (one view only) accordance with applicable Actel device specification 1015, Condition hours 125°C minimum accordance with applicable Actel device specification 1015, Condition hours 150°C minimum accordance with applicable Actel device specification Functional Parameters 25°C accordance with Actel applicable device specification which includes 5005 5005 100% 5005 5005 100% 5005 1014 100%
Method 5007 with Step Coverage Waiver 2011, Condition 2010, Condition
Requirement Lots Sample 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% Lots 100% 100%
Notes: Actel offers extended flow customers require additional screening beyond requirements MIL-STD-833, Class Actel compliant requirements MIL-STD-883, Paragraph 1.2.1, MIL-I-38535, Appendix Actel offering this extended flow incorporating majority screening procedures outlined Method 5004 MIL-STD-883, Class exceptions Method 5004 shown notes below. Wafer acceptance performed Method 5007; however, step coverage requirement specified Method 2018 must waived. MIL-STD-883, Method 5004 requires percent Radiation latch-up testing (Method 1020). Actel will performing radiation testing, this requirement must waived entirety.
Free temperature range Symbol TSTG Parameter Supply Voltage2, Input Voltage Output Voltage Source Sink Current5 Storage Temperature Limits -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150 Units
Parameter Temperature Range1 Power Supply Tolerance2 Commercial Military +125 Units %VCC
Notes: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside recommended operating conditions. except during device programming. except during device programming. except during device programming. Device inputs normally high impedance draw extremely current. However, when input voltage greater than 0.5V less than 0.5V, internal protection diode will forward biased draw excessive current.
Notes: Ambient temperature (TA) used commercial industrial; case temperature (TC) used military. power supplies must recommended operating range. more information, refer Power-Up Design Considerations application note http://www.actel.com/appnotes.
Commercial Symbol VOH1, VOL1, ICC(S) Parameter HIGH Level Output Test Condition (CMOS) (CMOS) Level Output HIGH Level Input Level Input Input Leakage 3-state Output Leakage Capacitance3, Standby Supply Current GND, 2/3/1200XL/3200DX ICC(D) Dynamic Supply Current (CMOS) Inputs Inputs -0.3 3.84 0.33 -0.3 Min. Max. Min. Military Max. Units
"Power Dissipation" section page
Notes: Actel devices drive receive either CMOS signal levels. assignment I/Os CMOS required. Tested output time, min. tested; information only. VOUT
device junction case thermal characteristic junction ambient characteristic thermal characteristics shown with different flow rates.
Maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed CPGA 176-pin package military temperature follows:
Max. junction temp. (°C) Max. military temp. 150°C 125°C -23°C/W (°C/W) Still ft/min
Package Type Ceramic Grid Array
Count
Units °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W
Ceramic Quad Flat Pack
Gener quat
[ICCstandby ICCactive] (VCC VOH) where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH. Accurate values difficult determine because they depend family type, design, system I/O. power divided into components-static active.
ponen
power standby current typically small component overall power. Standby power calculated below commercial, worst-case conditions. Family 1200XL/3200DX 5.25V 5.25V 5.25V 5.25V Power 10.5 10.5 10.5 15.8
static power dissipated loads depends number outputs driving high load current. Again, this value typically small. instance, 32-bit sinking 0.33V will generate with outputs driving low, with outputs driving high.
ower nent
Actel FPGAs have small static power components that result power dissipation lower than that PALs PLDs. integrating multiple PALs PLDs into FPGA, even greater reduction board-level power dissipation achieved.
Power dissipation CMOS devices usually dominated active (dynamic) power dissipation. This component frequency dependent, function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitance board traces load device inputs. additional component active power dissipation totempole current CMOS transistor pairs. effect associated with equivalent capacitance that
combined with frequency voltage represent active power dissipation.
quiv apac ance
where: Number logic modules switching Number input buffers switching Number output buffers switching Number clock loads first routed array clock (all families) Number clock loads second routed array clock (ACT 1200XL, 3200DX, only) Fixed capacitance first routed array clock (all families) Fixed capacitance second routed array clock (ACT 1200XL, 3200DX, only) Fixed number clock loads dedicated array clock (ACT only) Fixed number clock loads dedicated clock (ACT only) Equivalent capacitance logic modules Equivalent capacitance input buffers Equivalent capacitance output buffers Equivalent capacitance routed array clock Equivalent capacitance dedicated array clock Equivalent capacitance dedicated clock Output lead capacitance Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate (all families) Average second routed array clock rate (ACT 1200XL, 3200DX, only) Average dedicated array clock rate (ACT only) Average dedicated clock rate (ACT only)
power dissipated CMOS circuit expressed Equation Power (uW) VCC2 where: Equivalent capacitance Power supply volts Switching frequency
CEQM CEQI CEQO CEQCR CEQCD
Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements made over range frequencies fixed value VCC. Equivalent capacitance frequency independent that results used over wide range operating conditions. Equivalent capacitance values shown below.
1200XL 3200DX Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR) Dedicated Clock Buffer Loads (CEQCD) Clock Buffer Loads (CEQCI) 10.4 11.6 23.8 12.9 23.8 22.1 31.2
CEQCI
calculate active power dissipated from complete design, switching frequency each part logic must known. Equation shows piecewise linear summation over components that applies 1200XL, 3200DX, devices. Since family only routed array clock, terms labeled routed_Clk2, dedicated_Clk, IO_Clk apply. Similarly, family routed array clocks, dedicated_Clk IO_Clk terms apply. devices, terms will apply. Power VCC2 CEQM* fm)modules CEQI* fn)inputs (CEQO+ fp)outputs CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR fq2)routed_Clk2 fq2)routed_Clk2 CEQCD fs1)dedicated_Clk CEQCI fs2)IO_Clk]
Capa (pF)
Loads
Device Type A1010B A1020B A1240A A1280A A1280XL A1425A A1460A A14100A A32100DX A32200DX
Type Logic modules Input switching Outputs switching
routed_Clk1
routed_Clk2
modules inputs/4 #outputs/4 sequential modules sequential modules F/10 F/10
Device Type A1425A A1460A A14100A
Clock Loads Dedicated Array Clock
Clock Loads Dedicated Clock
hing ency
determine switching frequency design, must have detailed understanding data values input circuit. guidelines table below meant represent worst-case scenarios that they generally used predict upper limits power dissipation.
3200DX/ACT 2/1200XL modules inputs/4 #outputs/4 sequential modules sequential modules F/10 F/10
modules inputs/4 #outputs/4 modules F/10 F/10
First routed array clock loads (q1) Second routed array clock loads (q2) Load capacitance (CL) Average logic module switching rate (fm) Average input switching rate (fn) Average output switching rate (fp) Average first routed array clock rate (fq1) Average second routed array clock rate (fq2) Average dedicated array clock rate Average dedicated clock rate (fs2)
Input Delays Module tINPY IRD1
Internal Delays
Predicted Routing Delays
Output Delays Module
Combinatorial Module tRD1 tRD2 tRD4
tDLH
tINH tINSU tINGO Decode Module tPDD Module tDLH
tRDD
Sequential Logic Module
Combinatorial Logic included tSUD
tRD1
tENHZ 11.5
tLSU tGHL= 12.4
ARRAY CLOCKS tCKH FMAX
*Values shown A32100DX-1 worst-case military conditions.
Input Delays Module tINPY IRD1
Internal Delays
Predicted Routing Delays
Output Delays Module
Combinatorial Module tRD1 tRD2 tRD4
tDLH
tINH tINSU tINGO Decode Module tPDD Module tDLH
tRDD
Sequential Logic Module
Combinatorial Logic included tSUD
tRD1
tENHZ 11.5
tLSU tGHL= 12.4
QUADRANT CLOCKS tCKH ns**
FMAX
Values shown A32100DX-1 worst-case military conditions. Load dependent.
Input Delays Module tINPY IRD1
tINSU tINH tINGO
Predicted Routing Delays [7:0] WRAD [5:0] BLKEN WCLK tADSU tADH tWENSU tBENS [7:0] RDAD [5:0] tRD1
Module tDLH
RCLK tADSU tADH tRENSU tRCO
tGHL 12.4 tLSU
ARRAY CLOCKS FMAX
*Values shown A32100DX-1 worst-case military conditions.
Input Delays
Internal Delays
Combinatorial Module Logic Module tINYL IRD2
Predicted Routing Delays
Output Delays Module
tDLH tRD1 tRD2 tRD4 tRD8
tINH tINSU tINGL Sequential Logic Module
Combinatorial Logic included tSUD
Module tDLH
tRD1
tENHZ
tOUTH tOUTSU tGLH
ARRAY CLOCKS
tCKH FMAX
tLCO 10.7 loads, pad-pad)
*Values shown A1280XL-1 worst-case military conditions. Input module predicted routing delay.
TRIBUFF test loads (shown below)
tDLH 1.5V tDHL 1.5V
1.5V tENZL tENLZ
1.5V tENZH tENHZ
Test Load
Load (Used measure propagation delay)
Load (Used measure rising/falling edges)
output under test
output under test
tPLZ/tPZL tPHZ/tPZH
Inpu Buffe
Macr
INBUF
tINYH 1.5V 1.5V tINYL
tPLH tPHL
tPHL tPLH
(Positive edge triggered)
tSUD
tWCLKA tSUENA tHENA
tCLR tWASYN Note: represents data functions involving multiplexed flip-flops.
(continued)
(120 200D
(Positive edge triggered)
tSUD
tWCLKA tSUENA tHENA
PRE, tWASYN
Note: represents data functions involving multiplexed flip-flops.
(continued)
ffer 200D
IBDL
CLKBUF
tINH tINSU tHEXT tSUEXT
Buffe 1200
OBDLHS
tOUTSU tOUTH
A-G, tPHL tPLH
Write Port WRAD [5:0] BLKEN WCLK [7:0] Array 32x8 64x4 (256 bits)
Read Port RDAD [5:0] RCLK [7:0]
3200
tRCKHL WCLK tADSU WD[7:0] WRAD[5:0] Valid tWENSU tBENSU BLKEN Valid tBENH tWENH tADH
tRCKHL
Note:
Identical timing falling-edge clock.
3200 nous Oper
tCKHL RCLK
tRCKHL
tRENSU tADSU RDAD[5:0] Valid
tRENH
tADH
tRCO tDOH RD[7:0] Data Data
Note:
Identical timing falling-edge clock.
3200 hronous Oper
(Read Address Controlled)
tRDADV RDAD[5:0] ADDR1 tDOH RD[7:0] Data ADDR2 tRPD Data
3200 hronous Oper
(Write Address Controlled)
tWENSU
tWENH
WD[7:0] WRAD[5:0] BLKEN
Valid tADSU tADH tRPD tDOH
WCLK
RD[7:0]
Data
Data
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Logic Module Propagation Delays tPD1 tPD2 Single Module Dual Module Macros Sequential Latch Flip-Flop (Latch) Reset 10.8 12.7
Logic Module Predicted Routing Delays1 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.6
12.5
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN fMAX
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency
10.9 10.9 23.2
10.4 10.4 12.9 12.9 27.3
Input Module Propagation Delays tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 High
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.6
12.5
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Setup times assume fanout Further derating information obtained from DirectTime Analyzer utility. Optimization techniques further reduce delays
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 21.7 23.2 10.4 10.9 10.4 10.9 25.6 27.3 10.3 11.2 12.2 12.9 12.2 12.9 10.5 12.1 13.2
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data High Data Enable High Enable Enable High Enable Delta High Delta High 12.1 13.8 12.0 14.6 16.0 14.5 0.09 0.12 14.2 16.3 14.1 17.1 18.8 17.0 0.11 0.15 ns/pF ns/pF
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data High Data Enable High Enable Enable High Enable Delta High Delta High 15.1 11.5 12.0 14.6 16.0 14.5 0.16 0.09 17.7 13.6 14.1 17.1 18.8 17.0 0.18 0.11 ns/pF ns/pF
Notes: Delays based loading. information found Simultaneously Switching Output Limits Actel FPGAs application note http://www.actel.com/appnotes.
Cond
`-1' Speed Parameter Description
`Std' Speed Min. Max. Units
Min.
Max.
Logic Module Propagation Delays tPD1 tRD1 tRD2 tRD3 tRD4 tRD8 Single Module
Sequential Latch Flip-Flop (Latch) Reset
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
14.8 -3.5
18.6 -3.5
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Setup hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Input Module Propagation Delays tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 High High
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.9
12.9
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency 13.8 11.5 12.2 13.8 13.5 14.3 13.3 16.3 13.3 16.5 15.7 19.2 15.7 19.5
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Data High Data Enable High Enable Enable High Enable High Delta High Delta High 11.0 13.9 12.3 16.1 11.5 12.4 15.5 0.09 0.17 13.0 16.4 14.4 19.0 11.5 13.6 14.6 18.2 0.11 0.20 ns/pF ns/pF
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Data High Data Enable High Enable Enable High Enable High Delta High Delta High 14.0 11.7 12.3 16.1 11.5 12.4 15.5 0.17 0.12 16.5 13.7 14.4 19.0 11.5 13.6 14.6 18.2 0.20 0.15 ns/pF ns/pF
Notes: Delays based loading. information found Simultaneously Switching Output Limits Actel FPGAs application note http://www.actel.com/appnotes.
Cond
`-1' Speed Parameter Description
`Std' Speed Min. Max. Units
Min.
Max.
Logic Module Propagation Delays tPD1 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Single Module
Sequential Latch Flip-Flop (Latch) Reset
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.8
Logic Module Sequential Timing
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
16.4 -3.5
22.1 -3.5
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Setup hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
Cond
`-1' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL tRD1 tRD2 tRD3 tRD4 tRD8 High High
`Std' Speed Min. Max. Units
Min.
Max.
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
12.9
10.5 15.2
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency 13.8 13.7 16.0 13.8 16.2 18.9 13.3 17.9 13.3 18.2 15.7 21.1 15.7 21.4
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays
(continued)
Cond
`-1' Speed Parameter Description
`Std' Speed Min. Max. Units
Min.
Max.
Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL
Data High Data Enable High Enable Enable High Enable High Delta High Delta High
11.0 13.9 12.3 16.1 11.5 12.4 15.5 0.09 0.17
13.0 16.4 14.4 19.0 11.5 13.6 14.6 18.2 0.11 0.20
ns/pF ns/pF
CMOS Output Module Timing
Data High Data Enable High Enable Enable High Enable High Delta High Delta High
14.0 11.7 12.3 16.1 11.5 12.4 15.5 0.17 0.12
16.5 13.7 14.4 19.0 11.5 13.6 14.6 18.2 0.20 0.15
ns/pF ns/pF
Notes: Delays based loading. information found Simultaneously Switching Output Limits Actel FPGAs application note http://www.actel.com/appnotes.
Cond
`-1' Speed Parameter Description
`Std' Speed Min. Max. Units
Min.
Max.
Logic Module Propagation Delays tPD1 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Single Module
Sequential Latch Flip-Flop (Latch) Reset
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
10.7
12.3
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Setup hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
Cond
`-1' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL tRD1 tRD2 tRD3 tRD4 tRD8 High High
`Std' Speed Min. Max. Units
Min.
Max.
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.8
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency 10.7 11.8
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays
(continued)
Cond
`-1' Speed Parameter Description
`Std' Speed Min. Max. Units
Min.
Max.
Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL
Data High Data Enable High Enable Enable High Enable High Delta High Delta High
0.05 0.05
0.06 0.09
ns/pF ns/pF
CMOS Output Module Timing
Data High Data Enable High Enable Enable High Enable High Delta High Delta High
0.07 0.06
0.09 0.09
ns/pF ns/pF
Notes: Delays based loading. information found Simultaneously Switching Output Limits Actel FPGAs application note http://www.actel.com/appnotes.
Cond
`-1' Speed Parameter Description
`Std' Speed Min. Max. Units
Min.
Max.
Logic Module Propagation Delays tCLR tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWASYN tWCLKA fMAX
Internal Array Module Sequential Clock Asynchronous Clear
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency
Input Module Propagation Delays tINY tICKY tOCKY tICLRY tOCLRY Input Data Input IOCLK Output IOCLK Input Asynchronous Clear Output Asynchronous Clear
Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Notes: dual-module macros, tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input Data Hold (w.r.t. IOCLK Pad) Input Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output Data Hold (w.r.t. IOCLK Pad) Output Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad)
10.0
Output Module Timing tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS
Data Pad, High Slew Data Pad, Slew Enable Pad, H/L, High Slew Enable Pad, H/L, Slew Enable Pad, High Slew Enable Pad, Slew IOCLK H/L, High Slew IOCLK H/L, Slew Delta High, High Slew Delta High, Slew Delta High Low, High Slew Delta High Low, Slew
11.9 10.9 10.5 15.7 0.04 0.07 0.05 0.07
14.0 12.8 11.6 11.6 11.6 17.4 0.04 0.08 0.06 0.08
ns/pF ns/pF ns/pF ns/pF
Note: Delays based loading.
(continued)
Cond
`-1' Speed Parameter Description
`Std' Speed Min. Max. Units
Min.
Max.
CMOS Output Module Timing tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX
Data Pad, High Slew Data Pad, Slew Enable Pad, H/L, High Slew Enable Pad, H/L, Slew Enable Pad, High Slew Enable Pad, Slew IOCLK H/L, High Slew IOCLK H/L, Slew Delta High, High Slew Delta High, Slew Delta High Low, High Slew Delta High Low, Slew
17.3 13.1 10.5 12.5 18.1 0.06 0.11 0.04 0.05
10.8 20.3 15.5 11.6 11.6 13.7 20.1 0.07 0.13 0.05 0.06
ns/pF ns/pF ns/pF ns/pF
Dedicated (Hard-Wired) Clock Network Input High (Pad Module Input) Minimum Pulse Width High Minimum Pulse Width Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency
Dedicated (Hard-Wired) Array Clock Network Input High (Pad S-Module Input) Input High (Pad S-Module Input) Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Notes: Delays based loading. information found Simultaneously Switching Output Limits Actel FPGAs application note http://www.actel.com/appnotes.
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW fRMAX tIOHCKSW tIORCKSW tHRCKSW Input High (FO=64) Input High (FO=64) Min. Pulse Width High (FO=64) Min. Pulse Width (FO=64) Maximum Skew (FO=128) Minimum Period (FO=64) Maximum Frequency (FO=64) 10.1 11.6
Clock-to-Clock Skews Clock H-Clock Skew Clock R-Clock Skew H-Clock R-Clock Skew max.)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Logic Module Propagation Delays1 tCLR Internal Array Module Sequential Clock Asynchronous Clear
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWASYN tWCLKA fMAX Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 11.6
Input Module Propagation Delays tINY tICKY tOCKY tICLRY tOCLRY Input Data Input IOCLK Output IOCLK Input Asynchronous Clear Output Asynchronous Clear
Input Module Predicted Routing Delays2, tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Notes: dual-module macros, tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input Data Hold (w.r.t. IOCLK Pad) Input Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output Data Hold (w.r.t. IOCLK Pad) Output Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad)
10.0
Output Module Timing tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS
Data Pad, High Slew Data Pad, Slew Enable Pad, H/L, High Slew Enable Pad, H/L, Slew Enable Pad, High Slew Enable Pad, Slew IOCLK H/L, High Slew IOCLK H/L, Slew Delta High, High Slew Delta High, Slew Delta High Low, High Slew Delta High Low, Slew
11.9 10.9 11.5 10.9 11.6 17.8 0.04 0.07 0.05 0.07
14.0 12.8 13.5 12.8 13.4 19.8 0.04 0.08 0.06 0.08
ns/pF ns/pF ns/pF ns/pF
Note: Delays based loading.
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
CMOS Output Module Timing1 tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Data Pad, High Slew Data Pad, Slew Enable Pad, H/L, High Slew Enable Pad, H/L, Slew Enable Pad, High Slew Enable Pad, Slew IOCLK H/L, High Slew IOCLK H/L, Slew Delta High, High Slew Delta High, Slew Delta High Low, High Slew Delta High Low, Slew 17.3 13.1 10.9 10.9 14.1 20.2 0.06 0.11 0.04 0.05 10.8 20.3 15.5 12.8 12.8 16.0 22.4 0.07 0.13 0.05 0.06 ns/pF ns/pF ns/pF ns/pF
Dedicated (Hard-Wired) Clock Network Input High (Pad Module Input) Minimum Pulse Width High Minimum Pulse Width Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency 11.6
Dedicated (Hard-Wired) Array Clock Network Input High (Pad S-Module Input) Input High (Pad S-Module Input) Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 11.6
Notes: Delays based loading. information found Simultaneously Switching Output Limits Actel FPGAs application note http://www.actel.com/appnotes.
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW fRMAX tIOHCKSW tIORCKSW tHRCKSW Input High (FO=256) Input High (FO=256) Min. Pulse Width High (FO=256) Min. Pulse Width (FO=256) Maximum Skew (FO=128) Minimum Period (FO=256) Maximum Frequency (FO=256) 12.9 14.5 10.5 10.5
Clock-to-Clock Skews Clock H-Clock Skew Clock R-Clock Skew H-Clock R-Clock Skew max.)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Logic Module Propagation Delays1 tCLR Internal Array Module Sequential Clock Asynchronous Clear
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWASYN tWCLKA fMAX Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 11.6
Input Module Propagation Delays tINY tICKY tOCKY tICLRY tOCLRY Input Data Input IOCLK Output IOCLK Input Asynchronous Clear Output Asynchronous Clear
Input Module Predicted Routing Delays2, tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Notes: dual-module macros, tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input Data Hold (w.r.t. IOCLK Pad) Input Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output Data Hold (w.r.t. IOCLK Pad) Output Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad)
10.0
Output Module Timing tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS
Data Pad, High Slew Data Pad, Slew Enable Pad, H/L, High Slew Enable Pad, H/L, Slew Enable Pad, High Slew Enable Pad, Slew IOCLK H/L, High Slew IOCLK H/L, Slew Delta High, High Slew Delta High, Slew Delta High Low, High Slew Delta High Low, Slew
11.9 10.9 11.9 10.9 12.2 17.8 0.04 0.07 0.05 0.07
14.0 12.8 14.0 12.8 14.0 17.8 0.04 0.08 0.06 0.08
ns/pF ns/pF ns/pF ns/pF
Note: Delays based loading.
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
CMOS Output Module Timing1 tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Data Pad, High Slew Data Pad, Slew Enable Pad, H/L, High Slew Enable Pad, H/L, Slew Enable Pad, High Slew Enable Pad, Slew IOCLK H/L, High Slew IOCLK H/L, Slew Delta High, High Slew Delta High, Slew Delta High Low, High Slew Delta High Low, Slew 17.3 13.1 11.6 10.9 14.4 20.2 0.06 0.11 0.04 0.05 10.8 20.3 15.5 14.0 12.8 16.0 22.4 0.07 0.13 0.05 0.06 ns/pF ns/pF ns/pF ns/pF
Dedicated (Hard-Wired) Clock Network tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input High (Pad Module Input) Minimum Pulse Width High Minimum Pulse Width Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency 11.6
Dedicated (Hard-Wired) Array Clock Network Input High (Pad S-Module Input) Input High (Pad S-Module Input) Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 11.6
Notes: Delays based loading. information found Simultaneously Switching Output Limits Actel FPGAs application note http://www.actel.com/appnotes.
(continued)
Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW fRMAX tIOHCKSW tIORCKSW tHRCKSW Input High (FO=256) Input High (FO=256) Min. Pulse Width High (FO=256) Min. Pulse Width (FO=256) Maximum Skew (FO=128) Minimum Period (FO=256) Maximum Frequency (FO=256) 12.9 14.5 10.5 10.5
Clock-to-Clock Skews Clock H-Clock Skew Clock R-Clock Skew H-Clock R-Clock Skew max.)
(Wor Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Logic Module Combinatorial Functions tPDD tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tSUENA tHENA tWCLKA tWASYN Internal Array Module Delay Internal Decode Module Delay
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Decode-to-Output Routing Delay
Logic Module Sequential Timing Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Setup Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset Output Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
(continued)
(Wor Cond
'-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Read Cycle Time Write Cycle Time Clock High/Low Time Data Valid After Clock High/Low Address/Data Setup Time Address/Data Hold Time Read Enable Setup Read Enable Hold Write Enable Setup Write Enable Hold Block Enable Setup Block Enable Hold 11.8 11.8
Asynchronous SRAM Operations Asynchronous Access Time Read Address Valid Address/Data Setup Time Address/Data Hold Time Read Enable Setup Address Valid Read Enable Hold Write Enable Setup Write Enable Hold Data Hold Time 11.5 10.6 15.3 14.1
(continued)
(Wor Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fHMAX Input Data Input Latch Gate-to-Output Input Latch Hold Input Latch Setup Latch Active Pulse Width
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period (1/fmax) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 10.5 10.6 11.8
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays
(continued)
(Worst-Case Military Conditions, 4.5V, 125°C)
`-1' Speed Parameter Description
`Std' Speed Min. Max. Units
Min.
Max.
Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tWDO tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tWDO
Data High Data Enable High Enable Enable High Enable High Latch Output Setup Latch Output Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High Hard-Wired Wide Decode Output
11.5 11.5 11.5 12.4 11.5 16.3 0.04 0.06 0.05
15.3 15.3 15.3 16.6
15.4 21.7 0.06 0.08 0.07
ns/pF ns/pF
CMOS Output Module Timing1 Data High Data Enable High Enable Enable High Enable High Latch Setup Latch Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High Hard-Wired Wide Decode Output 13.7 19.2 0.06 0.05 0.05 11.5 11.5 11.5 12.4 18.2 25.6 0.08 0.07 0.07 15.3 15.3 15.3 16.6 ns/pF ns/pF
Notes: Delays based loading. information found Simultaneously Switching Output Limits Actel FPGAs application note http://www.actel.com/appnotes.
(Wor Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Logic Module Combinatorial Functions tPDD tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tSUENA tHENA tWCLKA tWASYN Internal Array Module Delay Internal Decode Module Delay
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Decode-to-Output Routing Delay
Logic Module Sequential Timing Characteristics Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Setup Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset Output Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
(continued)
(Wor Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Read Cycle Time Write Cycle Time Clock High/Low Time Data Valid After Clock High/Low Address/Data Setup Time Address/Data Hold Time Read Enable Setup Read Enable Hold Write Enable Setup Write Enable Hold Block Enable Setup Block Enable Hold 11.8 11.8
Asynchronous SRAM Operations Asynchronous Access Time Read Address Valid Address/Data Setup Time Address/Data Hold Time Read Enable Setup Address Valid Read Enable Hold Write Enable Setup Write Enable Hold Data Hold Time 11.5 10.6 15.3 14.1
(continued)
(Wor Cond
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA tIRD1 tIRD2 tIRD3 tIRD4 tIRD5 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fHMAX Input Data Input Latch Gate-to-Output Input Latch Hold Input Latch Setup Latch Active Pulse Width
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period (1/fmax) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 11.3 12.5
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Optimization techniques further reduce delays
(continued)
(Worst-Case Military Conditions, 4.5V, 125°C)
`-1' Speed Parameter Description
`Std' Speed Min. Max. Units
Min.
Max.
Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tWDO tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tWDO
Data High Data Enable High Enable Enable High Enable High Latch Output Setup Latch Output Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High Hard-Wired Wide Decode Output
11.5 11.5 11.5 12.3 11.5 16.3 0.04 0.06 0.05
15.3 15.3 15.3 16.5
15.4 21.7 0.06 0.08 0.07
ns/pF ns/pF
CMOS Output Module Timing1 Data High Data Enable High Enable Enable High Enable High Latch Setup Latch Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High Hard-Wired Wide Decode Output 13.7 19.2 0.06 0.05 0.05 11.5 11.5 11.5 12.3 18.2 25.6 0.08 0.07 0.07 15.3 15.3 15.3 16.5 ns/pF ns/pF
Notes: Delays based loading. information found Simultaneously Switching Output Limits Actel FPGAs application note http://www.actel.com/appnotes.
Clock (Input) MODE Mode (Input)
only. Clock input global clock distribution network. Clock input buffered prior clocking logic modules. This also used I/O.
CLKA Clock (Input)
1200XL, 3200DX, only. Clock input global clock distribution networks. Clock input buffered prior clocking logic modules. This also used I/O.
CLKB Clock (Input)
MODE controls diagnostic pins (DCLK, PRA, PRB, SDI). When MODE HIGH, special functions active. When MODE LOW, pins function I/Os. provide debugging capability, MODE should terminated through resistor that MODE pulled high when required.
Connection
This connected circuitry within device.
PRA, Probe (Output)
1200XL, 3200DX, only. Clock input global clock distribution networks. Clock input buffered prior clocking logic modules. This also used I/O.
DCLK Diagnostic Clock (Input)
Clock input diagnostic probe device programming. DCLK active when MODE HIGH. This functions when MODE LOW.
Ground
Probe used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when debugging been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. accessible when MODE HIGH. This functions when MODE LOW.
PRB, Probe (Output)
supply voltage.
HCLK Dedicated (Hard-wired) Array Clock (Input)
only. Clock input sequential modules. This input directly wired each S-module offers clock speeds independent number S-modules being driven. This also used I/O.
Input/Output (Input, Output)
functions input, output, tristate, bi-directional buffer. Input output levels compatible with standard CMOS specifications. 3200DX families, unused I/Os automatically tri-stated. With this configuration, input buffer internal module disabled. 1200XL families, unused I/Os automatically configured bi-directional buffers where each buffer configured driver.
IOCLK Dedicated (Hard-wired) Clock (Input)
Probe used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. accessible when MODE HIGH. This functions when MODE LOW.
Serial Data Input (Input)
Serial data input diagnostic probe device programming. active when MODE HIGH. This functions when MODE LOW.
5.0V Supply Voltage
HIGH supply voltage.
QCLKA/B,C,D Quadrant Clock (Input/Output)
only. Clock input modules. This input directly wired each module offers clock speeds independent number modules being driven. This also used I/O.
IOPCL Dedicated (Hard-wired) Preset/Clear (Input)
3200DX only. These four pins quadrant clock inputs. When used register control signal, these pins function general purpose I/O.
Test Clock
only. input preset clear. This global input directly wired preset clear inputs registers. This functions when preset clear macros used.
Clock signal shift JTAG data into device. This functions when JTAG fuse programmed. JTAG pins only available 3200DX device.
Test Data
Serial data input JTAG instructions data. Data shifted rising edge TCLK. This functions when JTAG fuse programmed. JTAG pins only available 3200DX device.
Test Data
Serial data output JTAG instructions test data. This functions when JTAG fuse programmed. JTAG pins only available 3200DX device.
Test Mode Select
Serial data input JTAG test mode. Data shifted rising edge TCLK. This functions when JTAG fuse programmed. JTAG pins only available 3200DX device.
84-Pin CPGA
Orientation (C3)
Number
A1010B Function PRA, PRB, SDI, DCLK, MODE
A1020B Function PRA, PRB, SDI, DCLK, MODE
Number
A1010B Function CLK,
A1020B Function CLK,
(continued)
132-
132-Pin CPGA
Orientation
132- Number A1240A Function MODE CLKB, CLKA, PRA, SDI, DCLK, PRB, Number A1240A Function Number A1240A Function
(continued)
133-
133-Pin CPGA
Orientation
133- Number A1425A Function PRA, CLKB, SDI, IOCLK, DCLK, CLKA, Number A1425A Function MODE HCLKA, Number A1425A Function PRB, IOPCL,
(continued)
176-
176-Pin CPGA
176- Number A1280A Function CLKA, DCLK, CLKB, SDI, MODE PRA, A1280XL Function CLKA, DCLK, CLKB, SDI, MODE PRA, Number A1280A Function PRB, A1280XL Function PRB,
176- Number A1280A Function A1280XL Function Number A1280A Function A1280XL Function
(continued)
207-
207-Pin CPGA
207- Number A1460A Function SDI, Number A1460A Function MODE DCLK, Number A1460A Function PRA, CLKB, HCLK, CLKA, PRB,
207- Number A1460A Function IOPCL, IOCLK, Number A1460A Function Number A1460A Function
(continued)
257-
257-Pin CPGA
257- Number A14100A Function MODE SDI, Number A14100A Function DCLK, Number A14100A Function PRA, HCLK, PRB,
257- Number A14100A Function CLKA, CLKB, Number A14100A Function IOPCL, IOCLK, Number A14100A Function
(continued)
CQFP
Index
84-Pin CQFP
CQFP
Number
A1020B Function
A32100DX Function MODE (WD) (WD) QCLKA, (WD) (WD) (WD) QCLKB, (WD) (WD) (WD) (WD) SDO,
Number
A1020B Function CLKA, MODE SDI, DCLK, PRA, PRB,
A32100DX Function TCK, SDI, (WD) (WD) (WD) (WD) QCLKD, (WD) (WD) PRA, CLKA, CLKB, PRB, (WD) (WD) QCLKC, (WD) (WD) DCLK,
(continued)
132-
Index
132-Pin CQFP
132- Number A1425A Function SDI, MODE Number A1425A Function PRB, HCLK, IOPCL, Number A1425A Function IOCLK, CLKA, CLKB, PRA, DCLK,
(continued)
172-
Index
172-Pin CQFP
172- Number A1280A Function MODE A1280XL Function MODE Number A1280A Function A1280XL Function
172- Number A1280A Function A1280XL Function Number A1280A Function SDI, PRA, CLKA, CLKB, PRB, DCLK, A1280XL Function SDI, PRA, CLKA, CLKB, PRB, DCLK,
(continued)
196-
Index
196-Pin CQFP
196- Number A1460A Function SDI, MODE Number A1460A Function PRB, HCLK, Number A1460A Function IOPCL,
196- Number A1460A Function IOCLK, Number A1460A Function CLKA, CLKB, PRA, Number A1460A Function DCLK,
(continued)
208-
Index
208-Pin CQFP
208- Number A32100DX Function MODE Number A32100DX Function TMS, TDI, (WD) (WD) QCLKA, (WD) (WD) (WD) (WD) (WD) (WD) Number A32100DX Function QCLKB, (WD) (WD) (WD) (WD) SDO, TCK,
208- Number A32100DX Function Number A32100DX Function SDI, (WD) (WD) (WD) (WD) QCLKD, (WD) (WD) PRA, CLKA, Number A32100DX Function CLKB, PRB, (WD) (WD) (WD) (WD) QCLKC, (WD) (WD) DCLK,
(continued)
256-
Index
256-Pin CQFP
256- Number A14100A Function SDI, MODE A32200DX Function TCK, Number A14100A Function A32200DX Function SDO, (WD) (WD) (WD) (WD) QCLKB, (WD) (WD) Number A14100A Function PRB, HCLK, IOPCL, A32200DX Function (WD) (WD) (WD) (WD) QCLKA, (WD) (WD) TDI, TMS,
256- Number A14100A Function A32200DX Function Number A14100A Function IOCLK, A32200DX Function MODE DCLK, (WD) (WD) QCLKC, (WD) (WD) (WD) (WD) Number A14100A Function CLKA, CLKB, PRA, DCLK, A32200DX Function PRB, CLKB, CLKA, PRA, (WD) (WD) QCLKD, (WD) (WD) (WD) (WD) SDI,
.050" .010" .045 .055
0.18" .002"
.100"
1.100" .020" square
.080" .110"
.120" .140"
1.000
Orientation
Notes: dimensions inches unless otherwise stated. BSC-Basic Spacing between Centers. This theoretical true position dimension tolerance.
(continued)
132-Pin CPGA
.085" .110"
.045 .055 0.18" .002"
.100"
.050" .010" 1.360" .015" square .120" .140"
1.200
Orientation
Notes: dimensions inches unless otherwise stated. BSC-Basic Spacing between Centers. This theoretical true position dimension tolerance.
(continued)
133-
View
0.100" 0.130"
0.045" 0.055" 0.018" 0.002"
0.100"
0.050" 0.010" 1.360" 0.015" square 0.120" 0.140"
1.200"
Side View
Orientation
Bottom View
Notes: dimensions inches unless otherwise stated. BSC-Basic Spacing between Centers. This theoretical true position dimension tolerance.
(continued)
176-
INDEX MARK 0.102" 0.132"
0.100"
0.018" .002"
0.050" .005" 1.570" .015" square 0.120" 0.140"
1.400
Notes: dimensions inches unless otherwise stated. BSC-Basic Spacing between Centers. This theoretical true position dimension tolerance.
(continued)
207-
View
INDEX MARK 0.120" 0.015"
0.100"
0.018" 0.002"
0.05" 0.005"
1.77" 0.010" square
0.180" 0.010" 0.05" 0.005"
Side View
1.600"
Bottom View
Notes: dimensions inches unless otherwise stated. BSC-Basic Spacing between Centers. This theoretical true position dimension tolerance.
(continued)
257-
View
0.105" 0.012"
0.100"
0.018" 0.002"
0.05" 0.005"
1.970" 0.015" square
0.180" 0.010" 0.05" 0.01"
Side View
1.800"
Bottom View
Notes: dimensions inches unless otherwise stated. BSC-Basic Spacing between Centers. This theoretical true position dimension tolerance.
(continued)
CQFP
View
Side View
Notes: Seal ring connected Ground. Lead material Kovar with minimum microinches gold plate over nickel. Packages shipped unformed with ceramic test carrier.
(continued)
132-Pin, 172-Pin, 196-Pin, 208-Pin, 256-Pin CQFP (Cavity
View
Ceramic
Side View
Lead Kovar
Notes: Outside leadframe holes (from dimension circular CQ208 CQ256. Seal ring connected Ground. Lead material Kovar with minimum microinches gold plate over nickel. Packages shipped unformed with ceramic bar. 32200DX CQ208 heat sink back.
CQFP
CQFP Symbol D1/E1 D2/E2 1.595 0.130 Min. 0.070 0.060 0.008 0.004 0.640 Nom. 0.090 0.075 0.010 0.006 0.650 0.500 0.025 0.140 1.460 1.600 1.615 2.485 0.150 0.325 Max. 0.100 0.080 0.012 0.008 0.660 Min. 0.094 0.080 0.007 0.004 0.940
CQFP Nom. 0.105 0.090 0.008 0.006 0.950 0.800 0.025 0.350 2.320 2.140 2.500 2.505 2.485 0.375 0.175 Max. 0.116 0.100 0.010 0.008 0.960 Min. 0.094 0.080 0.007 0.004 1.168
CQFP Nom. 0.105 0.090 0.008 0.006 1.180 1.050 0.025 0.200 2.320 2.140 2.495 2.505 2.485 0.225 0.175 Max. 0.116 0.100 0.010 0.008 1.192 Min. 0.094 0.080 0.007 0.004 1.336
CQFP Nom. 0.105 0.090 0.008 0.006 1.350 1.200 0.025 0.200 2.320 2.140 2.495 2.505 0.225 Max. 0.116 0.100 0.010 0.008 1.364
Note: dimensions inches except CQ208 CQ256, which millimeters. equals Basic Spacing between Centers. This theoretical true position dimension tolerance.
CQFP
CQFP Symbol D1/E1 D2/E2 74.60 7.05 Min. 2.78 2.43 0.18 0.11 28.96 Nom. 3.17 2.79 0.20 0.15 29.21 25.5 0.50 7.75 70.00 65.90 75.00 75.40 74.60 8.45 7.05 Max. 3.56 3.15 0.22 0.17 29.46 Min. 2.28 1.93 0.18 0.11 35.64
CQFP Nom. 2.67 2.29 0.20 0.15 36.00 31.5 0.50 7.75 70.00 65.90 75.00 75.40 8.45 Max. 3.06 2.65 0.22 0.18 36.36
Note: dimensions inches except CQ208 CQ256, which millimeters. equals Basic Spacing between Centers. This theoretical true position dimension tolerance.
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5192641-2/1.00

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