microSPARCTM-IIep DATA SHEET DESCRIPTION microSPARC-IIep 32-
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STP1100BGA
microSPARCTM-IIep
DATA SHEET DESCRIPTION
microSPARC-IIep 32-bit microprocessor highly integrated, high-performance microprocessor. Implementing SPARC Architecture version specification, ideally suited low-cost uniprocessor embedded applications. built with leading edge CMOS technology, with core operating voltage 3.3V optimized power consumption. microSPARC-IIep includes chip: integer unit (IU), floating-point unit (FPU), large separate instruction data caches, 32-entry version reference MMU, programmable DRAM controller, controller, interface, 16-entry IOMMU, flash memory interface support, interrupt controller, timers, internal boundary scan through JTAG interface, power management clock generation capabilities. operating frequencies MHz.
SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
Features
Integrated 32-bit, expansion controller Integrated MByte DRAM controller Built-in MByte flash memory controller SPARC high-performance RISC architecture Support little endian byte ordering 8-window, 136-word register file KByte instruction cache KByte data cache Built-in floating-point unit On-chip memory management unit Operating voltage 3.3V with compatible Integrated power management circuitry IEEE 1149.1 (JTAG) boundary scan test
Benefits
Connection industry-standard expansion High-bandwidth memory controller reduce latency Flash memory interface runs real-time operating systems that loads runs code Compatible with over 10,000 applications existing development tools Handles with ease devices designed machines, along with UNIX® applications Fast interrupt response, procedure calls, program execution Decouples processor operation from slow external memory Supports concurrent execution floating-point integer instructions Support sophisticated operating systems with memory protection virtual addressing Low-power core reduces power consumption supports industry-standard peripherals Consumes minimal power during standby Ease manufacturing tests
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microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
Clock Generator
I-Cache D-Cache Write Buffer entry entry
64-Bit Cache Fill
Flash Memory Interface
Memory Interface 256MByte DRAM
Controller
Address
32-bit 33MHz
Figure microSPARC-IIep Block Diagram
Flash Memory
microSPARC-IIep
loads Local DRAM SIMM Module DRAM SIMM Module DRAM SIMM Module DRAM SIMM Module DRAM SIMMs
Figure Typical microSPARC-IIep System Block Diagram
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TECHNICAL OVERVIEW
Integer Unit (IU)
microSPARC-IIep integer unit executes SPARC integer instructions defined SPARC Architecture Manual version contains registers supporting 8-window registers 8-global registers. numerous high performance features include instruction prefetching, branch folding 5-stage instruction pipeline. supports little- big-endian byte ordering data.
Floating-Point Unit (FPU)
floating-point unit executes single- double-precision floating-point instructions defined SPARC Architecture Manual version traps quad-precision instructions transfers their execution software. contains floating-point core based Meiko design, fast-multiplier, 3-instruction deep instruction queue, 32-bit floating-point registers. floating-point core fast multiplier allow parallel execution floating multiplication (FPMUL) another floating-point instruction while instruction queue support concurrent execution floating-point integer instruction.
Memory Management Unit (MMU)
microSPARC-IIep memory management unit translates 32-bit virtual addresses 31-bit physical address. maps physical address into different address spaces. provides functionalities specified SPARC version Reference implements hardware table-walk. implements 32-entry fully-associative translation lookaside buffer (TLB) provides memory protection contexts.
Instruction Cache
instruction cache KByte, direct-mapped, virtually-indexed, virtually-tagged cache. instruction cache organized lines bytes plus bits. reduce read-miss latency, instruction cache supports cache refill 32-bit words, streaming bypass.
Data Cache
data cache 8-KByte, direct-mapped, virtually-indexed, virtually-tagged cache. Cache write policy supported write-through with write-allocate. data cache organized lines bytes plus bits. data cache provides zero-penalty data accesses cache hits. reduce write latency, data cache contains 4-deep double-word store buffer. reduce read-miss latency, data cache supports cache refill 32-bit words, streaming bypass.
DRAM Interface
microSPARC-IIep DRAM interface supports industry standard fast-page mode DRAM DRAM that support fast-page mode. supports banks memory total MBytes system memory. Each bank memory consisted MBytes, MBytes MBytes. DRAM interface programmable support different memory speeds relative processor frequency. DRAM data bits wide with parity bits, each covering 32-bits data. parity bits disabled. DRAM interface provides programmable DRAM refresh controller that supports CAS-before-RAS refresh.
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Interface
interface complies with industry standard Local Specification version 2.1. provides 32-bit 33MHz interface. features include endian conversion different data byte ordering, Host Satellite mode, dedicated 16-entry translation lookaside buffer (TLB) dedicated transactions, arbiter, clock, reset interrupt handler. Host, microSPARC-IIep performs arbitration, clock, reset interrupt handling. Satellite, microSPARC-IIep relinquishes Host functionalities external Host. Other features supported interface include: Programmed input/output (PIO) transactions between microSPARC-IIep external devices. Host Satellite mode selected input pins during power-up. Programmable configuration external devices (Type Type while under Host mode. Programmable configuration external Host while under Satellite mode. Buffers with matching fill drain rate allow extended burst transfers. Direct transactions between masters slaves. fairness access arbitration protocols: same-level round robin three-level round robin. Direct virtual memory access (DVMA) transactions between masters microSPARC-IIep slave memory interface (referred DVMA) using software-controlled IOTLB generate physical DRAM addresses. Booting from from address selected user. While under standby mode reduce power consumption, interface consumes minimal power support clock generation wake-up when interrupted. 32-bit timers 32-bit timer 64-bit counter available. Interrupt handler supports eight programmable interrupt input/output lines.
Flash Memory Interface
Using industry-standard programming algorithm, microSPARC-IIep flash memory interface compatible with 28FxxxXX flash memory devices. interface programmable latency allow flash memory access time processor clocks. After power-up, default latency interface processor clocks. then programmed have access latency from processor clocks increments processor clocks. flash memory interface supports 16MBytes data. supports both 32-bit 8-bit data accesses selected boot-mode select input pin. microSPARC-IIep pin-selectable boot from flash memory interface address space.
JTAG Test Interface
microSPARC-IIep provides five-wire test access port (TAP) interface support boundary scan clock control. This interface compatible with IEEE 1149.1 specification, IEEE Standard Test Access Port Boundary Scan Architecture. This allows efficient access single chip scan daisy-chain without board-level multiplexing.
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Controller
controller synchronous finite state machine (FSM) which controls sequence operations JTAG test circuitry, response changes JTAG bus. controller asynchronous with respect system clocks, therefore used control clock control logic. implements state states) diagram detailed IEEE 1149.1 specification.
Power Management
microSPARC-IIep detect system inactivity, place itself standby mode reduce power consumption. While standby mode, processor consumes minimal power. However, interface remains active activity will wake processor.
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SIGNAL DESCRIPTIONS
Signals
Signal PCI_CLK[3:0] PCI_RST# AD[31:0] CBE[3:0]# FRAME# IRDY# TRDY# STOP# DEVSEL# PERR# SERR# Type Note Description Clock output pin. Under Host mode, provide clock other devices. Under Satellite mode, signal unconnected. Reset. Under Host mode, provides RESET other devices. Under Satellite mode, signal input. Address Data pins (multiplexed). Command Byte Enables pins (multiplexed). Parity. Even parity across AD[31:0] CBE[3:0]#. Frame. Driven current master indicate beginning duration access. Initiator Ready. Driven master complete current data phase transaction. Target Ready. Driven target complete current data phase transaction. Stop. Request from current target stop current transaction. Device Select. Driven device that decoded address target. Parity Error. System Error. Generates level interrupt (open drain drivers)
These notes apply description tables this section: Note uses clipping reference VDD3. Note uses clipping reference VDD2. Note power driver require external buffer provide sufficient drive. Note Volt tolerant internally biased VSS1 when connected. Note Volt tolerant internally biased VDD1 when connected. Note Bidirectional open-drain driver, requires external pull uses clipping reference VDD2. Note Volt tolerant. Note EXT_CLK1 driven above volts. this signal driven with driver, must clamped externally volts.
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Signals (Continued)
Signal PCI_INT_L[7:0] (IRL_L[3:0]) Type Note Description Interrupt Requests. Sent microSPARC-IIep interrupt controller. internal interrupt controller disabled, interrupt requests triggered software sent external interrupt controller. PCI, interrupt signals should connected following: INTH#: PCI_INT_L[7] INTD#: PCI_INT_L[3] INTG#: PCI_INT_L[6] INTC#: PCI_INT_L[2] INTF#: PCI_INT_L[5] INTB#: PCI_INT_L[1] INTE#: PCI_INT_L[4] INTA#: PCI_INT_L[0] PCI_INT_L[7:4] used volt bus, inputs have potential driving greater than volts external clamping diodes volts required (PCI_INT_L[3:0] internally clipped VDD2). internal interrupt controller disabled, PCI_INT_L[3:0] used function SPARC interrupt request lines (IRL[3:0]) defined SPARC version PCI_REQ[3:0]# Request. Host mode, microSPARC-IIep internal arbiter receives REQ# from other masters. Satellite mode, PCI_REQ#[0] functions Grant signal (SAT_GNT_L) PCI_REQ#[1] functions Initialization Device Select signal (IDSEL). remaining PCI_REQ#[3:2] signals should tied high. PCI_GNT[3:0]# Grant. Host mode, microSPARC-IIep internal arbiter sends GNT# other masters. Satellite mode, PCI_GNT#[0] functions Request signal (SAT_REQ_L).
DRAM Flash Memory Signals
Signal MEMDATA[63:0] MEMPAR[1:0] MEMADDR[11:0] RAS_L[7:0] Type Note Description 64-bit bi-directional memory data accesses DRAM flash memory. [31:0] [7:0] used dependent width flash memory interface. Bi-directional memory data parity pins DRAM only. MEMDATA[31:0] while MEMDATA[63:32]. Parity optional. DRAM Address output pins. Require external buffering provide sufficient drive. DRAM Address Strobe. Eight separate signals support eight banks DRAM. Require external buffering provide sufficient drive. CAS_L[3:0] MWE_L MOE_L SIMM32_SEL ROM_ADDR[23:0] DRAM Column Address Strobes. pairs signals with each pair supporting four banks DRAM. Require external buffering provide sufficient drive. DRAM Write Enable output pin. Require external buffering provide sufficient drive. DRAM Output Enable output pin. Require external buffering provide sufficient drive. DRAM Double-Density SIMM DIMM select. Disables dual-RAS mode under fast-page mode. Flash memory Address (Byte address).
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microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
DRAM Flash Memory Signals (Continued)
Signal ROM_CS_L ROM_OE_L ROM_WE_L Type Note Flash memory Chip Select. Flash memory Output Enable. Flash memory Write Enable. Description
Clock Timing Signals
Signal DIV_CTL[1:0] SP_SEL[2:0] REF_CLOCK EXT_CLK1 Type Note Description These input pins multiplication factor EXT_CLK1 clock input internal processor clock internal system clock shown Table Memory Speed Select. Selects memory interface timing. Refer Table settings. Clock output frequency processor core. Used testing monitoring. External Input Clock While under PLL-bypass mode, EXclusiveOR performed EXT_CLK1 EXT_CLK2 produce processor clock. Otherwise, EXT_CLK1 used produce processor clock using Phase-Locked Loop. External Input Clock While under PLL-bypass mode, EXclusiveOR performed EXT_CLK1 EXT_CLK2 produce processor clock. Otherwise, during power-up, EXT_CLK2 used select Host Satellite mode. Therefore, while bypassed, EXT_CLK2 tied high, microSPARC-IIep functions Satellite mode. microSPARC-IIep functions Host mode default. PLL-bypass mode select. When tied high during power-up, microSPARC-IIep output Phase-Locked Loop used generate processor clock. When tied during power-up, PLL-bypass mode selected processor clock generated using EXclusiveOR EXT_CLK1 EXT_CLK2. PLL_RST until VDD1 2.0V more when power-up.
EXT_CLK2 (MODE select)
PLL_BYP_L
JTAG Signals
Signal JTAG_CK JTAG_MS JTAG_TDI JTAG_TRST_L JTAG_TDO Type Note Clock boundary scan registers. Mode Select. Test Data Input. Test Reset. Test Data Output. Description
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Miscellaneous Signals
Signal INPUT_RESET_L BM_SEL[1:0] Type Note Power-up reset input pin. Boot Mode Select. 32-bit flash memory local memory (cacheable after boot). 8-bit flash memory local memory (cacheable after boot). memory fetch from addresses f000.0000 f0ff.ffff (non-cacheable). memory fetch from addresses fffe.0000 ffff.ffff (non-cacheable). After booting from (BM_SEL[1:0] Flash memory defaults 32-bit flash memory interface. EXT_EVENT_L INT_EVENT_L IIDDTN THERM_D SCAN_MODE PROCMON VDD4, VSS4 VDD2,VDD3 VDD1, VSS1 Input that used stop internal clocks based external trigger. Output that used trigger external events based internal trigger. Reserved test VSS1 normal operation. Reserved test. VDD1 normal operation. Reserved test. VSS1 normal operation Reserved test. VSS1 normal operation. Reserved test. Connect. power/ground. Reference power. Core power/ground. Description
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TIMING CONSIDERATIONS
TABLE Timing Settings DRAM Speeds
Core Frequency Frequency 60ns DRAM DIV_CTL[1:0]=10 SP_SEL[2:0]=010 DIV_CTL[1:0]=01 SP_SEL[2:0]=010
Table DIV_CTL settings Table SP_SEL settings.
TABLE Processor Interface Timing
DIV_CTL[1:0] Multiply Factor EXT_CLK1
TABLE Memory Interface Timing
Number Cycles Signal t_ASC Description (SP_SEL[2:0] reserved) Column address sent before CAS-before-RAS (refresh) t_CAS active (read) active (write) t_CP precharge (read) precharge (write) t_DH, t_WCH, t_DH t_DS, t_WCS, t_DS t_RAS Data, parity hold after Data, parity sent before active (read) active (write) active (refresh) t_RP precharge SP_SEL[2:0] SP_SEL[2:0] SP_SEL[2:0] SP_SEL[2:0] 11.5
timing diagrams Figure through Figure reflect SP_SEL[2:0] operation.
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200ns
programmable latency
150ns
rom_addr
rom_data
rom_cs_l
rom_oe_l
rom_we_l
Gclk
Figure Flash Memory Interface
50ns
100ns
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clk_100M
50ns
100ns
150ns
t_RAD t_RAH t_RC t_RAS t_CSH t_RAC t_RAL t_RCD t_RSH t_RRH t_RPC t_RP t_ASR t_OFF t_CDD t_RCH t_CP t_ASC t_CAS
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
t_CRP t_RP t_ASR ras_l
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t_RCS t_DZC t_ASC cas_l t_AA address we_l t_OZO
t_CAC t_CAS t_CAH t_CLZ
t_OEA oe_l Dout mc_mstb_l
t_OEZ t_ODD
Figure DRAM Read Cycle (100 Clock)
clk_100M
50ns
100ns
150ns
200ns
t_RAD t_RC t_RAS t_CSH t_RCD t_RWL t_RAH t_RSH t_CWL t_CAH t_DS t_WCH t_WCS t_DH t_ASC t_CAS cas_l address t_WP we_l Dout
Figure DRAM Write Cycle (100 Clock)
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
t_CRP t_RP t_ASR ras_l
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t_ASR t_RPC t_RP
t_CP t_ASC
STP1100BGA
50ns 100ns 150ns 200ns 250ns
STP1100BGA
clk_100M t_RWC t_RAS t_RWD t_CSH t_RAC t_RAL t_CRP t_ASR t_RP t_RSH t_RWL t_CAH t_CWD t_ASC t_CWL t_DS t_CAS t_DH t_RCS t_DZC t_AWD t_AA t_OEH t_WP we_l t_OEA t_DZO oe_l Dout t_ODD t_OEZ t_CAC t_CAS t_CLZ t_CP ras_l t_RCD t_RAD t_RAH t_RPC t_RP t_ASR
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cas_l
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
Microsystems, Figure DRAM Read-Modify-Write Cycle (100 Clock)
address
mc_mstb_l
100ns 200ns 300ns t_RCD t_RC t_RASP t_CSH t_RAC t_RAD t_CRP t_RP t_ASR t_RAH t_CPRH ras_l t_RAL t_RSH t_ASR t_RP t_RPC t_RRH
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clk_100M
t_RCS t_ASC t_DZC t_CAC t_CAH t_CAS t_CLZ t_AA we_l t_OEZ t_OEA t_DZO oe_l Dout t_OEA t_ODD t_DZO t_DZO t_OEA t_OEZ t_ODD t_AA t_AA t_PC t_CAC t_DZC t_CAH t_CAS
t_OFF t_CP t_ASC
t_OFF t_CP t_CAH t_PC t_CAC t_ASC t_DZC t_CAS t_AA
t_OFF t_CAH t_CAS t_PC t_RCH t_CAC t_CP t_OFF t_ASC t_CP t_DZC t_CDD
cas_l
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
Microsystems, Figure DRAM Page-Mode Read Cycle (100 Clock)
address
t_DZO t_OEA t_OEZ t_ODD
t_OEZ t_ODD
STP1100BGA
mc_mstb_l
STP1100BGA
clk_100M
50ns
100ns
150ns
200ns
250ns
t_RC t_RASP t_RCD t_CRP t_RP t_ASR ras_l t_DS t_CWL t_WCS t_CAH t_WCH t_CAS t_CP t_ASC t_DH t_RAD t_RAH t_RAL t_RSH t_CPRH t_RPC t_RP t_ASR
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
Microsystems,
t_WCS t_CAH t_ASC t_DS cas_l address
t_PC t_CP
t_WP we_l oe_l Dout mc_mstb_l Figure DRAM Page-Mode Write Cycle (100 Clock)
100ns 200ns 300ns 400ns t_ASR
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clk_100M
t_CRP t_RP ras_l t_DZC t_CAH t_CLZ t_CAS t_CAC t_ASC t_AA we_l t_OEA t_DZO oe_l Dout t_DZO t_OEA t_OEZ t_ODD t_DZO t_OEA t_OEZ t_ODD t_DZO t_OEA t_OEZ t_ODD t_AA t_AA
t_RCD t_CSH t_RAC t_RAD t_RAH
t_RCS t_DZC
t_DZC t_OFF t_CAH t_CAS t_PC t_CAC t_CP t_ASC t_AA
t_DZC t_OFF t_CAH t_CAS t_PC t_CAC t_CP t_ASC
t_OFF t_OFF t_CP t_CAH t_CAS t_PC t_CAC t_CP t_CP t_ASC t_CDD
t_CAS t_PC t_CAC t_RCH t_CP
cas_l
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
Microsystems,
address
t_OEA t_OEZ t_ODD
mc_mstb_l
STP1100BGA
Figure DRAM Read After Page-Mode Read (100 Clock)
100ns 200ns 300ns 400ns
STP1100BGA
clk_100M t_ASR
t_CRP t_RP t_DZC t_CAH t_CAS t_PC t_OFF t_CP t_RCH t_CAC t_ASC t_AA t_OFF t_CP t_CP t_CDD
t_RCD t_CSH t_RAC t_RAD t_RAH
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ras_l
t_CAH t_CLZ t_RCS t_DZC t_CAS t_CAC t_ASC t_AA we_l t_OEA t_DZO oe_l t_DZO t_OEA t_OEZ t_ODD t_DZO t_OEA t_OEZ t_ODD t_DZO t_OEA t_OEZ t_ODD t_AA t_AA
t_DZC t_CAH t_CAS t_OFF t_CP t_PC t_CAC t_ASC
t_DZC t_CAH t_CAS t_OFF t_CP t_PC t_CAC t_ASC
t_PC t_CAS t_CP
cas_l
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
Microsystems, Figure DRAM Write After Page-Mode Read (100 Clock)
address
t_OEZ t_ODD
Dout
mc_mstb_l
clk_100M t_CRP t_RP t_ASR ras_l
50ns
100ns
150ns
200ns
250ns
t_RCD t_RAD t_RAH
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
t_WCS t_ASC t_CAH t_DS cas_l
t_CWL t_WCS t_CAH t_WCH t_CAS t_CP t_PC t_DS t_RCS t_ASC t_DH t_CP t_AA
t_CPA t_CAS t_OFF
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address t_WP we_l t_OEA t_DZO oe_l Dout t_OEZ
STP1100BGA
mc_mstb_l
Figure DRAM Read After Page-Mode Write (100 Clock)
STP1100BGA
clk_100M t_CRP t_RP t_ASR ras_l
50ns
100ns
150ns
200ns
250ns
t_RCD t_RAD t_RAH t_PC t_CP t_DS t_CWL t_WCS t_CAH t_WCH t_CAS t_ASC t_DH t_CP t_ASC t_DS t_CWL t_WCS t_CAS t_CAH t_WCH t_RCS t_DH
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
Microsystems,
t_WCS t_ASC t_CAH t_DS cas_l address
t_WP we_l oe_l Dout mc_mstb_l
Figure DRAM Write After Page-Mode Write (100 Clock)
t_WP
clk_100M
50ns
100ns
150ns
200ns
t_CSR t_RC t_WRP t_RPC t_RP ras_l
Microsystems,
t_WRH t_RAS t_CHR
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
t_RP t_RPC t_CRP
t_OFF t_CDD t_CP cas_l we_l t_OEZ t_ODD oe_l Dout
STP1100BGA
Figure DRAM RAS-Before-CAS Refresh Cycle (100 Clock)
STP1100BGA
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Reference Voltage supply voltage Input voltage (any pin) Input clamp current (any pin) Operating junction temperature Storage temperature Static discharge voltage VDD1 VDD2, VDD3 VDD4 -0.5 2000 Symbol -0.5 Units
Operation device values excess those listed above result degradation destruction device. Extended operation absolute maximum ratings degrade reliability product. voltages defined with respect ground.
TABLE Recommended Operating Conditions:
Parameter Core supply voltage reference voltage MEMDATA voltage supply ground Ground voltage MEMDATA Operating case temperature Symbol VDD1 VDD2 VDD3 VDD4 VSS4 VSS1 3.14 -0.2 -0.2 3.14 3.3/5.0 3.3/5.0 3.47 VDD2 VDD3 3.47 Units
microSPARC-IIep designed with compatible I/O.
Note: following characteristics preliminary reference only.
These electrical specification numbers preliminary, shown reference only subject change.
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TABLE Characteristics (VCC VDD2 VDD3)
Symbol Parameter Input high voltage Input voltage Output high voltage Output voltage Input current Output leakage current Power dissipation VOUT GND, Outputs disabled VDD1, VDD2, VDD3 max,
REF_CLOCK, JTAG_TDO, MEMADDR, RAS_L, CAS_L, MWE_L, MOE_L outputs only. each line PCI_CLK output only. MEMPAR, MEMDATA outputs only.
Conditions
-0.5 -500
Units
TABLE Capacitance
Symbol COUT COUT Parameter Input capacitance (Non-PCI pins) Output capacitance (Non-PCI pins) Bidirectional capacitance (Non-PCI pins) Input capacitance pins Output capacitance pins Bidirectional capacitance pins Units
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EXT_CLK1
SS-CLOCK (Internal)
PCI_CLK
REF_CLOCK
1.4V
1.4V
INPUT SIGNAL 1.4V
1.4V
OUTPUT SIGNAL
Parameter Definitions Required setup time chip input referenced given (clock) edge. Required hold time chip input referenced given (clock) edge. Guaranteed propagation time output referenced given (clock) edge. Guaranteed hold time output referenced given (clock) edge. Guaranteed setup time output referenced next given (clock) edge. Required clock high time. Required clock time. Required clock rise time. Required clock fall time.
Figure Timing Waveforms
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TABLE Characteristics (Input Pins)
Name JTAG_CK Symbol JTAG_MS JTAG_TDI JTAG_TRST_L EXT_CLK1 INPUT_RESET_L EXT_EVENT_L cycles REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ cycles Conditions Reference Edge asynch asynch asynch asynch JTAG_CK+ JTAG_CK+ JTAG_CK+ JTAG_CK+ JTAG_CK+ JTAG_CK+ Unit
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TABLE Characteristics (Input Pins) (Continued)
Name BM_SEL[1:0] PCI_INT_L[7:0] (IRL[3:0]) Symbol PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ cycles Conditions Reference Edge REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ Unit
BIDI's Refer Specification AD[31:0] FRAME# TRDY# IRDY# STOP# DEVSEL# CBE[3:0]# PERR# SERR# Inputs [2]: Refer Specification PCI_REQ_L[3:2] PCI_REQ_L[1] PCI_REQ_L[0]
EXT_CLK1 driven above volts. this driven with driver, must clamped volts. PCI_REQ_L[0] used signal grant (SAT_GNT_L) external arbiter enabled. PCI_REQ_L[1] used signal IDSEL when operating Satellite mode.
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TABLE Characteristics (Bidirectional Output Pins)
Name MEMDATA[31:0] Symbol MEMDATA[63:32] MEMPAR[1:0] ROM_ADDR[23:0] ROM_OE_L ROM_WE_L ROM_CS_L MEMADDR[11:0] RAS_L[7:0]+ RAS_L[7:0]CAS_L[3:0] MWE_L MOE_L INT_EVENT_L Conditions Reference Edge REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCKREF_CLOCKREF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ REF_CLOCK+ Unit
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TABLE Characteristics (Bidirectional Output Pins) (Continued)
Name JTAG_TDO REF_CLOCK Symbol Conditions Reference Edge JTAG_CK+ JTAG_CK+ Unit
BIDI's: Refer Specification AD[31:0] FRAME# TRDY# IRDY# STOP# DEVSEL# CBE[3:0]# PERR# SERR# Outputs: Refer Specification PCI_GNT[3:0]# PCI_CLK[3:0] PCI_RST#
PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+ PCI_CLK+
PCI_CLK+ PCI_CLK+
DRAM interface pins tested with VDD3 5.0V DRAM interface pins tested with VDD3 5.0V PCI_GNT[0] used signal host request external arbiter enabled.
Microsystems,
This Material Copyrighted Respective Manufacturer
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
STP1100BGA
ASSIGNMENTS
Plastic Ball Grid Array (PBGA) Assignment
SIGNAL NAME AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31] MEMDATA[0] MEMDATA[1] MEMDATA[2] MEMDATA[3] MEMDATA[4] MEMDATA[5] MEMDATA[6] MEMDATA[7] MEMDATA[8] MEMDATA[9] MEMDATA[10] MEMDATA[11] MEMDATA[12] MEMDATA[13] MEMDATA[14] MEMDATA[15] MEMDATA[16] BALL SIGNAL NAME MEMDATA[17] MEMDATA[18] MEMDATA[19] MEMDATA[20] MEMDATA[21] MEMDATA[22] MEMDATA[23] MEMDATA[24] MEMDATA[25] MEMDATA[26] MEMDATA[27] MEMDATA[28] MEMDATA[29] MEMDATA[30] MEMDATA[31] MEMDATA[32] MEMDATA[33] MEMDATA[34] MEMDATA[35] MEMDATA[36] MEMDATA[37] MEMDATA[38] MEMDATA[39] MEMDATA[40] MEMDATA[41] MEMDATA[42] MEMDATA[43] MEMDATA[44] MEMDATA[45] MEMDATA[46] MEMDATA[47] MEMDATA[48] MEMDATA[49] MEMDATA[50] MEMDATA[51] MEMDATA[52] MEMDATA[53] MEMDATA[54] MEMDATA[55] MEMDATA[56] MEMDATA[57] MEMDATA[58] MEMDATA[59] MEMDATA[60] MEMDATA[61] MEMDATA[62] MEMDATA[63] MEMPAR[0] MEMPAR[1] BALL SIGNAL NAME BM_SEL[0] BM_SEL[1] CBE[0]# CBE[1]# CBE[2]# CBE[3]# PCI_INT_L[4] PCI_INT_L[5] DEVSEL# DIV_CTL[0] DIV_CTL[1] EXT_CLK1 EXT_CLK2 EXT_EVENT_L FRAME# IIDDTN INPUT_RESET_L INT_EVENT_L IRDY# JTAG_CK JTAG_MS JTAG_TDI JTAG_TDO JTAG_TRST_L SCAN_MODE CAS_L[0] CAS_L[1] CAS_L[2] CAS_L[3] MEMADDR[0] MEMADDR[1] MEMADDR[2] MEMADDR[3] MEMADDR[4] MEMADDR[5] MEMADDR[6] MEMADDR[7] MEMADDR[8] MEMADDR[9] MEMADDR[10] MEMADDR[11] MOE_L MWE_L RAS_L[0] RAS_L[1] RAS_L[2] RAS_L[3] RAS_L[4] RAS_L[5] BALL SIGNAL NAME RAS_L[6] RAS_L[7] PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_GNT[0]# PCI_GNT[1]# PCI_GNT[2]# PCI_GNT[3]# PCI_INT_L[0] PCI_INT_L[1] PCI_INT_L[2] PCI_INT_L[3] PCI_REQ[0]# PCI_REQ[1]# PCI_REQ[2]# PCI_REQ[3]# PCI_RST# PERR# PLL_BYP_L PLL_RST PLL_VDD (VDD4) PLL_VSS (VSS4) PROCMON REF_CLOCK ROM_ADDR[0] ROM_ADDR[1] ROM_ADDR[2] ROM_ADDR[3] ROM_ADDR[4] ROM_ADDR[5] ROM_ADDR[6] ROM_ADDR[7] ROM_ADDR[8] ROM_ADDR[9] ROM_ADDR[10] ROM_ADDR[11] ROM_ADDR[12] ROM_ADDR[13] ROM_ADDR[14] ROM_ADDR[15] ROM_ADDR[16] ROM_ADDR[17] ROM_ADDR[18] ROM_ADDR[19] ROM_ADDR[20] ROM_ADDR[21] BALL VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 SIGNAL NAME ROM_ADDR[22] ROM_ADDR[23] ROM_CS_L ROM_OE_L ROM_WE_L SERR# SIMM32_SEL SP_SEL[0] SP_SEL[1] SP_SEL[2] PCI_INT_L[6] STOP# THERM_D TRDY# PCI_INT_L[7] BALL SIGNAL NAME VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 BALL
STP1100BGA JEDEC level moisture sensitive will shipped packed. JEDEC standards should apply handling.
Microsystems,
This Material Copyrighted Respective Manufacturer
STP1100BGA
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
PACKAGE DIMENSIONS
272-Pin Package
Seating Plane (Note 0.15 -C0.75 ±0.15 (Note
1.27
2.33 ±0.21 1.17 ±0.08
27.00 24.00 ±1.00 16.10
1.27
Index Area
(Bottom View)
0.56 ±0.06 272x 0.60 ±0.10
(Top View)
Notes: Dimensions Measured maximum solder ball diameter parallel primary datum Primary datum seating plane defined spherical crowns solder balls.
Microsystems,
This Material Copyrighted Respective Manufacturer
microSPARCTM-IIep SPARC 32-Bit Microprocessor With PCI/DRAM Interfaces
STP1100BGA
ORDERING INFORMATION
Part Number STP1100BGA-100 Speeds Description SPARC 32-bit microprocessor with PCI/DRAM interfaces.
Document Part Number: 802-7327-05
Microsystems,
This Material Copyrighted Respective Manufacturer
STP1100BGA
Microsystems, Inc. Antonio Road Palo Alto, 94303-4900 Telephone: 960-1300 Fax: 969-9131 Internet: www.sun.com/microelectronics
©1997 Microsystems, Inc. Rights reserved. INFORMATION CONTAINED THIS DOCUMENT PROVIDED WITHOUT EXPRESS REPRESENTATIONS WARRANTIES. ADDITION, MICROSYSTEMS, INC. DISCLAIMS IMPLIED REPRESENTATIONS WARRANTIES, INCLUDING WARRANTY MERCHANTABILITY, FITNESS PARTICULAR PURPOSE, NON-INFRINGEMENT THIRD PARTY INTELLECTURAL PROPERTY RIGHTS. This document contains proprietary information Microsystems, Inc. under license from third parties. part this document reproduced form means transferred third party without prior written consent Microsystems, Inc. Sun, Microsystems Logo trademarks registered trademarks Microsystems, Inc. United States other countries. SPARC trademarks based upon architecture developed Microsystems, Inc. information contained this document designed intended on-line control aircraft, aircraft navigation aircraft communications; design, construction, operation maintenance nuclear facility. disclaims express implied warranty fitness such uses.
Part Number: 802-7327-05
This Material Copyrighted Respective Manufacturer
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