Changes accordance with 5962-R023-92. Changes accordance with 5962-R18

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REVISIONS DESCRIPTION Technical changes were made table Editorial changes throughout.
Changes accordance with 5962-R023-92. Changes accordance with 5962-R189-93. devices Editorial changes throughout. Changes accordance with 5962-R001-01. Update boilerplate requirements MIL-PRF-38535. Editorial changes throughout.
DATE (YR-MO-DA) 90-08-15
91-10-30 93-07-07 94-11-26 00-12-21 01-12-03
APPROVED William Heckman
Monica L.Poelking Dupay Monica L.Poelking Thomas Hess Thomas Hess
ORIGINAL FIRST SHEET THIS DRAWING BEEN REPLACED.
SHEET SHEET STATUS SHEETS SHEET PMIC PREPARED
STANDARD MICROCIRCUIT DRAWING
THIS DRAWING AVAILABLE DEPARTMENTS AGENCIES DEPARTMENT DEFENSE
CHECKED APPROVED William K.Heckman DRAWING APPROVAL DATE 89-02-16 REVISION LEVEL SIZE
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 http://www.dscc.dla.mil
MICROCIRCUIT, DIGITAL, CMOS, 16-BIT MICROPROCESSOR, MONOLITHIC SILICON
CAGE CODE
AMSC
SHEET
67268
5962-88501
DSCC FORM 2233 DISTRIBUTION STATEMENT Approved public release; distribution unlimited.
5962-E094-02
SCOPE Scope. This drawing describes device requirements MIL-STD-883 compliant, non-JAN class level microcircuits accordance with MIL-PRF-38535, appendix Part Identifying Number (PIN). complete shown following example: 5962-88501
Drawing number
Device type (see 1.2.1)
Case outline (see 1.2.2)
Lead finish (see 1.2.3)
1.2.1 Device type(s). device type(s) identify circuit function follows: Device type Generic number M80C186 M80C186 M80C186XL M80C186XL M80C186XL M80C186XL Frequency 12.5 12.5 Circuit function 16-bit CHMOS microprocessor 16-bit CHMOS microprocessor 16-bit CHMOS microprocessor 16-bit CHMOS microprocessor 16-bit CHMOS microprocessor 16-bit CHMOS microprocessor
1.2.2 Case outline(s). case outline(s) designated MIL-STD-1835 follows: Outline letter Descriptive designator figure CMGA3-P68 Terminals Package style Ceramic quad package grid array package
1.2.3 Lead finish. lead finish specified MIL-PRF-38535, appendix Absolute maximum ratings. Voltage (referenced GND). Maximum power dissipation (PD) Storage temperature range Thermal resistance, junction-to-case (JC): Case Case Junction temperature (TJ). Lead temperature (soldering, seconds) Recommended operating conditions. Supply voltage range (VCC): Device types Device types Frequency operation: Device type Device type Device type Device type Device type Device type Case operating temperature range (TC) 4.75 5.25 12.5 12.5 -55°C +125°C -1.0 +7.0 -65°C +150°C 13°C/W MIL-STD-1835 +150°C +260°C
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APPLICABLE DOCUMENTS Government specification, standards, handbooks. following specification, standards, handbooks form part this drawing extent specified herein. Unless otherwise specified, issues these documents those listed issue Department Defense Index Specifications Standards (DoDISS) supplement thereto, cited solicitation. SPECIFICATION DEPARTMENT DEFENSE MIL-PRF-38535 Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT DEFENSE MIL-STD-883 MIL-STD-1835 HANDBOOKS DEPARTMENT DEFENSE MIL-HDBK-103 MIL-HDBK-780 List Standard Microcircuit Drawings. Standard Microcircuit Drawings. Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines.
(Unless otherwise indicated, copies specification, standards, handbooks available from Standardization Document Order Desk, Robbins Avenue, Building Philadelphia, 19111-5094.) Order precedence. event conflict between text this drawing references cited herein, text this drawing takes precedence. Nothing this document, however, supersedes applicable laws regulations unless specific exemption been obtained. REQUIREMENTS Item requirements. individual item requirements shall accordance with MIL-PRF-38535, appendix non-JAN class level devices specified herein. Product built this drawing that produced Qualified Manufacturer Listing (QML) certified qualified manufacturer manufacturer been granted transitional certification MIL-PRF-38535 processed product accordance with manufacturers approved program plan qualifying activity approval accordance with MIL-PRF-38535. This flow documented Quality Management (QM) plan make modifications requirements herein. These modifications shall affect form, fit, function device. These modifications shall affect described herein. "QML" certification mark accordance with MIL-PRF-38535 required identify when flow option used. This drawing been modified allow manufacturer alternate die/fabrication requirements paragraph A.3.2.2 MIL-PRF-38535 other alternative approved Qualifying Activity. Design, construction, physical dimensions. design, construction, physical dimensions shall specified MIL-PRF-38535, appendix herein. 3.2.1 Case outlines. case outlines shall accordance with 1.2.2 figure herein. 3.2.2 Terminal connections. terminal connections shall specified figure 3.2.3 Functional block diagram. functional block diagram shall specified figure 3.2.4 Timing waveforms. timing waveforms shall specified figure
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Electrical performance characteristics. Unless otherwise specified herein, electrical performance characteristics specified table shall apply over full case operating temperature range. Electrical test requirements. electrical test requirements shall subgroups specified table electrical tests each subgroup described table Marking. Marking shall accordance with MIL-PRF-38535, appendix part shall marked with listed herein. addition, manufacturer's also marked listed MIL-HDBK-103 (see herein). packages where marking entire number feasible space limitations, manufacturer option marking "5962-" device. 3.5.1 Certification/compliance mark. compliance indicator shall marked non-JAN devices built compliance MIL-PRF-38535, appendix compliance indicator shall replaced with "QML" certification mark accordance with MIL-PRF-38535 identify when flow option used. product built accordance with A.3.2.2 MIL-PRF-38535, modified manufacturer's plan, "QD" certification mark shall used place "QML" certification mark. Certificate compliance. certificate compliance shall required from manufacturer order listed approved source supply MIL-HDBK-103 (see herein). certificate compliance submitted DSCC-VA prior listing approved source supply shall affirm that manufacturer's product meets requirements MIL-PRF-38535, appendix requirements herein. Certificate conformance. certificate conformance required MIL-PRF-38535, appendix shall provided with each microcircuits delivered this drawing. Notification change. Notification change DSCC-VA shall required accordance with MIL-PRF-38535, appendix Verification review. DSCC, DSCC's agent, acquiring activity retain option review manufacturer's facility applicable required documentation. Offshore documentation shall made available onshore option reviewer. QUALITY ASSURANCE PROVISIONS Sampling inspection. Sampling inspection procedures shall accordance with MIL-PRF-38535, appendix Screening. Screening shall accordance with method 5004 MIL-STD-883, shall conducted devices prior quality conformance inspection. following additional criteria shall apply: Burn-in test, method 1015 MIL-STD-883. Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1015 MIL-STD-883. +125°C, minimum. Interim final electrical test parameters shall specified table herein, except interim electrical parameter tests prior burn-in optional discretion manufacturer.
Quality conformance inspection. Quality conformance inspection shall accordance with method 5005 MIL-STD-883 including groups inspections. following additional criteria shall apply.
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TABLE Electrical performance characteristics. Test Symbol Conditions -55°C +125°C unless otherwise specified Device type 03-06 High level input voltage, High level input voltage, ARDY/SRDY level output voltage VIH3 other outputs -200 0.8VCC -200 -2.4 Power supply current 0.2VCC +1.3 VCC+0.5 0.45 VIH2 Group subgroups Limits -0.5 0.2VCC +1.1 0.2VCC +0.9 0.2VCC -0.3 VCC+0.5 VCC+0.5 VCC+0.5 Unit
level input voltage, except High level input voltage, except
VIH1
High level output voltage
03-06
0.8VCC VCC-0.5
Input leakage current Output leakage current level clock output voltage High level clock output voltage level clock input voltage (X1) High level clock input voltage (X1) footnotes table.
VCLO
0.45 0.45 VOUT ICLO
03-06
0.45
VCHO
ICHO -500
03-06
0.8VCC VCC-0.5
VCLI VCHI
-0.5
+0.6 VCC+0.5
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C unless otherwise specified 4.3.1c 4.3.1d tDVCL figure Device type Group subgroups Limits 04-06 Data hold (A/D) tCLDX 03-06 Unit
Input capacitance capacitance Functional test Data set-up (A/D)
ARDY resolution transition set-up time
tARYCH
04-06
Asynchronous ready (ARDY) set-up time
tARYLCL
04-06
ARDY active hold time
tCLARX
04-06
ARDY inactive hold time
tARYCHL
04-06
Synchronous ready (SRDY) transition set-up time
tSRYCL
04-06
SRDY transition hold time
tCLSRY
04-06
Hold set-up
tHVCL
04-06
footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C unless otherwise specified figure Device type 04-06 DRQ0, DRQ1 set-up time tINVCL 04-06 Address valid delay tCLAV Address hold tCLAX 03-06 Address float delay tCLAZ 03-04 Command lines float delay tCHCZ Command lines valid delay (after float) tCHCV footnotes table. Group subgroups Limits tCLAX tCLAX tCLAX tCLAX tCLAX Unit
INTX, NMI, TEST TMRIN set-up time
tINVCH
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C unless otherwise specified figure Device type 03-06 active delay tCHLH 03-04 inactive delay tCHLL 03-04 Address hold inactive tLLAX figure Equal loading figure Data valid delay tCLDV figure 04-06 Data hold time tCLDOX Data hold after (min) tWHDX figure Equal loading figure 04-05 footnotes table. tCHCL-20 tCHCL-15 tCHCL-10 tCHCL-15 tCLCL-34 tCLCL-20 tCLCL-15 tCLCL-20 tCLCL-34 Group subgroups Limits tCLCL-30 tCLCL-15 Unit
width
tLHLL
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C unless otherwise specified figure Equal loading figure tWHLH figure Equal loading figure Control active delay tCVCTV figure Device type 03-06 03-06 Control active delay tCHCTV Control inactive delay tCVCTX
inactive delay (nonwrite cycle)
Group subgroups
Limits tCLCH-10 tCLCH-10
Unit
inactive inactive
tWHDEX
inactive high
tCLCH-14 tCLCH-14
tCVDEX
footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C unless otherwise specified figure Device type
inactive delay
Group subgroups
Limits
Unit
Address float active
active delay
tAZRL tCLRL
tCLRH
inactive high
tRHLH
figure Equal loading figure
03-06
tCLCH-14 tCLCH-14
inactive address active (min)
tRHAV
figure
tCLCL-40 tCLCL-20 tCLCL-15
Equal loading figure HLDA valid delay tCLHAV figure
03-06
pulse width (min)
tRLRH
04-05
2tCLCL-46 2tCLCL-40 2tCLCL-20 2tCLCL-25 2tCLCL-30
footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C unless otherwise specified figure Device type 04-05 Address valid (min) tAVLL figure Equal loading figure 04-05 Status active delay tCHSV figure Status inactive delay tCLSH Timer output delay tCLTMV maximum figure figure Group subgroups Limits 2tCLCL-34 2tCLCL-30 2tCLCL-20 2tCLCL-25 2tCLCL-30 tCLCH-19 tCLCH-15 tCLCH-10 tCLCH-15 tCLCH-18 Unit
pulse width (min)
tWLWH
footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C unless otherwise specified figure Device type Queue status delay tCHQSV 01-02 set-up Status hold time Address valid clock high LOCK valid/invalid delay tRESIN tCHDX tAVCH tCLLV 03-06 01-02
inactive
Group subgroups
Limits
Unit
Reset delay
tCLR0
tDXDL
figure Equal loading figure
03-06
Chip-select active delay
tCLCSV
figure
footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C unless otherwise specified figure Equal loading figure tCHCSX figure Device type 03-06 CLKIN period tCKIN
valid clock high
Group subgroups
Limits tCLCH-10 tCLCH-10
Unit
Chip-select hold from command inactive
tCXCSX
Chip-select inactive delay
1000 1000
31.25
tRVCH tCSVLL tCKHL tCKLH tCLCK figure figure figure
tCLCH-14
Chip select valid CLKIN fall time CLKIN rise time CLKIN time
footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C unless otherwise specified figure Device type CLKIN CLKOUT skew tCICO figure 03-04 CLKOUT period tCLCL CLKOUT time tCLCH figure 03-05 CLKOUT high time tCHCL 03-05 CLKOUT rise time tCH1CH2 figure 04-06 CLKOUT fall time tCL2CL1 figure 04-06 footnotes next sheet. 62.5 0.5tCLCL-8 0.5tCLCL-7 0.5tCLCL-5 0.5tCLCL-6 0.5tCLCL-8 0.5tCLCL-7 0.5tCLCL-5 0.5tCLCL-6 Group subgroups Limits 2000 2000 Unit
CLKIN high time
tCHCK
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TABLE Electrical performance characteristics Continued. device types ±10% device types through timings measured loading CLKOUT unless specified. device type outputs measured with MHz). device type (12.5 MHz). device types through outputs test conditions with unless noted. tests, input 0.45 except where figure Guaranteed tested limits specified. Power save current (IPS) +25°C with typically Current measured with device RESET with driven other nonpower pins open. Pins being floated during HOLD invoking ONCE mode. guarantee recognition next CLK. Voltages indicated refer voltage measurements waveforms figure tCLCK tCHCK (CLKIN high times) should have duration less than percent tCKIN.
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Case
FIGURE Case outline.
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Case Symbol .066 .050 .080 .016 .040 .030 .005 .008 1.640 .935 Inches .106 .020 .060 .040 .020 .012 1.870 .970 Millimeters 2.03 0.41 1.02 0.76 0.13 0.20 41.66 23.75 2.69 0.51 1.52 1.02 0.51 0.31 47.50 24.64
.800 .050 .375 .040 .087 .450 .060
20.32 1.27 9.53 1.02 1.68 1.27 2.21 11.43 1.52
FIGURE Case outline Continued.
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Device type Case outline Terminal number Terminal symbol AD12 AD13 AD14 AD15 A16/S3 A17/S4 A18/S5 A19/S6
/QS1 QSMD
Terminal number Terminal symbol HLDA HOLD SRDY LOCK TEST INT0 INT1 INT2/ INTA0 INT3/ INTA1
Terminal number
Terminal symbol PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 DRQ1 DRQ0 AD10 AD11
ALE/QS0 RESET CLKOUT ARDY
MCS0 MCS1 MCS2 MCS3 PCS6
FIGURE Terminal connections.
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Device type Case outline Terminal number Terminal symbol A16/S3 A18/S5
QSMD
Terminal number Terminal symbol SRDY AD13 LOCK TEST AD12 INT0 AD11 INT1 AD10 INT2/ INTA0 INT3/ INTA1
Terminal number
Terminal symbol MCS0 MCS1 DRQ1 PCS0 PCS1 PCS3 PCS5 MCS2 MCS3 DRQ0 PCS2 PCS4 PCS6
CLKOUT AD15 A17/S4 A19/S6
/QS1
ALE/QS0 RESET ARDY HLDA AD14 HOLD
FIGURE Terminal connections Continued.
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Device types
FIGURE Functional block diagram.
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Device types
FIGURE Functional block diagram Continued.
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FIGURE Timing waveforms.
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NOTES: Following write cycle, local floated devices only when devices enter "hold acknowledge" state. INTA occurs clock later slave mode. Status inactive just prior Latched have same timings PCS5 PCS6 write cycle followed read.
FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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TABLE Electrical test requirements. MIL-STD-883 test requirements Subgroups accordance with MIL-STD-883, method 5005, table -1*,
Interim electrical parameters (method 5004 5010) Final electrical test parameters (method 5004 5010) Group test requirements (method 5005 5010) Groups end-point electrical parameters (method 5005 5010) Additional electrical subgroups group periodic inspections applies subgroup 4.3.1 Group inspection. Tests shall specified table herein.
Subgroups table method 5005 MIL-STD-883 shall omitted. Subgroup (CIN COUT measurements) shall measured only initial test after process design changes which affect capacitance. minimum sample size devices with zero rejects shall required. Subgroups shall include verification instruction (see table III).
4.3.2 Groups inspections. End-point electrical parameters shall specified table herein. Steady-state life test conditions, method 1005 MIL-STD-883. Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1005 MIL-STD-883. +125°C, minimum. Test duration: 1,000 hours, except permitted method 1005 MIL-STD-883.
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PACKAGING Packaging requirements. requirements packaging shall accordance with MIL-PRF-38535, appendix NOTES Intended use. Microcircuits conforming this drawing intended Government microcircuit applications (original equipment), design applications, logistics purposes. Replaceability. Microcircuits covered this drawing will replace same generic device covered contractor-prepared specification drawing. Configuration control SMD's. proposed changes existing SMD's will coordinated with users record individual documents. This coordination will accomplished using Form 1692, Engineering Change Proposal. Record users. Military industrial users shall inform Defense Supply Center Columbus when system application requires configuration control applicable SMD. DSCC will maintain record users this list will used coordination distribution changes drawings. Users drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. Comments. Comments this drawing should directed DSCC-VA, Columbus, Ohio 43216-5000, telephone (614) 692-0547. Abbreviations, symbols, definitions. abbreviations, symbols, definitions used herein defined MIL-PRF-38535, MIL-HDBK-1331, table herein. Approved sources supply. Approved sources supply listed MIL-HDBK-103. vendors listed MIL-HDBK-103 have agreed this drawing certificate compliance (see herein) been submitted accepted DSCC-VA.
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TABLE III. Instruction summary. Function DATA TRANSFER Move: Register register/memory Register/memory register Immediate register/memory Immediate register Memory accumulator Accumulator memory Register/memory segment register Segment register register/memory PUSH Push: Memory Register Segment register Immediate PUSHA Push Pop: Memory Register Segment register POPA XCHG Exchange: Register/memory with register Register with accumulator Input from: Fixed port Variable port Output Fixed port Variable port 1110011w 1110111w port 1110010w 1110110w port 1000011w mode 4/17 10001111 01100000 (reg mode 11111111 011010s0 01100000 data data mode 10001110 2/11 1000100w 1000101w 1000111w 1010000w 1010001w 10001110 data addr-low addr-low data data addr-high addr-high data 2/12 12-13 8/16-bit 8/16-bit Format Clock cycles Comments
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TABLE III. Instruction summary Continued. Function DATA TRANSFER Continued XLAT Translate byte Load register Load pointer Load pointer LAHF Load with flags SAHF Store into flags PUSHF Push flags POPF flags SEGMENT Segment override: ARITHMETIC Add: Reg/memory with register either Immediate register/memory Immediate accumulator with carry: Reg/memory with register either Immediate register/memory Immediate accumulator Increment: Register/memory Register 1111111w 3/15 100000sw 0001010w data data data data 4/16 8/16-bit 000100dw 3/10 100000sw 0000010w data data data data 4/16 8/16-bit 000000dw 3/10 00101110 00110110 00111110 00100110 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101 (mod (mod Format Clock cycles Comments
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TABLE III. Instruction summary Continued. Function ARITHMETIC Continued Subtract: Reg/memory register either Immediate from register/memory Immediate from accumulator Subtract with borrow: Reg/memory register either Immediate from register/memory Immediate from accumulator Decrement: Register/memory Register Compare: Register/memory with register Register with register/memory Immediate with register/memory Immediate with accumulator Change sign register/memory ASCII adjust Decimal adjust ASCII adjust subtract Decimal adjust subtract Multiply (unsigned): Register-Byte Register-Word Memory-Byte Memory-Word 1111011w 26-28 35-37 32-34 41-43 00110111 00100111 00111111 00101111 0011101w 0011100w 100000sw 001111 1111011w data data data data 3/10 3/10 3/10 3/10 8/16-bit 1111111w 3/15 100000sw 0001110w data data data data 4/16 8/16-bit 000110dw 3/10 100000sw 0010110w data data data data 4/16 8/16-bit 001010dw 3/10 Format Clock cycles Comments
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TABLE III. Instruction summary Continued. Function ARITHMETIC Continued IMUL Integer multiply (signed): Register-Byte Register-Word Memory-Byte Memory-Word IMUL Integer immediate multiply (signed): Divide (unsigned): Register-Byte Register-Word Memory-Byte Memory-Word IDIV Integer divide (signed): Register-Byte Register-Word Memory-Byte Memory-Word ASCII adjust multiply ASCII adjust divide Convert byte word Convert word double word LOGIC Shift/Rotate instructions: Register/memory Register/memory Register/memory count 1101000w 1101001w 1100000w instruction SHL/SAL count 2/15 5+n/17+n 5+n/17+n 11010100 11010101 10011000 10011001 00001010 00001010 1111011w 44-52 53-61 50-58 59-67 1111011w 011010s1 data data 1111011w 25-28 34-37 31-34 40-43 22-25/ 29-32 Format Clock cycles Comments
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TABLE III. Instruction summary Continued. Function LOGIC Continued And: Reg/memory register either Immediate register/memory Immediate accumulator TEST function flags, result: Register/memory register Immediate data register/memory Immediate data accumulator Reg/memory register either Immediate register/memory Immediate accumulator Exclusive Reg/memory register either Immediate register/memory Immediate accumulator Invert register/memory STRING MANIPULATION MOVS Move byte/word CMPS Compare byte/word SCAS Scan byte/word LODS Load byte/wd ALAX STOS Store byte/wd from Input byte/wd from port OUTS Output byte/wd port 0110111w 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 001100dw 1000000w 0011010w 1111011w data data data data 3/10 4/16 3/10 8/16-bit 000010dw 1000000w 0000110w data data data data 3/10 4/16 8/16-bit 1000010w 1111011w 1010100w data data data data 3/10 4/10 8/16-bit 001000dw 1000000w 0010010w data data data data 3/10 4/16 8/16-bit Format Clock cycles Comments
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TABLE III. Instruction summary Continued. Function STRING MANIPULATION Continued Repeated count MOVS Move string CMPS Compare string SCAS Scan string LODS Load string STOS Store string Input string OUTS Output string CONTROL TRANSFER CALL Call: Direct within segment Register/memory indirect within segment Direct intersegment 10011010 segment offset segment selector Indirect intersegment Unconditional jump: Short/long Direct within segment Register/memory indirect within segment Direct intersegment 11101010 segment offset segment selector Indirect intersegment Return from call: Within segment Within adding immed Intersegment Intersegment adding immediate 11000011 11000010 11001011 11001010 data-low data-high data-low data-high 11111111 (mod 11101011 11101001 11111111 disp-low disp-low disp-high 11/17 11111111 (mod 11101000 11111111 disp-low disp-high 13/19 11110010 1111001z 1111001z 11110010 11110010 11110010 11110010 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 8+8n 5+22n 5+15n 6+11n 6+9n 8+8n 8+8n Format Clock cycles Comments
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TABLE III. Instruction summary Continued. Function CONTROL TRANSFER Continued JE/JZ Jump equal/zero JL/JNGE Jump less/not greater equal JLE/JNG Jump less equal/not greater JB/JNAE Jump below/not above equal JBE/JNA Jump below equal/not above JP/JPE Jump parity/parity even Jump overflow Jump sign JNE/JNZ Jump equal/ zero JNL/JGE Jump less/greater equal JNLE/JG Jump less equal/greater JNB/JAE Jump below/above equal JNBE/JA Jump below equal/above JNP/JPO Jump par/par Jump overflow Jump sign JCXZ Jump zero LOOP Loop times LOOPZ/LOOPE Loop while zero/equal LOOPNZ/LOOPNE Loop while zero/equal ENTER Enter procedure LEAVE Leave procedure Interrupt: Type specified Type INTO Interrupt overflow 11001101 11001100 11001110 type 48/4 INT. taken/if INT. taken 11001001 01110100 01111100 01111110 01110010 01110110 01111010 01110000 01111000 01110101 01111101 01111111 01110011 01110111 01111011 01110001 01111001 11100011 11100010 11100001 11100000 11001000 disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp data-low data-high 22+16(n-1) 4/13 4/13 4/13 4/13 4/13 4/13 4/13 4/13 4/13 4/13 4/13 4/13 4/13 4/13 4/13 4/13 5/15 6/16 6/16 6/16 LOOP taken/LOOP taken taken/JMP taken Format Clock cycles Comments
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TABLE III. Instruction summary Continued. Function CONTROL TRANSFER Continued IRET Interrupt return BOUND Detect value range PROCESSOR CONTROL Clear carry Complement carry carry Clear direction direction Clear interrupt interrupt Halt WAIT Wait LOCK lock prefix Processor extension escape 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11110000 11011TTT test 11001111 01100010 33-35 Format Clock cycles Comments
(TTT opcode processor extension)
NOTES: effective address (EA) memory operand computed according fields: then treated field then DISP disp-low disp-high absent then DISP disp-low sign-extended 16-bits, disp-high absent then DISP disp-high: disp-low then (BX) (SI) DISP then (BX) (DI) DISP then (BP) (SI) DISP then (BP) (DI) DISP then (SI) DISP
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TABLE III. Instruction summary Continued. then (DI) DISP then (BP) DISP* then (BX) DISP DISP follows
byte instruction (before data required)
Except then disp-high: disp-low. calculation time clock cycles modes, included execution times given whenever appropriate. Segment override prefix assigned according folowing: assigned according following table: 16-Bit 8-Bit Segment Register
physical addresses operands addressed register computed using segment register. physical addresses destination operands string primitive operations (those addressed register) computed using segment, which overridden.
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TABLE description. Symbol RESET System power: volt power supply. System ground. Reset output indicates that device being reset, used system reset. active HIGH, synchronized with processor clock, lasts integer number clock periods corresponding length signal. Reset goes inactive clockout periods after goes inactive. When tied TEST /BUSY pin, Reset forces devices into enhanced mode. Crystal inputs, provide external connections fundamental mode third overtone parallel resonant crystal internal oscillator. interface external clock instead crystal. this case, minimize capacitance drive with complemented input oscillator frequency internally divided generate clock signal (CLKOUT). Clock output provides system with percent duty cycle waveform. device timings specified relative CLKOUT. CLKOUT sufficient drive capabilities numeric processor extension. System reset causes device immediately terminate present activity, clear internal logic, enter dormant state. This signal asynchronous device clock. device begins fetching instructions approximately 61/2 clock cycles after returned HIGH. proper initialization, must within specifications clock signal must stable more than clocks with held low. internally synchronized. This input provided with Schmitt-trigger facilitate power-on generation network. When occurs, device will drive status lines inactive level clock, then float them. TEST /BUSY TEST sampled during after reset determine whether device enter compatible enhanced mode. Enhanced mode requires TEST high rising edge four clocks later. other combination will place device compatible mode. weak internal pullup insures high state when driven. TEST compatible mode, this configured operate TEST This examined WAIT instruction. TEST input high when WAIT execution begins, instruction execution will suspend. TEST will resampled every five clocks until goes low, which time execution will resume. interrupts enabled while device waiting TEST interrupts will serviced. BUSY, enhanced mode, this configured operate BUSY. BUSY input used notify device numerics processor extension activity. Floating point instructions executing device sample BUSY determine when numeric processor ready accept coninand. BUSY active high. DRQ0, DRQ1 Timer inputs used either clock control signals, depending upon programmed timer mode. These inputs active high low-to-high transitions counted) internally synchronized. Timer outputs used provide single pulse continuous waveform generation, depending upon timer mode selected. request driven high external device when desires that (channel perform transfer. These signals active high, level-triggered, internally synchronized. Name Function
CLKOUT
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TABLE description Continued. Symbol Name Function Nonmaskable interrupt edge-triggered input which causes type interrupt. maskable internally. transition from high initiates interrupt next instruction boundary. latched internally. duration clock more will guarantee service. This input internally synchronized. Maskable interrupt requests requested activating these pins. When configured inputs, these pins active high. Interrupt requests synchronized internally. INT2 INT3 configured software provide active-low interrupt-acknowledge output signals. interrupt inputs configured software either edge- level-triggered. ensure recognition, interrupt requests must remain active until interrupt acknowledged. When slave mode selected, function these pins changes. Address outputs (16-19) cycle status (3-6) reflect four most significant address bits during These signals active high. During status information available these lines encoded below: Processor cycle High cycle
INT0, INT1, INT2/ INTA0 INT3/ INTA1
A19/S6, A18/S5, A17/S4, A16/S3
defined during T2-T4. AD15 Address/data (0-15) signals constitute time multiplexed memory address (T1) data (T2. bus. active high analogous lower byte data bus, pins through during when byte transferred onto lower portion memory operations.
(bus high enable) signal analogous that used enable data most significant half data bus, pins D15-D8. will during when upper byte transferred will remain through does need latched. will float during hold reset. enhanced mode, will also used signify DRAM refresh cycles. refresh cycle indicated being high.
encodings value
value Word tranfer
Function
Byte transfer upper half data (D15-D8) Byte transfer lower half data (D7-D0) Refresh
ALE/QS0
Address latch enable/queue status provided device latch address. active high. Addresses guaranteed valid trailing edge ALE. rising edge generated rising edge CLKOUT immediately preceding associated cycle. trailing edge generated CLKOUT rising edge Note that never floated.
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TABLE description Continued. Symbol
/QS1
Name Function Write strobe/queue status indicates that data written into memory device. active write cycle. active low, floats during "HOLD" "Reset". driven high clock during reset, then floated. When device queue status mode, ALE/QS0 /QS1 pins provide information about processor instruction queue interaction. Queue operation queue operation First opcode byte fetched from queue Subsequent byte fetched from queue Empty queue
QSMD
Read strobe indicates that device performing memory read cycle. active read cycle. guaranteed until after address floated. active low, floats during "HOLD". driven high clock during reset, then output driver floated. weak internal pull-up mechanism line holds high when line driven. During RESET sampled determine whether device should provide ALE, queue-status should provided. should connected provide queue-status data.
ARDY
Asynchronous ready informs device that addressed memory space device will complete data transfer. ARDY input will accept asynchronous input, active high. Only rising edge internally synchronized device. This means that falling edge ARDY must synchronized device clock. connected VCC, WAIT states inserted. Asynchronous ready (ARDY) synchronous ready (SRDY) must active terminate cycle. unused, this line should tied yield control SRDY pin. Synchronous ready must synchronized externally device. SRDY provides relaxed system-timing specification ready input. This accomplished eliminating one-half clock cycle which required internally resolving signal level when using ARDY input. This line active high. this line connected VCC, WAIT states inserted. Asynchronous ready (ARDY) synchronous ready (SRDY) must active before cycle terminated. unused, this line should tied yield control ARDY pin. LOCK output indicates that other system masters gain control system while LOCK active low. LOCK signal requested LOCK prefix instruction activated beginning first data cycle associated with instruction following LOCK prefix. remains active until completion instruction following LOCK prefix. prefetches will occur while LOCK asserted. LOCK active driven high clock during RESET. LOCK devices 03-06 stay high during reset, while floated devices.
SRDY
LOCK
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TABLE description Continued. Symbol Name Function cycle status encoded provide bus-transaction information. Queue operation Interrupt acknowledge Read Write Halt Instruction fetch Read data from memory Write data memory Passive cycle)
status pins float during "HOLD/HLDA". used logical indicator, indicator. status lines driven high clock during reset, then floated until cycle begins. HOLD (input) HLDA (output) HOLD indicates that another master requesting local bus. HOLD input active high. HOLD asynchronous with respect device clock. device will issue HLDA (high) response HOLD request Simultaneous with issuance HLDA device will float local control lines. After HOLD detected being LOW, device will lower HLDA. When device needs another cycle, will again drive local control lines. enhanced mode, HLDA will when DRAM refresh cycle pending device external master control bus. will external master relinquish lowering HOLD that device execute refresh cycle. Lowering HOLD four clocks returning high will insure only refresh cycle external master. HLDA will immediately active after refresh cycle taken place. Upper memory chip select active output whenever memory reference made defined upper portion (1K-256K block) memory. This line floated during HOLD. address range activating software programmable. sampled upon rising edge both pins held low, device will enter ONCE mode. ONCE mode pins assume high impedance state remain until subsequent RESET. weak internal pullup normal operation. Lower memory chip select active whenever memory reference made defined lower portion (1K-256K block) memory. This line floated during HOLD. address range activating software programmable. sampled upon rising edge both pins held low, device will enter ONCE mode. ONCE mode pins assume high impedance state remain until subsequent RESET. weak internal pullup normal operation.
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TABLE description Continued. Symbol MCS0 /PEREQ MCS1/ ERROR MCS2 MCS3 enhanced mode, MCS0 becomes PEREQ input (processor extension request). When connected numerics processor extension, this input used signal device when make numeric data transfers from NPX. MCS3 becomes (numeric processor select) which only activated communication numeric processor extension. MCS1 becomes ERROR enhanced mode used signal numeric coprocessor errors. PCS0 PCS1 PCS5 Peripheral chip select signals active when reference made defined peripheral area (64K byte space). These lines floated during HOLD. address ranges activating PCS0 software programmable. Peripheral chip select latched programmed provide sixth peripheral chip select, provide internally latched signal. address range activating PCS5 software programmable. When programmed provide latched rather than PCS5 this will retain previously latched value during HOLD. active high. PCS6 Peripheral chip select latched programmed provide seventh peripheral chip select, provide internally latched signal. address range activating PCS6 software progranmiable. When programmed provide latched rather than PCS6 this will retain previously latched value during HOLD. active HIGH.
Name Function Mid-range memory chip select signals active when memory reference made defined mid-range portion memory (8K-512K). These lines floated during HOLD. address ranges activating MCS0 software programmable.
Data transmit/receive controls direction data flow through external data transceiver. When low, data transferred device. When high, device places write data data bus. Data enable provided data transceiver output enable. active during each memory access. high whenever changes state.
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STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 01-12-03 Approved sources supply 5962-88501 listed below immediate acquisition information only shall added MIL-HDBK-103 QML-38535 during next revision. MIL-HDBK-103 QML-38535 will revised include addition deletion sources. vendors listed below have agreed this drawing certificate compliance been submitted accepted DSCC-VA. This bulletin superseded next dated revision MIL-HDBK-103 QML-38535.
Standard microcircuit drawing 5962-8850101ZA 5962-8850101ZC 5962-8850101YA 5962-8850101YC 5962-8850102ZA 5962-8850102ZC 5962-8850102YA 5962-8850102YC 5962-8850103ZA 5962-8850104ZA 5962-8850105ZA 5962-8850106ZA
Vendor CAGE number 3V146 3V146 3V146 3V146 3V146 3V146 3V146 3V146
Vendor similar MG80C186-10/BZA MG80C186-10/BZC MQ80C186-10/BYA MQ80C186-10/BYC MG80C186-12/BZA MG80C186-12/BZC MQ80C186-12/BYA MQ80C186-12/BYC MG80C186XL-20/B MG80C186XL-16/B MG80C186XL-12/B MG80C186XL-10/B
lead finish shown each representing hermetic package most readily available from manufacturer listed that part. desired lead finish listed contact vendor determine availability. Caution. this number item acquisition. Items acquired this number satisfy performance requirements this drawing. longer available from approved source supply.
Vendor CAGE number 63V146
Vendor name address Rochester Electronics Inc. Malcolm Hoyt Drive Newburyport, 01950
information contained herein disseminated convenience only Government assumes liability whatsoever inaccuracies information bulletin.

Changes accordance with 5962-R023-92. Changes accordance with 5962-R18

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