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Alpha 21066 Alpha 21066A Microprocessors Data Sheet
Order Number: EC-QC4HB-TE Revision/Update Information: This document supersedes Alpha 21066/21066A Microprocessors Data Sheet (EC-QC4HA-TE).
Digital Equipment Corporation Maynard, Massachusetts
December 1995 While Digital believes information included this publication correct date publication, subject change without notice. Digital Equipment Corporation makes representations that products manner described this publication will infringe existing future patent rights, descriptions contained this publication imply granting licenses make, use, sell equipment software accordance with description. Digital Equipment Corporation 1995. Printed U.S.A. rights reserved.
AlphaGeneration, DECchip, Digital, Digital Semiconductor, VAX, DOCUMENT, AlphaGeneration design mark, DIGITAL logo trademarks Digital Equipment Corporation. Digital Semiconductor Digital Equipment Corporation business. IEEE registered trademark Institute Electrical Electronic Engineers, Inc. GRAFOIL registered trademark Union Carbide Corporation. other trademarks registered trademarks property their respective owners.
This document prepared using DOCUMENT Version 2.1.
Contents
1.10 3.5.1 Microarchitecture Overview Instruction Fetch Decode Unit Integer Execution Unit Load Store Unit Floating-Point Unit Pipeline Organization Internal Cache Organization Memory Controller Controller Obtaining Additional Information Pinout Signal List Signal Descriptions Quick Reference Signals Function Direction Electrical Specifications Electrical Specification Conformance Absolute Maximum Ratings Supply Current Power Dissipation Chip Power Supply Sequencing Specifications Operating Specifications Specifications Mechanical Specifications Thermal Specifications Operating Temperature Thermal Resistance Register Summary Instruction Summary
Figures
21066 Block Diagram Instruction Pipelines Timing Measurement 21066/21066A Package-Top Side 21066/21066A Package-Bottom
Tables
Signal List Signal Description Signals Function Signals Direction Absolute Maximum Ratings Characteristics 21066 Parameters 21066A Parameters Clock Reset Parameters Memory Controller Parameters Parameters Specifications Signaling JTAG Parameters Miscellaneous Parameters Maximum Various Frequencies 2hs0a Various Airflows 21066-Specific Internal Processor Registers Memory Controller Registers Controller Registers Memory Integer Load Store Instructions Integer Control Instructions Integer Arithmetic Instructions Logical Shift Instructions Byte-Manipulation Instructions Memory Format Floating-Point Instructions Floating-Point Branch Instructions Floating-Point Operate Instructions
Miscellaneous Instructions Compatibility Instructions Required PALmode Instructions Architecturally Reserved PALmode Instructions
Microarchitecture
Note This Data Sheet describes Digital's Alpha 21066 Alpha 21066A microprocessors. Except where differences detailed specifically, what described 21066 holds true 21066A.
21066 microprocessor implements Digital's Alpha architecture. following sections provide overview chip's architecture major functional units. Figure block diagram 21066 microprocessor.
Overview
21066 microprocessor consists core central processing unit (CPU), memory controller, controller (IOC). 21066 also contains instruction data caches (Icache Dcache) serial read-only memory (SROM) interface. peripheral component interconnect (PCI) interface between peripheral devices system memory. compatible with Local Specification, Revision 2.0. memory controller interfaces system memory optional, external, backup cache (Bcache). also contains embedded graphics accelerator. SROM interface provides initialization data load path from SROM Icache. Following initialization, this interface converted diagnostic port through privileged architecture library code (PALcode). interface unit connects CPU, memory controller, IOC, SROM interface. consists 64-bit bidirectional data bus, address bus, invalidate address bus, reset logic, control. instruction fetch decode unit (IDU) CPU's central control unit. issues instructions, maintains pipeline, performs program counter (PC) calculations. also contains four independent execution units: Integer execution unit (IEU) Load store unit (LSU) Floating-point unit (FPU)
Figure 21066 Block Diagram
Instruction Cache (Icache) Branch History Table Data Interface Unit Instruction Fetch/Decode Unit (IDU) Prefetcher Resource Conflict Calculation Pipeline Control Floating-Point Execution Unit (FPU) Multiplier/ Adder Pipeline Divider Memory Controller Addr/Data Data Path Backup Cache Controller Floating-Point Register File (FRF) Graphics Accelerator Controller (IOC) Addr/Data Queue Scatter-Gather Load Silo SROM Debug Port Data Cache (Dcache) Data SROM Data SROM Clock Interrupts Clock Generator Clock Address, RAS, Backup Cache Memory Data/ECC
Integer Execution Unit (IEU) Multiplier Shifter Adder Logic
Integer Register File (IRF)
Control Address/Data
Load/Store Unit (LSU) Write Buffer Address Generator
Branch unit
Each unit accepts more than instruction cycle; however, correctly scheduled code issue instructions independent units single cycle.
Instruction Fetch Decode Unit
primary function issue instructions IEU, LSU, FPU. contains: Prefetcher pipeline instruction translation buffers (ITBs) Abort logic Register conflict dirty logic Exception logic Internal processor registers (IPRs)
Instruction Fetch Decode decodes instructions parallel checks that required resources available both instructions, follows: resources available, both instructions issued. resources available only second instruction, neither instruction issued. issues only first pair instructions, does advance another instruction attempt another dual issue; dual issue attempted only aligned quadword (8-byte) pairs.
Branch Prediction branch unit, prediction logic, also part IDU. microprocessor offers register-selectable choice branch prediction strategies. Each instruction location instruction cache (Icache) includes single history record outcome branch instructions. This information used predict result when branch instruction next executed. 21066A supports improved branch prediction scheme that uses 2-bit history table. table indexed same bits that index Icache. Each 2-bit table entry behaves counter that increments branches taken (stopping decrements branches not-taken (stopping 00). upper counter set, branch predicted taken. contents table disturbed Icache fills. 21066A also supports static branch-prediction mode that uses sign branch displacement 21066).
Translation Buffers includes fully associative ITBs: 8-entry, small-page 8-KB pages. 4-entry, large-page that supports 4-MB (512 pages.
Both translation buffers store recently used, instruction stream (Istream) page table entries (PTEs) not-last-used replacement algorithm. addition, both ITBs support register-enabled extension called superpage. superpage mappings provide one-to-one virtual <33:13> physical <33:13> translation when virtual address bits <42:41> Interrupts exception logic supports three sources interrupts: Hardware interrupts There three level-sensitive hardware interrupts sourced pins irq<2:0>. There internally generated interrupts that respond external interface error conditions. These sourced registers memory controller IOC.
Software interrupts There prioritized software interrupts, sourced onchip register. Asynchronous system traps (ASTs) There four ASTs, each processor mode: user, supervisor, executive, kernel. These traps sourced onchip register.
interrupt mechanism provides flexible, software-controlled priority scheme that implemented PALcode operating system. interrupts independently masked onchip enable registers. addition, interrupts qualified current processor mode. Performance Monitoring onchip performance recording mechanism counts various hardware events causes interrupt upon counter overflow. counters provided allow accurate comparison variables under potentially nonrepeatable, experimental conditions. events counted include: Instruction issues Nonissues Total cycles
Pipeline Pipeline freeze Cache misses Counts various instruction classes
addition, external interface events, such direct memory access (DMA) transactions external cache accesses, counted programming memory controller register.
Integer Execution Unit
integer execution unit (IEU) contains 64-bit integer execution data path, which includes following: Adder Logic Barrel shifter Byte zapper Bypassers Integer multiplier
also contains 32-entry, 64-bit integer register file (IRF). four read ports write ports simultaneously read operands write operands (results) from integer execution data path load store unit (LSU).
Load Store Unit
contains four major sections: Address translation data path, which includes data translation buffer (DTB) Load silo Write buffer Internal processor registers (IPRs)
Address Translation Data Path address translation data path displacement adder that generates effective virtual address load store instructions, that generates corresponding physical address.
Data Translation Buffer 32-entry, fully associative stores recently used, data stream (Dstream) page table entries (PTEs). supports four page-size granularity options (also called granularity hints) that allow aligned group pages treated single larger page. also supports register-enabled superpage extension. superpage mappings provide virtual-to-physical address translation regions virtual address space: first region enables superpage mapping when virtual address (VA) bits <42:41> this mode, entire physical address space mapped multiple times quadrant virtual address space defined <42:41> second region maps 30-bit region total physical address space, defined physical address (PA) bits <33:30> into single corresponding region virtual address space defined <42:30> 1FFE.
Load Silos contains memory reference pipeline that accept load store instruction every cycle until Dcache fill required. Instructions issued pipeline stage result each Dcache lookup known until pipeline stage Therefore, there instructions pipeline behind load instruction that misses Dcache. These instructions handled follows: Loads that Dcache allowed complete (hit-under-miss). Loads that miss placed silo replayed sequence after first load miss completes. Store instructions presented Dcache their normal time, with respect pipeline. They placed silo presented write buffer sequence, with respect loads that miss.
Write Buffer write buffer purposes: 21066 generate store data faster than backup cache (Bcache) subsystem accept data. This cause stall cycles. write buffer provides finite, high-bandwidth resource receiving store data minimize number possible stall cycles.
write buffer also attempts aggregate store data into aligned, 32-byte cache blocks maximize rate which 21066 write data into Bcache.
21066A implements revised write buffer unload logic, removing rare possibility that write operations buffered indefinitely.
Floating-Point Unit
onchip, pipelined floating-point unit (FPU) execute both IEEE floating-point instructions. 21066 supports IEEE S_floating T_floating data types, with rounding modes (except round infinity, which provided software). 21066 fully supports F_floating G_floating data types, provides limited support D_floating format. contains: 32-entry, 64-bit floating-point register file (FRF) user-accessible control register
accept instruction every cycle, with exception floating-point divide instructions. latency data-dependent, nondivide instructions cycles. 21066 supports IEEE floating-point operations defined Alpha architecture. Support complete implementation IEEE Standard Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754-1985) provided combination hardware software. 21066A includes floating-point divide hardware that implements nonrestoring, normalizing, variable-shift (maximum bits cycle) algorithm that retires average bits cycle. average overall divide latency, including pipeline overhead, cycles double precision cycles single precision (compared cycles, respectively, previous implementations). Additionally, avoid noncompliant (IEEE) divide behavior previous implementations, divider calculates inexact flag, setting inexact (INE) floating-point control register (FPCR) appropriate, trapping DIVx/SI instructions only when result really inexact.1 inexact trap disable (INED) also been added FPCR.
Alpha Architecture Reference Manual more information about FPCR.
Pipeline Organization
21066 7-stage pipeline integer operate memory reference instructions, 10-stage pipeline floating-point operate instructions. maintains state pipeline stages, track outstanding register write operations determine Icache hits misses. Figure shows integer operate, memory reference, floating-point operate pipelines IDU, IEU, LSU, FPU. first four stages pipelines same, executed IDU. last stages unit specific. units have bypassers that allow results instruction operand following instruction, without writing results first instruction register file. Figure Instruction Pipelines
Instruction Fetch Swap Dual-Issue Instruction/Branch Prediction Decode Register File Access/Issue Check Integer Operate Pipeline
Computation Cycle computes Computation Cycle Lookup Integer Register File Write/Icache Miss
Memory Reference Pipeline
calculates effective Dstream address Lookup Dcache Miss Load Data Register File Write Pipeline
Floating-Point Pipeline
Floating-Point Calculate Pipeline Floating-Point Register File Write Pipeline
Internal Cache Organization
21066 includes onchip caches-a Dcache Icache. memory cells both caches fully static, 6-transistor, CMOS structures. Data Cache 8-KB Dcache write-through, direct-mapped, read-allocate, physical cache with 32-byte blocks. When device writes cacheable memory, Dcache block corresponding memory address invalid. 21066A maintains longword cache parity Dcache. Instruction Cache 8-KB Icache physical direct-mapped cache. Each Icache block (line) contains: Istream data bytes) Associated bits) Address space number (ASN) field bits) Address space match (ASM) field bit) Branch history (BHT) field bits 21066, bits 21066A)
Icache does contain hardware maintaining coherency with memory, unaffected write operations memory. 21066A maintains longword cache parity Icache.
Memory Controller
onchip memory controller interfaces system memory optional backup cache (Bcache). several memory-mapped control status registers (CSRs) program organization, timing, size DRAM, VRAM, Bcache SRAM. controls requests requests (from IOC) from memory Bcache. also controls VRAM shift-register loads memory refresh operations. memory controller decodes address request determine whether request memory IOC. handles access memory controller CSRs, memory, Bcache. request directed IOC, memory controller passes control IOC. memory controller also perform following graphics operations: Dumb frame buffer operation Transparent stipple operation Write-per-bit plane masking
Byte write operations (with external gating) Full split VRAM shift-register load instructions
Controller
onchip controller (IOC) interface bridge between peripheral devices system memory. interface protocol complies with Local Specification, Revision 2.0. peripheral devices 21066-based system communicate with system memory through IOC. Peripheral chips that compliant connected directly 21066 without glue logic. runs asynchronously CPU, using clock input. incorporates scatter-gather mapping logic translate 32-bit addresses generated masters 34-bit physical address space. implements 8-entry translation lookaside buffer (TLB) fast translations. programmable address windows control peripheral device access system memory.
1.10 Obtaining Additional Information
obtain more information about 21066 21066A microprocessors, Alpha architecture instruction set, PCI, Technical Support Ordering Information section this manual.
Pinout
Sections through list external signals their associated pins, describe external signals, list signals according function.
Signal List
Table lists signal associated with each pin. Table Signal List
Signal (Index point) gnt_l lock_l bc_tag4 bc_idx_tag1 Signal ad12 ad11 perr_l devsel_l trdy_l c_be_l3 c_be_l0 bc_cs_l bc_tag7 bc_tag5 bc_tag2 bc_tag0 bc_parity bc_idx_tag3 mem_addr0 mem_addr3 Signal ad17 ad14 pci_clk_in ad10 req_l frame_l stop_l irdy_l c_be_l1 bc_oe_l bc_tag6 bc_tag3 bc_dirty bc_idx_tag0 bc_idx_tag2 bc_idx_tag4 mem_addr1 (continued next page)
Table (Cont.) Signal List
Signal ad16 instr_ref ad13 rst_l c_be_l2 bc_we_l bc_tag1 bc_index mem_addr2 mem_addr4 Signal ad18 ad15 mem_addr5 mem_addr6 mem_addr9 ad23 ad21 ad19 mem_addr7 mem_addr10 ad24 ad22 ad20 mem_addr8 mem_addr11 mem_cas_l ad26 ad25 Signal mem_wr_oe_l mem_write_l mem_rd_oe ad29 ad28 ad27 mem_data0 mem_data1 mem_data32 ad31 ad30 mem_data2 mem_data3 mem_data4 mem_data34 mem_data33 mem_data5 mem_data6 mem_data7 (continued next page)
Table (Cont.) Signal List
Signal mem_data35 mem_data36 mem_data37 mem_data9 mem_data8 mem_data38 mem_data39 mem_data40 mem_data12 mem_data11 mem_data10 mem_data41 mem_data42 mem_data15 mem_data14 mem_data13 mem_data43 mem_data44 mem_data45 Signal mem_data17 mem_data16 mem_data46 mem_data47 mem_data51 mem_data22 mem_data20 mem_data18 mem_data48 mem_data50 mem_data23 mem_data21 mem_data19 mem_data49 mem_data52 mem_data54 mem_data26 mem_data24 Signal mem_data53 mem_data57 mem_data60 pll_filter irq1 mem_dsf mem_ecc1 mem_data31 mem_data29 mem_data25
(continued next page)
Table (Cont.) Signal List
Signal mem_data56 mem_data59 mem_data62 pll_clk_in pll_clk_in_l pll_bypass test_clk_out sromoe_l irq0 trst_l vrefresh_l mem_rasa_l3 mem_rasa_l0 mem_rasb_l2 mem_ecc0 mem_ecc2 mem_ecc5 mem_ecc7 mem_data28 mem_data27 AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 Signal mem_data55 mem_data58 mem_data61 pll_i_ref pll_5v sromd sromclk memreq_l memack_l mem_dtoe_l vframe_l mem_rasa_l2 mem_rasa_l1 mem_rasb_l1 mem_rasb_l0 mem_ecc3 mem_ecc4 mem_data30 AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Signal mem_data63 reset_in_l irq2 mem_rasb_l3 mem_ecc6
Signal Descriptions
Table describes function each external signal alphabetical order. Table Signal Description
Signal ad<31:0> Type Description Multiplexed address data. byte address driven during first clock transaction, data driven during subsequent clock cycles. Bcache SRAM chip select. SRAMs enabled only when this signal asserted. This signal provides power-saving feature when Bcache being accessed. Indicates status data stored cache block. value indicates that cache memory contain same data; value indicates that cache contains more recently written data than memory (that memory data stale). same timing characteristics bc_tag<7:0>. index bit, depending Bcache size. When signal index bit, output. When signal bit, signal direction depends cycle type-during cache fill write operation, signal output; during cache lookup, signal input. Transmits Bcache index cache. Bcache output enable signal. Transmits Bcache parity array during cache fill write operations, from array during cache lookups. same timing characteristics bc_tag<7:0>. Represent upper part physical address stored cache block. During Bcache lookup operation, cache drives these bits (and possibly bc_idx_tag<4:0>) with that corresponds current index being driven mem_addr<11:0>, bc_index, nontag bits bc_idx_tag<4:0>. During Bcache fill write operation, memory controller drives most significant address bits these lines, stored Bcache array. Bcache write-enable signal. Multiplexed command codes byte enables. command code driven during address cycle transaction, inverted byte enables driven during data cycles. (continued next page)
bc_cs_l
bc_dirty
bc_idx_tag<4:0>
bc_index bc_oe_l bc_parity
bc_tag<7:0>
bc_we_l c_be_l<3:0>
Table (Cont.) Signal Description
Signal devsel_l frame_l Type Description Asserted device that addressed current transaction. Asserted beginning transaction. also controls number data transfers during transaction (burst length). deasserted during final data phase transaction. Asserted external arbitration logic when granted ownership PCI. arbiter expected park (default grant) when other device requesting ownership. During normal operation, this signal indicates type current access (instruction data) memory data bus. When high, this signal indicates Istream reference; when low, this signal indicates Dstream reference. During reset, internal clock output this test purposes. irdy_l Asserted initiator transaction indicate that complete current data phase transaction. During read cycle, this signal asserted indicate that initiator ready accept read data. During write cycle, this signal asserted indicate that initiator driving valid write data onto ad<31:0>. current data phase completes when both trdy_l irdy_l asserted when sampled. External interrupt requests. During reset, these pins part clock system tristated receive power-up values (through external resistors tied Vdd) that frequency ratio between internal clock external reference clock. lock_l Implements atomic (exclusive) access operations PCI. test mode, this signal used test 24-bit retry timeout counter chip tester. This test mode selected programming JTAG instruction register (IR) During test mode, when this signal high, selects lower half counter testing; when this signal selects upper half counter testing. memack_l This sideband signal synchronous with pci_clk_in. asserts this signal when arbitration (internal 21066) access memory requested memreq_l. This signal remains asserted until memreq_l deasserted. (continued next page)
gnt_l
instr_ref
irq<2:0>
Table (Cont.) Signal Description
Signal mem_addr<11:0> Type Description Transmit column address memory least significant index bits Bcache. memory read write operations (that refresh operations), signals mem_ addr<11:0> contain valid address when mem_ras_l3 asserted, contain valid column address when mem_cas_l asserted. When asserted during memory read write operations, this signal indicates that mem_addr<11:0>, mem_data<63:0> (for write operations), mem_write_l contain valid information. During memory refresh cycle, this signal asserted before mem_ras_l3 asserted. mem_data<63:0> Transmit data between memory controller either memory Bcache. Memory optional transceiver, mem_rd_oe mem_wr_oe_l) drives these signals during read operation from memory, when mem_cas_l mem_rd_oe asserted mem_write_l asserted. Bcache drives these signals during read operation from Bcache, when bc_oe_l asserted. memory controller drives these signals during write operation. Data valid when either bc_we_l mem_cas_l, mem_wr_oe_l, mem_write_l asserted. During write-per-bit operation, memory controller drives these signals with write-per-bit mask. Data valid when mem_ras_l3 mem_wr_oe_l, mem_write_l asserted. mem_dsf Selects full split VRAM shift-register load function. This special function signal valid before mem_ras_l3 asserted when mem_dtoe_l asserted.
mem_cas_l
term mem_ras_l represents mem_rasa_l<3:0> mem_rasb_l<3:0> signals selected bank.
(continued next page)
Table (Cont.) Signal Description
Signal mem_dtoe_l Type Description Controls memory output enable function VRAM shiftregister load function. normal memory operations, this multifunction signal deasserted when mem_ras_l3 asserted. During read cycle, this signal asserted before mem_cas_l asserted enable memory data output drivers. indicate VRAM shift-register load sequence, this signal asserted before mem_ras_l asserted. value mem_dsf determines whether full split VRAM shift-register load sequence performed. mem_ecc<7:0> Transmit error correction codes (ECC) between memory controller either memory Bcache. memory controller generates write operations checks read operations. These signals have same external timing mem_data<63:0>. (Memory storage optional, checking disabled using bank configuration registers.) These signals also transmit write byte mask banks that have byte write enabled bank configuration register (external logic required gate DRAM write signals). When used this way, mem_ecc0 corresponds mem_data<7:0>, mem_ecc1 corresponds mem_data<15:8>, mem_rasa_l<3:0>, mem_rasb_l<3:0> Each pair these signals associated with bank memory. During normal read write operations, assertion mem_ ras_l3 indicates that mem_addr<11:0> contains valid address. Which asserted depends following: Which memory bank addressed Whether split bank enabled bank configuration register address
During memory refresh cycle, refresh enable set, eight these signals asserted together. Refresh cycles CAS-before-RAS type. During VRAM shift-register load functions, mem_rasa_ln mem_rasb_ln bank asserted.
term mem_ras_l represents mem_rasa_l<3:0> mem_rasb_l<3:0> signals selected bank.
(continued next page)
Table (Cont.) Signal Description
Signal mem_rd_oe Type Description Enables optional, external, memory transceiver drive data from memory parts onto mem_data<63:0> mem_ecc<7:0>. asserted during read cycles when mem_cas_l asserted. This signal should ignored transceiver used. This sideband signal synchronous with pci_clk_in. When samples this signal asserted, arbitrates (internal 21066) access memory. When arbitration memory been won, asserts memack_l. Provides read write control memory enables loading write-per-bit mask. write operations, mem_write_l asserted before mem_cas_l asserted; read operations, mem_write_l deasserted before mem_cas_l asserted. write-per-bit function activated when mem_write_l asserted before mem_ras_l3 Enables optional, external, memory transceiver drive data from mem_data<63:0> mem_ecc<7:0> memory parts. asserted during write cycles when mem_data<63:0> driven. This should ignored transceiver used. This signal even parity ad<31:0> c_be_l<3:0>. Provides timing transactions PCI. IOC's signals except rst_l synchronous with this signal. Inputs sampled outputs change state result rising edge this signal. This signal asserted when data parity error been detected. Asserted when external clock input pll_clk_in directly drives internal logic, internal clock external reference frequencies equal. normal operation, low-speed (less than MHz), single-ended clock appropriate reference bias voltage supplied pll_clk_in pll_clk_in_l, respectively. minimize jitter induced module package noise, highspeed (greater than MHz) differential reference clock (logically complementary, nominal square waves) supplied pll_clk_in pll_clk_in_l.
memreq_l
mem_write_l
mem_wr_oe_l
pci_clk_in
perr_l pll_bypass
pll_clk_in, pll_clk_in_l
term mem_ras_l represents mem_rasa_l<3:0> mem_rasb_l<3:0> signals selected bank.
(continued next page)
Table (Cont.) Signal Description
Signal pll_filter Type Description capacitor connected between this signal maintains stable operation setting correct feedback-loop time constant. time constant regulates speed with which phasedlocked loop (PLL) responds changes frequency operating conditions. constant current flowing resistor connected between this signal reference analog circuits. reduces variations speed CMOS devices over wide range process operating conditions. This clean +5-V signal regulated internally source nominal +3.3 used associated logic. This onchip isolation necessary reduce phase jitter. Connect decoupling capacitors close possible this pins. Asserted when needs initiate transfer. External arbitration logic required. Master reset input 21066; should asserted when power first applied chip. When asserted, certain internal chip logic immediately initialized (some internal state reset must handled software when chip boots). Internal chip activity starts cycles after reset_in_l negated synchronism with internal clock. reset signal generated CPU. soft reset register allows this signal asserted under software control. This signal automatically asserted when reset_in_l asserted. SROM clock signal when sromoe_l asserted. When sromoe_l asserted, this software-controlled serial port output data. SROM data when sromoe_l asserted. When sromoe_l asserted, this software-controlled serial port input data. Asserted after reset_in_l asserted, enables SROM initialization. Following initialization, this signal deasserted, enabling SROM port used software-controlled serial port. target transaction drives this signal request that initiator stop current transaction. JTAG boundary scan clock. JTAG serial boundary scan data-in signal. (continued next page)
pll_i_ref
pll_5v
req_l reset_in_l
rst_l
sromclk sromd sromoe_l
stop_l
Table (Cont.) Signal Description
Signal test_clk_out Type Description JTAG serial boundary scan data-out signal. output reference clock used only testing 21066. rising edge into 40-pF load nominally coincides with start internal microcycle. relationship between this signal pll_clk_in determined following second negation reset_in_l after power turned clock frequency ratio changed. This should used drive module-level logic. 21066A, when pll_bypass test_clk_out internal clock divided when pll_bypass test_clk_out imitates internal clock. trdy_l JTAG test mode select signal. Asserted target transaction indicate that complete current data phase transaction. During read cycle, this signal asserted indicate that selected device driving valid data onto ad<31:0>. During write cycle, this signal asserted indicate that selected device ready accept write data. current data phase completes when both trdy_l irdy_l asserted when sampled. JTAG test access port (TAP) reset signal. This signal must asserted during power-up, select standard SROM initialization Icache. left continuously asserted other JTAG functions need exercised. When this signal asserted, memory controller uses video graphics control register fields
trst_l
vframe_l
Reload video display pointer with start-of-video-frame
value.
Perform full VRAM shift-register load cycle bank
selected start-of-video-frame value.
Increment video display pointer twice, specified
address increment value.
(continued next page)
Table (Cont.) Signal Description
Signal vrefresh_l Type Description When this signal asserted, memory controller uses video graphics control register fields
Perform split VRAM shift-register load cycle bank
selected start-of-video-frame value.
Increment video display pointer once specified
address increment value.
Quick Reference Signals Function Direction
Table provides quick reference signals, grouped function. Table Signals Function
Name Type Purpose Value Reset
Memory Controller Signals bc_cs_l bc_dirty bc_idx_tag<4:0> bc_index bc_oe_l bc_parity bc_tag<7:0> bc_we_l mem_addr<11:0> mem_cas_l mem_data<63:0> mem_dsf mem_dtoe_l mem_ecc<7:0> mem_rasa_l<3:0> mem_rasb_l<3:0> mem_rd_oe mem_write_l mem_wr_oe_l vframe_l vrefresh_l Bcache chip select Bcache valid Bcache index Bcache index (bit Bcache output enable Bcache parity Bcache Bcache write-enable Row/column address, Bcache index Column address strobe Memory/Bcache data Disable special function Data transfer/output enable Memory/Bcache error correction code address strobes Memory read transceiver output enable Write-enable Memory write transceiver output enable Load video display pointer load VRAM shift register Increment video display pointer load VRAM shift register Driven, asserted Tristate Tristate Driven, UNDEFINED Driven, asserted Tristate Tristate Driven, deasserted Driven, UNDEFINED Driven, deasserted Tristate Driven, deasserted Driven, deasserted Tristate Driven, deasserted Driven, deasserted Driven, deasserted Driven, asserted
applicable
(continued next page)
Table (Cont.) Signals Function
Name Signals ad<31:0> multiplexed address data multiplexed cycle command byte enables device select cycle frame grant initiator ready lock Grant access 21066 memory Request access 21066 memory even parity Tristate when gnt_l deasserted; otherwise, UNDEFINED Tristate when gnt_l deasserted; otherwise, UNDEFINED Tristate Tristate Type Purpose Value Reset
c_be_l<3:0>
devsel_l frame_l gnt_l irdy_l lock_l memack_l memreq_l
Tristate Tristate Tristate when gnt_l deasserted; otherwise, UNDEFINED Tristate Tristate Asserted Tristate Tristate
pci_clk_in perr_l req_l stop_l trdy_l Clock Signals pll_bypass pll_clk_in pll_clk_in_l pll_i_ref
clock input parity error request reset target stop target ready
bypass select clock input clock input reference current
applicable
(continued next page)
Table (Cont.) Signals Function
Name Clock Signals pll_filter pll_5v reset_in_l test_clk_out JTAG Signals JTAG boundary scan clock JTAG serial boundary scan data JTAG serial boundary scan data JTAG test mode select JTAG reset Determined state JTAG controller low-pass filter capacitor voltage supply Master reset input Output clock Type Purpose Value Reset
Driven, clocking
trst_l
Interrupt, SROM Interface, instr_ref Signals instr_ref Istream Dstream reference lock_l deasserted mode PCI_SYNC_MODE, this driven with pci_clk_in; otherwise, this driven with chip internal clock Driven high Driven, deasserted
irq<2:0> sromclk sromd sromoe_l
External interrupt request SROM clock transmit serial data SROM data receive serial data SROM output enable
applicable
Table provides quick reference signals, grouped direction.
Table Signals Direction
Signal Input Signals gnt_l irq<2:0> lock_l memreq_l pci_clk_in pll_bypass pll_clk_in Output Signals bc_cs_l bc_index bc_oe_l bc_we_l instr_ref memack_l mem_addr<11:0> Signals ad<31:0> bc_dirty bc_idx_tag<4:0> bc_parity bc_tag<7:0> High High High High High c_be_l<3:0> devsel_l frame_l irdy_l mem_data<63:0> High mem_ecc<7:0> perr_l stop_l trdy_l High High High High High mem_cas_l mem_dsf mem_dtoe_l mem_rasa_l<3:0> mem_rasb_l<3:0> mem_rd_oe mem_write_l High High mem_wr_oe_l req_l rst_l sromclk sromoe_l test_clk_out High High High High High High High pll_clk_in_l pll_filter pll_i_ref pll_5v reset_in_l sromd High High High High trst_l vframe_l vrefresh_l High High High Active Level Signal Active Level Signal Active Level
Electrical Specifications
This section specifies: electrical conformance Absolute maximum ratings Supply current power dissipation Chip power supply sequencing specifications
Electrical Specification Conformance
21066 pins conform basic electrical specifications Local Specification, Revision 2.0, including: Standard signaling Logic levels follow standard thresholds accommodate drivers receivers implemented with existing CMOS devices processes. 33-10 support 21066 supports 33-MHz interconnection devices.
Absolute Maximum Ratings
Table lists absolute maximum ratings 21066. These stress ratings only; extended exposure maximum ratings might affect reliability device. Caution Although 21066 incorporates protective circuitry resist damage from static electric discharge, Digital recommends avoiding high-static voltages electric fields.
Table Absolute Maximum Ratings
Parameter Storage temperature range Active temperature range (case) Supply voltage Supply voltage (pll_5v) protection voltage Overshoot (5-V-safe pins) Overshoot (5-V-nonsafe pins) Undershoot Minimum -55°C -0.5 -0.5 Maximum +125°C 1500.0 Notes Table Notes Table -1.0
applicable Table Section maximum case temperatures.
Supply Current Power Dissipation
supply current power dissipation follows:
Microprocessor Parameter Power 21066A-266 (maximum) 21066A-233 (maximum) 21066-166 (maximum) 21066A-100 (maximum)
Test Conditions supply current power dissipation test conditions follows:
Parameter Package temperature with heat sink pll_5v Clock frequency Condition Table Section (maximum). 3.465 5.250 MHz/233.33 MHz/166.67 MHz/100
Chip Power Supply Sequencing
(3.3-V) pll_5v (5-V) supply voltages should ramp ramp down simultaneously, ramps need perfectly aligned. shown following relationship, rule that pll_5v supply must never exceed value supply more than that cannot less than ground more than 3.465
(pll_5v 3.465
This tells that, when supply less, 3.3-V supply zero. after supply exceeds 3.3-V supply must match rise supply, volt volt. example, when supply reaches 3.3-V supply must more (4.5 0.9). ramp rates supplies part equation only difference voltages need considered. However, power supplies with long ramp rates (several tens milliseconds longer) should avoided because such slow ramp rates likely cause excessive heating. 3.3-V supply ramps before supply, there voltagedifferential restrictions value 3.3-V supply lead value supply amount. However, because power dissipation high absence clocks, phase-locked loop (PLL) that generates clocks runs timing restricted. power-up, supply leads pll_5v supply, pll_5v supply must reach more than second after supply reached Generally, there problem during power-down provided that clocks stopped longer than second while 3.3-V supply remains applied. This power-down timing restriction satisfied ensuring that value supply will less within second after value pll_5v supply less than Because rules supply leading pll_5v supply more difficult implement, Digital recommends that pll_5v supply applied removed before supply according guidelines this section. pll_5v must connected directly supply either clamps used.
Specifications
Table lists characteristics. Table Characteristics
Signals mem_data<63:0> mem_ecc<7:0> mem_addr<11:0> mem_write_l mem_rasa_l<3:0> mem_rasb_l<3:0> mem_cas_l mem_dtoe_l mem_dsf mem_rd_oe mem_wr_oe_l bc_oe_l bc_tag<7:0> bc_parity bc_index bc_idx_tag<4:0> bc_cs_l bc_we_l bc_dirty vframe_l vrefresh_l ad<31:0> c_be_l<3:0> frame_l trdy_l irdy_l stop_l
Type
Internal3 Pull-Up Notes Pull-Down Pull-down Pull-down Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-down Pull-up Pull-down Pull-down Pull-down Pull-up Pull-down
Signals perr_l devsel_l req_l gnt_l rst_l lock_l pci_clk_in memreq_l memack_l pll_clk_in pll_clk_in_l pll_bypass pll_filter pll_i_ref pll_i_ref_ret test_clk_out reset_in_l trst_l irq<2:0> sromoe_l sromd sromclk instr_ref
Type
Internal3 Pull-Up Notes Pull-Down
Pull-up Pull-up Pull-down Pull-up
Internal pull-up pull-down during reset JTAG operations. req_l tristated during chip reset.
Notes Table
input-only pins 5-V-safe. This means that long ±5%, these pins safely exposed voltages indefinitely. addition, overshoots allowed duty cycle, pulse. input-only pins 5-V-safe when less than 3.135 Under these conditions, pins exposed voltages greater length time. Overshoots greater allowed duty cycle, pulse. These overshoot limits apply pins unless pll_5v 4.75
output-only pins 5-V-safe. This means that when driving, these pins exposed voltages indefinitely, cannot exposed higher voltages. Therefore, returned reflections present, they must limited test equipment used overdrive output-only pin, test equipment must expose voltages greater than
3.5.1 Operating Specifications Table lists functional operating parameters 21066, Table lists them 21066A. functional operating range follows: Tcase (maximum) (package temperature with heat sink) except noted. (See Table Section maximum case temperatures.) Note Tables currents into chip (chip sinking) denoted positive current. Currents from chip (chip sourcing) denoted negative current.
Table 21066 Parameters
Symbol Parameter Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Input leakage current
Min3
Max3
Unit Comments
pins without internal pullup pull-down pins with internal pulldown pins with internal pull-up Pins without pull-up pulldown Pins with pull-down Pins with pull-up Frequency MHz, design Frequency MHz, design
Input leakage current Input leakage current Tristate leakage current
+175
0260
+195
0195
Input capacitance output-only capacitance
minimum, maximum
(continued next page)
Table (Cont.) 21066 Parameters
Symbol Parameter Cclk capacitance: pll_clk_in pll_clk_in_l pci_clk_in Differential voltage: pll_clk_in pll_clk_in_l Inactive clock bias voltage: pll_clk_in pll_clk_in_l Externally driven voltage Externally driven voltage
Min3
Max3
Unit Comments Frequency MHz, design Frequency MHz, design Frequency MHz, design Vcclk 1.2-V nominal clock differential center voltage single-ended clock operation
±0.6 ±0.6
Viclk
Vbclk
Also applies pins pll_5v 4.75 duty cycle, maximum pulse width, also applies pins pll_5v 4.75 pll_5v
Vclamp clamp voltage
minimum, maximum clamps protect only 21066 other devices bus.
Table 21066A Parameters
Symbol Parameter Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Input leakage current
Min3
Max3
Unit Comments
pins without internal pullup pull-down
minimum, maximum
(continued next page)
Table (Cont.) 21066A Parameters
Symbol Parameter Input leakage current Input leakage current Tristate leakage current Min3
Max3 +175
Unit Comments pins with internal pulldown pins with internal pull-up Pins without pull-up pulldown Pins with pull-down Pins with pull-up Frequency MHz, design Frequency MHz, design
0230
+215
0270
Cclk
Input capacitance output-only capacitance capacitance: pll_clk_in pll_clk_in_l pci_clk_in Differential voltage: pll_clk_in pll_clk_in_l Inactive clock bias voltage: pll_clk_in pll_clk_in_l Externally driven voltage
±0.6 ±0.6
Frequency MHz, design Frequency MHz, design Frequency MHz, design Vcclk 1.2-V nominal clock differential center voltage single-ended clock operation
Viclk
Vbclk
pll_clock_in, pll_clock_in_l Applies other pins except test_clk_out,pll_filter, pll_i_ref pll_5v 4.75 duty cycle, maximum pulse width, applies other pins except test_clk_out, pll_filter, pll_i_ref pll_5v 4.75 pll_5v
Externally driven voltage
Vclamp clamp voltage
7.35
minimum, maximum
clamps protect only 21066A other devices bus.
Specifications
specifications consist input requirements output responses. input requirements rise fall times, pulse widths, setup hold times. Output responses delays from clock signal. Test Conditions test conditions parameters specified this section (except Table follows:
Parameter Package temperature with heat sink Cload Condition
unless otherwise specified
Table Section maximum case temperatures.
Figure defines parameter measurements.
Figure Timing Measurement
Rise Fall
Rise Time Fall Time Pulse Width
Setup
Clock
Width Hold
Setup Hold Time
Valid Signal
Delay
Output Delay
Valid Signal
Valid High Impedance
Valid Signal
High
High Impedance Valid
High
Valid Signal
Table lists clock reset parameters. Table Clock Reset Parameters
Symbol Parameter/Signals Tfreq Internal clock frequency Frequency pll_clk pll_clk pci_clk Clock cycle time pll_clk pll_clk pci_clk Clock high time pll_clk pll_clk pci_clk Clock time pll_clk pll_clk pci_clk Clock rise time pll_clk pll_clk pci_clk Clock fall time pll_clk pll_clk pci_clk Reset pulse width reset_in_l (PCI) Setup time reset_in_l Clock active time Delay time test_clk_out Min* Max* 266/233.33/ 166.67/100 0.42Tcyc 0.42Tcyc 0.42Tcyc 0.42Tcyc 102Tcyc
Unit
Notes
16.67
Tcyc
Thigh
Tlow
design
design
design
Trst
Trss Trst_ Tclkout
minimum, maximum. Bypass Bypass
Notes Table
pll_clk refers both pll_clk_in pll_clk_in_l, differential clock inputs chip. maximum internal clock frequency (Tif) 21066A-100, 166.67 21066-166, 233.33 21066A-233, 21066A-266. internal highfrequency clock function programmed multiplier value irq<2:0> pins during reset. pll_clk maximum frequency must chosen such that maximum internal clock frequency (Tif) exceeded. When pll_bypass asserted, internal clock frequency equals external clock frequency. When pll_bypass deasserted, typical internal clock frequencies follows:
pll_clk_in (MHz) Multiplier Values 150.00 133.33 116.67 100.00 83.33 66.67 50.00 33.33 16.67 25.00 33.33
Internal Clock Frequency (MHz) 225.00 200.00 175.00 150.00 125.00 100.00 75.00 50.00 300.00* 266.67* 233.33 200.00 166.67 133.33 100.00 66.67
maximum internal frequency (Tif) limits range multiplier values given pll_clk_in frequency. Although these multiplier values available, they should used this pll_clk_in frequency following: 21066A-233 21066A-100 21066-166 21066A-266
clock input asynchronous internal clock. correct operation, clock frequency must less than equal internal clock frequency. Trst typical Signal reset_in_l asynchronous input. setup time only tester. Clock must before deassertion rst.
Signal test_clk_out delay measured with respect rising edge pll_clk_in. Guaranteed design.
maintain stable operation, 0.01-µF capacitor connected between pll_filter Vss. sets feedback-loop time constant needed regulate speed with which responds changes frequency operating conditions. Additionally, 5.1-k
resistor connected between pll_i_ref Vss. constant current that flows resistor provides reference analog circuits.
Table lists memory controller parameters. parameters relative core clock. Table Memory Controller Parameters
Symbol Tsv1 Tvz1 Tzv1 Tsv2 Parameter Setup time Hold time Valid delay time Valid high-Z delay time High-Z valid delay time Setup time Signals mem_data<63:0> mem_ecc<7:0> mem_data<63:0> mem_ecc<7:0> mem_data<63:0> mem_ecc<7:0> mem_data<63:0> mem_ecc<7:0> mem_data<63:0> mem_ecc<7:0> bc_tag<7:0> bc_parity bc_idx_tag<4:0> bc_dirty bc_tag<7:0> bc_parity bc_idx_tag<4:0> bc_dirty bc_tag<7:0> bc_parity bc_idx_tag<4:0> bc_dirty mem_addr<11:0> bc_index bc_tag<7:0> bc_parity bc_idx_tag<4:0> bc_dirty bc_index bc_tag<7:0> bc_parity bc_idx_tag<4:0> bc_dirty bc_index Minimum 1.50 0.50 1.50 2.00 Maximum 4.50 4.00 Notes
Hold time
0.00
Valid delay time
4.25
Tvz2
Valid high-Z delay time
3.75
Tzv2
High-Z valid delay time
1.50
(continued next page)
Table (Cont.) Memory Controller Parameters
Symbol Parameter Valid delay time Signals mem_cas_l mem_rd_oe mem_wr_oe_l mem_rasa_l<3:0> mem_rasb_l<3:0> mem_dtoe_l mem_dsf mem_write_l bc_we_l bc_oe_l bc_cs_l vrefresh_l vframe_l vrefresh_l vframe_l vrefresh_l vframe_l Minimum Maximum 4.00 Notes
Valid delay time
3.75
Valid delay time
4.50
Tpwl Tpwh
Pulse width time Pulse width high Time which assertion vrefresh_l vframe_l must separated
10.00 1000.00 1000.00
85.00
Notes Table
Setup hold times measured with respect rising edge test_clk_out pin. test_clk_out pin, when loaded with lumped 40-pF load, imitates internal clock. 21066A, when pll_bypass test_clk_out internal clock divided when pll_bypass test_clk_out imitates internal clock. test_clk_out intended test purposes only. drive times assume lumped, 40-pF load measured with respect test_clk_out pin. 21066A, pll_bypass defined tristate when 2-mA current source changes output voltage assumed connected lumped 40-pF load this test.
Table lists controller parameters. parameters relative clock signal pci_clk_in.
Table Parameters
Symbol Tval Parameter Clock signal valid delay time Signals ad<31:0> c_be_l<3:0> frame trdy_l irdy_l stop_l perr_l devsel_l lock_l ad<31:0> c_be_l<3:0> frame trdy_l irdy_l stop_l perr_l devsel_l lock_l ad<31:0> c_be_l<3:0> frame trdy_l irdy_l stop_l perr_l devsel_l lock_l ad<31:0> c_be_l<3:0> frame trdy_l irdy_l stop_l perr_l devsel_l lock_l Minimum Maximum
Tival
Clock signal invalid delay time
High-Z active delay time
Toff
Active high-Z delay time
Cload
(continued next page)
Table (Cont.) Parameters
Symbol Parameter Input signal valid setup time Signals ad<31:0> c_be_l<3:0> frame trdy_l irdy_l stop_l perr_l devsel_l lock_l memreq_l ad<31:0> c_be_l<3:0> frame trdy_l irdy_l stop_l perr_l devsel_l lock_l memreq_l memack_l req_l gnt_l Minimum Maximum
Input signal hold time
Tackv Tval-side Tsu-side
Valid delay time from clock rising edge Signal valid delay time Signal valid setup time
Cload
signaling environment used bus, pll_5v must connected supply. Table (abridged from Local Specification, Revision 2.0) specifies parameters signaling.
Table Specifications Signaling
Symbol Parameter clamp current Unloaded output rise time Unloaded output fall time Condition Minimum Maximum Unit V/ns
(Vin 0.015
V/ns
Table lists JTAG parameters. Table JTAG Parameters
Symbol Parameter Tjht Tjlt Tjrt Tjft Tjfd Frequency Period High time time Rise time Fall time Setup time Hold time Valid delay Float delay Signals Minimum Maximum Unit Comments Measured between Measured between With respect rising edge With respect rising edge With respect falling edge Cload With respect falling edge
Table lists parameters miscellaneous pins. parameters specified test purposes only measured with respect test_clk_out signal. Table Miscellaneous Parameters
Symbol Tmst Tmht Parameter Setup time Hold time Signals irq<2:0> sromd irq<2:0> sromd Minimum Maximum
Mechanical Specifications
Figures show 287-pin standard grid array (PGA) package dimensions. Figure 21066/21066A Package-Top Side
0.050 0.195 HEAT SLUG BASE AREA 1.250 0.850 CHAMFER (0.010 45°) 0.035 0.005
0.018
10-32 STUD (2X)
0.005 1.130
0.250
21066: 0.106 0.011 1.130 2.260 ±0.014 CHAMFER (0.010 45°) 21066A: 0.069 0.007
Figure 21066/21066A Package-Bottom
1.050 0.100 0.100 1718
1.050
STANDOFF (4X)
287X 0.065 BRAZE
POSITION INDICATOR
Thermal Specifications
Sections specify 21066 operating temperature thermal resistance.
Operating Temperature
operating temperature 21066 measured center heat sink between package studs. 21066 specified operate within temperature range from (maximum), which based operating frequency chip. Table gives maximum operating temperatures 21066. Table Maximum Various Frequencies
(Maximum) Frequency 21066 85°C 21066A 93°C 84°C 70°C
Thermal Resistance
following equations define heat-sink-to-ambient thermal resistance values:
2hs0a
2hs0a
symbols previous equations defined follows:
2hs0a heat-sink-to-ambient thermal resistance (°C/W). ambient temperature (°C). case temperature measured predefined location
heat sink (°C). power dissipation (W). Section 3.3, which details chip power consumption various frequencies.
Table lists 2hs0a values several heat sinks used with 21066 287-pin ceramic PGA. Note heat sink greatly improves ambient temperature requirement Digital recommends use.
Table
2hs0a Various Airflows
Heat Sink 2.65 1.95 1.35 1.00 0.85
2hs0a with:
Heat Sink 7.35 6.55 5.00 3.10 2.10 1.65
Airflow (ft/min)
Heat Sink 3.70 2.80 1.85 1.30 1.10
Heat sink fins): 2.55 Heat sink fins): Heat sink fins):
2.55 (6.5 2.27 2.27 (5.8 2.38 2.10 (6.0
heat sinks unidirectional made aluminium alloy 6063. GRAFOIL interface material between package heat sink.
Register Summary
tables this section provide summary 21066 implementationspecific internal processor registers (IPRs), memory controller registers, controller (IOC) registers. information about architecturally specified IPRs, Alpha Architecture Reference Manual. Table 21066-Specific Internal Processor Registers
Mnemonic Register Name
Field3 Index3
Instruction Fetch Decode Unit Registers ASTER ASTRR EXC_ADDR EXC_SUM HIER HIRR ICCSR ITBASM ITBIS ITB_PTE ITB_PTE_TEMP ITBZAP PAL_BASE SIER SIRR SL_CLR SL_RCV SL_XMIT TB_TAG Asynchronous system trap interrupt enable Asynchronous system trap request Exception address Exception summary Hardware interrupt enable Hardware interrupt request Instruction cache control status Instruction translation buffer address space match Instruction translation buffer initial state Instruction translation buffer page table entry Instruction translation buffer page table entry temporary Instruction translation buffer Programmable array logic (PAL) base address Processor status Software interrupt enable Software interrupt request Clear serial line interrupt Serial line receive Serial line transmit Translation buffer
Load Store Unit Registers ABOX_CTL ALT_MODE Load store unit (Abox) control Alternate processor mode Cycle counter
HW_MFPR HW_MTPR instruction fields:
PAL, ABX, IBX, Index (<7,6,5,4:0>).
(continued next page)
Table (Cont.) 21066-Specific Internal Processor Registers
Mnemonic Register Name
Field3 Index3
Load Store Unit Registers CC_CTL DC_STAT C_STAT DTBASM DTB_CTL DTBIS DTB_PTE DTB_PTE_TEMP DTBZAP FLUSH_IC FLUSH_IC_ASM MM_CSR Cycle counter control Data cache status Cache status Data translation buffer address space match Data translation buffer control Data translation buffer invalidate single Data translation buffer page table entry Data translation buffer page table entry temporary Data translation buffer Flush instruction cache Flush instruction cache address space match Memory management control status Virtual address
Temporary Registers PAL_TEMP<31:0> PAL_TEMP internal processor 31.0
HW_MFPR HW_MTPR instruction fields:
Implemented 21066A only. Implemented 21066 only.
PAL, ABX, IBX, Index (<7,6,5,4:0>).
Table Memory Controller Registers
Mnemonic BCR0 BCR1 BCR2 BCR3 BMR0 BMR1 BMR2 BMR3 BTR0 Register Name Bank Bank Bank Bank Bank Bank Bank Bank Bank configuration configuration configuration configuration mask mask mask mask timing Address (Hexadecimal) 2000 2000 2000 2000 2000 2000 2000 2000 2000 0000 0008 0010 0018 0020 0028 0030 0038 0040
(continued next page)
Table (Cont.) Memory Controller Registers
Mnemonic BTR1 BTR2 BTR3 PMR3 Register Name Bank timing Bank timing Bank timing Global timing Error status Error address Cache control Video graphics control Plane mask Foreground Power management register Address (Hexadecimal) 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 0048 0050 0058 0060 0068 0070 0078 0080 0088 0090 0098
Implemented 21066A only.
Table Controller Registers
Mnemonic IOC_HAE IOC_CFG IOC_STAT0 IOC_STAT1 IOC_TBIA IOC_TB_ENA IOC_SFT_RST IOC_PAR_DIS IOC_W_BASE0 IOC_W_BASE1 IOC_W_MASK0 IOC_W_MASK1 IOC_T_BASE0 IOC_T_BASE1 IOC_TB_TAG0 IOC_TB_TAG1 IOC_TB_TAG2 IOC_TB_TAG3 IOC_TB_TAG4 Register Name Host address extension Configuration cycle type Status Status Translation buffer invalidate Translation buffer enable soft reset Parity disable Window base Window base Window mask Window mask Translated base Translated base Translation buffer Translation buffer Translation buffer Translation buffer Translation buffer Address (Hexadecimal) 8000 8000 8000 8000 8000 8000 8000 8000 8000 8000 8000 8000 8000 8000 8100 8100 8100 8100 8100 0000 0020 0040 0060 0080 00A0 00C0 00E0 0100 0120 0140 0160 0180 01A0 0000 0020 0040 0060 0080
(continued next page)
Table (Cont.) Controller Registers
Mnemonic IOC_TB_TAG5 IOC_TB_TAG6 IOC_TB_TAG7 IOC_IACK_SC Register Name Translation buffer Translation buffer Translation buffer Interrupt vector special cycle Address (Hexadecimal) 8100 00A0 8100 00C0 8100 00E0
quadword-aligned address range 1A0000000.1BFFFFFE0.
Instruction Summary
tables this section summarize common instructions implemented Alpha architecture, PALmode instructions required Alpha implementations, architecturally reserved PALmode instructions implemented 21066 microprocessor. instruction summaries contained following tables:
Instructions Memory integer load store Integer control Integer arithmetic Logical shift Byte manipulation Memory format floating-point Floating-point branch Floating-point operate Miscellaneous compatibility instructions Required PALmode Architecturally reserved PALmode Table
Table Memory Integer Load Store Instructions
Mnemonic LDAH LDL_L LDQ_L LDQ_U STL_C STQ_C STQ_U Operation Load address Load address high Load Load Load Load Load Store Store Store Store Store sign-extended longword sign-extended longword locked quadword quadword locked quadword unaligned longword longword conditional quadword quadword conditional quadword unaligned
Table Integer Control Instructions
Mnemonic BLBC BLBS JSR_COROUTINE Operation Branch Branch Branch Branch Branch Branch Branch Branch register register register register register register register register equal zero greater than equal zero greater than zero clear less than equal zero less than zero equal zero
Unconditional branch Branch subroutine Jump Jump subroutine Return from subroutine Jump subroutine return
Table Integer Arithmetic Instructions
Mnemonic S4ADD S8ADD CMPEQ CMPLT CMPLE CMPULT CMPULE UMULH S4SUB S8SUB Operation quadword/longword Scaled Scaled Compare signed quadword equal Compare signed quadword less than Compare signed quadword less than equal Compare unsigned quadword less than Compare unsigned quadword less than equal Multiply quadword/longword Multiply quadword unsigned high Subtract quadword/longword Scaled subtract Scaled subtract
Table Logical Shift Instructions
Mnemonic ORNOT CMOVxx Operation Logical Logical Logical Logical Logical Logical product product with complement (OR) equivalence (XORNOT) with complement difference
Conditional move integer Shift left logical Shift right arithmetic Shift right logical
Table Byte-Manipulation Instructions
Mnemonic CMPBGE EXTBL EXTWL EXTLL EXTQL EXTWH EXTLH EXTQH INSBL INSWL INSLL INSQL INSWH INSLH INSQH MSKBL MSKWL MSKLL MSKQL Operation Compare byte Extract Extract Extract Extract Extract Extract Extract Insert Insert Insert Insert Insert Insert Insert Mask Mask Mask Mask byte word longword quadword word high longword high quadword high
byte word longword quadword word high longword high quadword high byte word longword quadword (continued next page)
Table (Cont.) Byte-Manipulation Instructions
Mnemonic MSKWH MSKLH MSKQH ZAPNOT Operation Mask word high Mask longword high Mask quadword high Zero bytes Zero bytes
Table Memory Format Floating-Point Instructions
Mnemonic Operation Load Load Load Load Store Store Store Store F_floating G_floating (load D_floating) S_floating (load longword integer) T_floating (load quadword integer) F_floating G_floating (store D_floating) S_floating (store longword integer) T_floating (store quadword integer) Subset IEEE IEEE IEEE IEEE
Table Floating-Point Branch Instructions
Mnemonic FBEQ FBGE FBGT FBLE FBLT FBNE Operation Floating Floating Floating Floating Floating Floating branch branch branch branch branch branch equal greater than equal greater than less than equal less than equal Subset IEEE IEEE IEEE IEEE IEEE IEEE
Table Floating-Point Operate Instructions
Mnemonic Arithmetic Operations ADDF ADDG ADDS ADDT CMPGxx CMPTxx CVTDG CVTGD CVTGF CVTGQ CVTQF CVTQG CVTQS CVTQT CVTST CVTTQ CVTTS DIVF DIVG DIVS DIVT MULF MULG MULS MULT SUBF SUBG SUBS SUBT F_floating G_floating S_floating T_floating IEEE IEEE IEEE IEEE IEEE IEEE IEEE IEEE IEEE IEEE IEEE IEEE IEEE IEEE (continued next page) Operation Subset
Compare G_floating Compare T_floating Convert Convert Convert Convert Convert Convert Convert Convert Convert Convert Convert Divide Divide Divide Divide D_floating G_floating G_floating D_floating G_floating F_floating G_floating quadword quadword F_floating quadword G_floating quadword S_floating quadword T_floating S_floating T_floating T_floating quadword T_floating S_floating
F_floating G_floating S_floating T_floating F_floating G_floating S_floating T_floating F_floating G_floating S_floating T_floating
Multiply Multiply Multiply Multiply Subtract Subtract Subtract Subtract
Table (Cont.) Floating-Point Operate Instructions
Mnemonic Operation Subset
FPCR Operations CPYS CPYSE CPYSN CVTLQ CVTQL FCMOVxx MF_FPCR MT_FPCR Copy sign Copy sign exponent Copy sign negate Convert longword quadword Convert quadword longword Floating conditional move Move from floating-point control register Move floating-point control register IEEE IEEE IEEE IEEE IEEE IEEE IEEE IEEE
Table Miscellaneous Instructions
Mnemonic CALL_PAL EXCB FETCH FETCH_M RPCC TRAPB Operation Call privileged architecture library routine Exception barrier Prefetch data Prefetch data, modify intent Memory barrier Read process cycle counter Trap barrier Write memory barrier
Table Compatibility Instructions
Mnemonic Operation Read clear Read
Table Required PALmode Instructions
Mnemonic HALT Operation Halt processor Instruction stream memory barrier
Table Architecturally Reserved PALmode Instructions
Mnemonic HW_MTPR HW_MFPR HW_LD HW_ST HW_REI Operation Move data processor register Move data from processor register Move data from memory Move data memory Return from PALmode exception
Technical Support Ordering Information
Technical Support need technical support help deciding which literature best meets your needs, call Digital Semiconductor Information Line: United States Canada Outside North America 1-800-332-2717 +1-508-628-4760
Ordering Digital Semiconductor Products order Alpha 21066 Alpha 21066A microprocessors, contact your local distributor. order following semiconductor products from Digital:
Product 21066-166 microprocessor 21066A-233 microprocessor 21066A-100 microprocessor 21066A-266 microprocessor Order Number 21066-AA 21066-AB 21066-CB 21066-DB
Ordering Associated Literature following table lists some available Digital Semiconductor literature. complete list, contact Digital Semiconductor Information Line.
Title Alpha Architecture Reference Manual1
Order Number EY-L520E-DP-YCH
order purchase Alpha Architecture Reference Manual, call 1-800-DIGITAL from U.S. Canada, contact your local Digital office, technical reference bookstore where Digital Press books distributed Prentice Hall.
Ordering Third-Party Literature order following third-party literature directly from vendor.
Title Local Specification, Revision Vendor Special Interest Group 1-800-433-5177 (U.S.) 1-503-797-4207 (International) 1-503-234-6762 (FAX) IEEE Service Center Hoes Lane P.O. 1331 Piscataway, 08855-1331 1-800-678-IEEE (U.S. Canada) 908-562-3805 (Outside U.S. Canada)
IEEE Standard Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754-1985)

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