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Alpha 21064A Microprocessors Data Sheet
Order Number: EC-QFGKC-TE This document contains information about following Alpha microprocessors: 21064A-200, 21064A-233, 21064A-275, 21064A-275-PC, 21064A-300.
Revision/Update Information:
This document supersedes Alpha 21064A-233, -275 Microprocessor Data Sheet, EC-QFGKB-TE.
Digital Equipment Corporation Maynard, Massachusetts
January 1996 While Digital believes information included this publication correct date publication, subject change without notice. Digital Equipment Corporation makes representations that products manner described this publication will infringe existing future patent rights, descriptions contained this publication imply granting licenses make, use, sell equipment software accordance with description. Digital Equipment Corporation 1995, 1996. Printed U.S.A. rights reserved.
AlphaGeneration, Digital, Digital Semiconductor, OpenVMS, VAX, DOCUMENT, AlphaGeneration design mark, DIGITAL logo trademarks Digital Equipment Corporation. Digital Semiconductor Digital Equipment Corporation business. GRAFOIL registered trademark Union Carbide Corporation. Windows trademark Microsoft Corporation. other trademarks registered trademarks property their respective owners.
This document prepared using DOCUMENT Version 2.1.
Contents
4.1.1 4.1.2 4.1.3 4.1.3.1 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 4.1.11 4.1.12 4.1.13 4.1.14 Overview Signal Names Functions Instruction Instruction Summary IEEE Floating-Point Instructions 21064A IEEE Floating-Point Conformance Floating-Point Instructions Required PALcode Function Codes Opcodes Reserved PALcode Opcodes Reserved Digital Instructions Specific 21064A Internal Processor Registers Ibox Internal Processor Registers Translation Buffer Register (TB_TAG) Instruction Translation Buffer Page Table Entry Register (ITB_PTE) Instruction Cache Control Status Register (ICCSR) Performance Counters Instruction Translation Buffer Page Table Entry Temporary Register (ITB_PTE_TEMP) Exceptions Address Register (EXC_ADDR) Clear Serial Line Interrupt Register (SL_CLR) Serial Line Receive Register (SL_RCV) Instruction Translation Buffer Register (ITBZAP) Instruction Translation Buffer Register (ITBASM) Instruction Translation Buffer Register (ITBIS) Processor Status Register (PS) Exception Summary Register (EXC_SUM) PAL_BASE Address Register (PAL_BASE) Hardware Interrupt Request Register (HIRR)
4.1.15 4.1.16 4.1.17 4.1.18 4.1.19 4.1.20 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.2.11 4.2.12 4.2.13 4.2.14 4.2.15 4.2.16 4.2.17 4.2.18 4.2.19 4.2.20 4.2.21
Software Interrupt Request Register (SIRR) Asynchronous Trap Request Register (ASTRR) Hardware Interrupt Enable Register (HIER) Software Interrupt Enable Register (SIER) Interrupt Enable Register (ASTER) Serial Line Transmit Register (SL_XMIT) Abox Internal Processor Registers Translation Buffer Control Register (TB_CTL) Data Translation Buffer Page Table Entry Register (DTB_PTE) Data Translation Buffer Page Table Entry Temporary Register (DTB_PTE_TEMP) Memory Management Control Status Register (MM_CSR) Virtual Address Register (VA) Data Translation Buffer Register (DTBZAP) Data Translation Buffer Register (DTBASM) Data Translation Buffer Invalidate Single Register (DTBIS) Flush Instruction Cache Register (FLUSH_IC) Flush Instruction Cache Register (FLUSH_IC_ASM) Abox Control Register (ABOX_CTL) Alternate Processor Mode Register (ALT_MODE) Cycle Counter Register (CC) Cycle Counter Control Register (CC_CTL) Interface Unit Control Register (BIU_CTL) Cache Status Register (C_STAT) Interface Unit Status Register (BIU_STAT) Interface Unit Address Register (BIU_ADDR) Fill Address Register (FILL_ADDR) Fill Syndrome Register (FILL_SYNDROME) Backup Cache Register (BC_TAG) PAL_TEMP Registers Lock Registers Internal Processor Registers Reset State Electrical Characteristics Characteristics Characteristics Thermal Considerations Critical Parameters Thermal Design Mechanical Specifications Package Information
21064A Pins Signal Lists
Figures
Block Diagram Alpha 21064A Microprocessor Translation Buffer Register Instruction Translation Buffer Page Table Entry Register ICCSR Register ITB_PTE_TEMP Register Exception Address Register Clear Serial Line Interrupt Register Serial Line Receive Register Processor Status Register Exception Summary Register PAL_BASE Address Register Hardware Interrupt Request Register Software Interrupt Request Register Asynchronous Trap Request Register Hardware Interrupt Enable Register Software Interrupt Enable Register Interrupt Enable Register Serial Line Transmit Register Translation Buffer Control Register Data Translation Buffer Page Table Entry Register Data Translation Buffer Page Table Entry Temporary Register Memory Management Control Status Register Abox Control Register Alternate Processor Mode Register Cycle Counter Register Cycle Counter Control Register 21064A Interface Unit Control Register Cache Status Register Interface Unit Status Register Interface Unit Address Register Fill Address Register
FILL_SYNDROME Register Backup Cache Register Clock Termination Input Clock Timing Diagram Reset Timing Reset Timing-End Preload Sequence Output Delay Time Measurement Setup Hold Time Measurement READ_BLOCK Timing Diagram WRITE_BLOCK Timing Diagram BARRIER Timing Diagram FETCH/FETCH_M Timing Diagram Package Components Temperature Measurement Locations Heat Sink Dimensions Package Dimensions Cavity Down View
Tables
Data, Address, Parity/ECC Signals Primary Cache Invalidate Signals External Cache Control Signals Fast Lock Mode Signals External Cycle Control Signals Interrupt Signals Instruction Cache Initialization Serial Interface Signals Initialization Signals Clock Signals Performance Monitoring Signals Other Signals Instruction Format Opcode Notation Architecture Instructions IEEE Floating-Point Instruction Function Codes Floating-Point Instruction Function Codes Required PALcode Function Codes
Opcodes Specific 21064A Opcodes Reserved Digital Instructions Specific 21064A ICCSR Fields Description BHE, Branch Prediction Selection (Conditional Branches Only) Performance Counter Input Selection ICCSR) Performance Counter Input Selection ICCSR) Clear Serial Line Interrupt Register Fields Exception Summary Register Fields Hardware Interrupt Request Register Fields Hardware Interrupt Enable Register Fields Memory Management Control Status Register Abox Control Register Fields Alternate Processor Mode Register Interface Unit Control Register Fields BC_SIZE BC_PA_DIS Cache Status Register Fields Interface Unit Status Register Fields Syndromes Single-Bit Errors Backup Cache Register Fields Internal Process Register Reset State 21064A Maximum Ratings (PRELIMINARY ESTIMATES) Input/Output Characteristics testClkIn States Input Clock Timing External Cycles 21064A-200 Thermal Characteristics Forced-Air Environment 21064A-233 Thermal Characteristics Forced-Air Environment 21064A-275 21064A-275-PC Thermal Characteristics Forced-Air Environment 21064A-300 Thermal Characteristics Forced-Air Environment List
Data Signals List Address Signals List Parity/ECC Signals List Primary Cache Invalidate Signals List External Cache Control Signals List Interrupt Signals List Instruction Cache Initialization Signals List Serial Interface Signals List Initialization Signals List Load/Lock Store/Conditional Fast Lock Mode Signals List Clock Signals List Performance Monitoring Signals List Other Signals List Power List Ground List Spare List
viii
Overview
This document describes Alpha 21064A microprocessors (21064A). five versions 21064A differ clock frequency indicated their labels (200, 233, 275, 275-PC, 300). 21064A-200, 21064A-233, 21064A-275, 21064A-300 functionally identical. Their memory management operation very flexible allow them enable multiple memory management functions different operating system environments. 21064A-275-PC functionally identical other four except that differs memory management functions. 21064A-275-PC will only support memory management functions necessary Windows operating system other operating systems using Windows memory management model. label 21064A will used describe functions operations that identical five devices. label 21064A-275-PC will used identify information that unique that device. 21064A features listed here: 64-bit RISC microprocessor implements Alpha architecture Super-scalar, 200, 233, 275, System clock frequency processor clock frequency divided value from Dual instruction issue that yields peak instruction execution rate 400, 466, 550, MIPS Super pipelined on-chip caches (with data parity protection) 16-Kbyte instruction cache (Icache) 16-Kbyte data cache (Dcache) Integer registers floating-point registers (64-bit) 2-bit branch prediction history table External data path selectable bits bits Byte parity mode available external data Fast lock mode available with LDx/L STx/C instructions Backward compatible with 21064 layout software
Programmable external cache size speed
43-bit virtual address 34-bit physical address IEEE floating-point data types Performance monitoring 64-bit internal data paths
21064A associated PALcode implement IEEE single- doubleprecision, F_floating G_floating data types, support longword (32-bit) quadword (64-bit) integers. Byte (8-bit) word (16-bit) support provided byte manipulation instructions. Limited hardware support provided D_floating data type. 21064A consists four independent functional units: Integer execution unit (Ebox) Floating-point unit (Fbox) Load/store address unit (Abox) Branch unit
Other sections include central control unit (Ibox), Icache Dcache. Ebox-Contains 64-bit fully pipelined integer execution data path including: adder, logic box, barrel shifter, byte extract mask, independent integer multiplier. Ebox also contains 32-entry, 64-bit integer register file. Fbox-Contains fully pipelined floating-point unit independent divider that supports both IEEE floating-point data types. IEEE singleprecision double-precision floating-point data types supported. F_floating G_floating data types fully supported, limited support provided D_floating data type. Abox-Contains five major sections: address translation data path, load silo, write buffer, data cache interface, external interface unit (BIU). Abox supports integer floating-point load store instructions including address calculation translation, cache control logic.
Ibox-Performs instruction fetch, resource checks, dual-instruction issue Ebox, Abox, Fbox, branch unit. addition, Ibox controls pipeline stalls, aborts, restarts. Pipeline Organization 21064A uses 7-stage pipeline integer operate memory reference instructions, 10-stage pipleline floating-point operate instructions. Ibox maintains state pipeline stages track outstanding register writes. Cache Organization 21064A contains on-chip caches-data cache (Dcache) instruction cache (Icache). 21064A also supports external cache. Icache-Contains bytes direct-mapped cache with 32-byte blocks. Virtual address physical address bits [12:5] index into cache. Dcache-Contains bytes write through, read-allocate cache with 32-byte blocks. used either modes. 8K-byte direct-mapped cache support 21064 designs). Physical address [12:5] index into cache. 16K-byte cache Dcache appears externally 2-way set-associative cache. Physical address [12:5] index into cache. Dcache appears internally direct-mapped cache. Virtual address [13] physical address [12:5] index into cache. External Cache-The 21064A supports external cache that made with readily available static RAMs. 21064A directly controls operation using programmable external cache interface, allowing each hardware implementation make external cache speed configuration trade-offs. external cache interface supports cache sizes 256K bytes, 512K bytes, bytes, bytes, bytes, bytes bytes. range operating speeds external cache sub-multiples 21064A clock.
Virtual Address Space architecture virtual address 64-bit unsigned integer that specifies byte location within virtual address space. 21064A implements 43-bit subset virtual address space. Physical Address Space 21064A uses 34-bit physical address support bytes physical address space. Backward Compatibility 21064A backward compatible with 21064. compatibility includes layout, PALcode, application programs. following restrictions apply compatibility between 21064A 21064. 21064A internal pulldown resistors inputs which unused spare pins 21064. these spare pins unconnected module designed 21064, then there will migration problem with these pins. pins have been reallocated other uses. these pins were used module designed 21064, then there will migration problem with these pins. 21064 pins tagEq_l tagAdr_h 21064A they lockWE_h lockFlag_h respectively. behavior tagOK protocol 21064A differs from that 21064. Designers should investigate effect change this protocol used existing 21064 modules.
Figure shows block diagram 21064A microprocessor. Figure Block Diagram Alpha 21064A Microprocessor
Instruction Cache (Icache) Branch History Table Parity Data Parity Address
Integer Execution Unit (Ebox) Multiplier Adder Shifter Logic
Instruction Fetch/Decode Unit (Ibox) Prefetcher Resource Conflict Calculation Pipeline Control
Floating-Point Execution Unit (Fbox) Multiplier/ Adder Divider
Data (128 bits)
Control
Integer Register File (IRF)
Floating-Point Register File (FRF) Interrupts
Load/Store Unit (Abox) Write Buffer Address Generator Load Silo External Cache Control
System Timing Data Cache (Dcache) Parity Data Parity
MLO-012077
Signal Names Functions
tables this section list various signals grouped function. information Type column identifies signal input (I), output (O), bidirectional (B). Signals with suffix active (asserted) when high. Those with suffix active (asserted) when low. Table describes 21064A data, address, parity/ECC signals. Table Data, Address, Parity/ECC Signals
Signal data_h [127:0] adr_h [33:5] Type Count Function Provide data path between 21064A system. Provide address path between 21064A system. These address bits provide granularity down 32-byte internal cache blocks. Provide path parity bits between 21064A rest system.
check_h [27:0]
Table describes 21064A primary cache invalidate signals. Table Primary Cache Invalidate Signals
Signal iAdr_h [12:5] dInvReq_h [1:0]1 Type Count Function Used index blocks Dcache Dcache invalidates. Used external logic invalidate Dcache entry indexed iAdr_h [12:5].
dInvReq_h location spare 21064. internal pulldown that draws maximum current
Table describes 21064A external cache control signals. Table External Cache Control Signals
Signal tagCEOE_h Type Count Function Controls control chip enable output enable during 21064A controlled external cache accesses. Controls control write enable during 21064A controlled transactions. Provide read/write path external cache valid, shared, dirty bits. following combinations tagCtl bits allowed. tagCtlS_h viewed write-protect bit. tagCtlV_h tagCtlS_h tagCtlD_h Meaning Invalid Valid, private Valid, private, dirty Valid, shared Valid, shared, dirty
tagCtlWE_h tagCtlV_h, tagCtlS_h, tagCtlD_h
tagCtlP_h
Carries parity across tagCtlV_h, tagCtlD_h, tagCtlS_h. (continued next page)
Table (Cont.) External Cache Control Signals
Signal tagAdr_h [33:18] tagAdrP_h tagOk_h, tagOk_l dataCEOE_h [3:0] dataWE_h [3:0] dataA_h [4:3] holdReq_h holdAck_h dMapWE_h [1:0]1
dMapWE_h
Type
Count
Function Carries address contents tagAdr 21064A address comparator parity checker. Carries parity contents tagAdr 21064A address comparator parity checker. interface control signals that allow external logic stall CPU-controlled access external cache RAMs last possible moment. Controls data RAMs output enable chip enable during 21064A controlled cache accesses. Controls data RAMs write enable during 21064A controlled cache accesses. Controls data RAMs adr_h [4:3] during 21064A controlled cache accesses. Asserted external logic gain access external cache. Asserted 21064A indicate that external logic access external cache. Controls write enable inputs (optional) data cache backmap during 21064A controlled external cache reads.
location spare 21064.
Table describes signals which allow 21064A perform LDxL STxC transactions from external cache. Table Fast Lock Mode Signals
Signal lockWE_h1 Type Count Function 21064A able probe Bcache LDxL transaction. there Bcache hit, then 21064A will assert lockWE_h allowing external logic lock flag load lock address register. This signal line allows external logic indicate state lock flag (set clear). When 21064A performs STxC transaction, probe Bcache test this signal. signal asserted, then 21064A will perform write Bcache while asserting lockWE_h. This transaction allows external logic clear lock flag bit.
lockFlag_h2
lockWE_h
location used signal tagEq_l 21064. location used signal tagAdr_h 21064.
lockFlag_h
Table describes 21064A external cycle control signals. Table External Cycle Control Signals
Signal dOE_l dWSel_h [1:0] Type Count Function Used external logic tell 21064A drive data during external write transactions. Used external logic tell 21064A which part 32-byte block write data should driven onto data bus. Informs 21064A that read data valid data bus, indicates whether data should cached whether parity checking should attempted. Read data acknowledge types are: dRAck_h dRAck_h dRAck_h
dRAck_h [2:0]
Type IDLE NCACHE_ NCHK NCACHE NCHK
(continued next page)
Table (Cont.) External Cycle Control Signals
Signal cReq_h [2:0] Type Count Function Used 21064A specify cycle type start external cycle. cycle types are: cReq_h cReq_h cReq_h Type IDLE BARRIER FETCH FETCH_M READ_ BLOCK WRITE_ BLOCK LDL_L/ LDQ_L STL_C/ STQ_C
cWMask_h [7:0]
Supplies longword write masks external logic during write cycles; contains miss address bits other miss information during other cycles. Used external logic acknowledge external cycle. Acknowledge types are: cAck_h cAck_h cAck_h Type IDLE HARD_ ERROR SOFT_ ERROR STL_C_FAIL /STQ_C_ FAIL
cAck_h [2:0]
Table describes 21064A interrupt signals. Table Interrupt Signals
Signal irq_h [5:0] Type Count Function These signal lines have uses: During normal operation they provide types external interrupts 21064A. reset, they provide initialization information 21064A.
sysClkDiv_h1
reset, this line provides initialization information 21064A. When reset_l asserted, irq_h [4:3] encodes delay clock cycles, from sysClkOut1 sysClkOut2, follows: irq_h irq_h Delay
sysClkDiv_h location AA16 spare 21064. internal pulldown that draws maximum current
(continued next page)
Table (Cont.) Interrupt Signals
Signal Type Count Function When reset_l asserted, sysClkDiv_h irq_h [2:0] encode value divisor used generate system clock from clock, follows: sysClkDiv_h1 irq_h [2:0] Ratio
When reset_l asserted, irq_h used select 128-bit 64-bit mode. irq_h asserted, then 128-bit mode selected.
sysClkDiv_h location AA16 spare 21064. internal pulldown that draws maximum current
Table describes 21064A instruction cache initialization serial interface signals. Table Instruction Cache Initialization Serial Interface Signals
Signal icMode_h [2:0]1 Type Count Function Determines which Icache initialization mode used after reset. 21064A implements several Icache modes used Digital support chip module level testing. icMode_h [2:0] Mode Serial Disabled Digital reserved
other combinations sRomOE_l
serial mode, supplies output enable external serial ROM, serving both output enable reset. serial mode, inputs external serial data 21064A. serial mode, supplies clock external serial that causes advance next bit. signals sRomOE_l, sRomD_h, sRomClk_h also serve simple parallel pins drive diagnostic terminal. When serial being read, output signal sRomOE_l false. This means that sRomOE_l wired active high enable RS422 receiver driving onto sRomD_h active high enable RS422 driver driving from sRomClk_h. allows sRomD_h read sRomClk_h written PALcode; this sufficient hardware support implement software-driven serial interface.
sRomD_h sRomClk_h
icMode_h location spare 21064. internal pulldown that draws maximum current
Table describes initialization signal pins dcOk_h, reset_l reset_SClk_h. Table Initialization Signals
Signal dcOk_h reset_l reset_SClk_h1
reset_SClk_h
Type
Count
Function Switches clock sources between on-chip ring oscillator external clock oscillator. Forces into known state. test signal. forces system clock divider into known state.
location AA11 spare 21064. internal pulldown that draws maximum current
Table describes 21064A clock signals. Table Clock Signals
Signal clkIn_h, clkIn_l testClkIn_h, testClkIn_l cpuClkOut_h Type Count Function Supplies 21064A with differential clock from external logic. Test signals; should tied Vss, respectively. Supplies internal chip clock external interface. low-to-high transition cpuClkOut_h ``CPU clock'' used timing specification tagOk_h tagOk_l signals. Provides system clock external interface. low-to-high transition sysClkOut1_h provides system clock that used timing reference throughout this document. Provide delayed system clock external interface. delay between zero three clock cycles.
sysClkOut1_h, sysClkOut1_l
sysClkOut2_h, sysClkOut2_l
Table describes performance monitoring signals. Table Performance Monitoring Signals
Signal perf_cnt_h [1:0] Type Count Function Provides 21064A internal performance monitoring hardware with access off-chip events.
Table describes some other signals common 21064A. Table Other Signals
Signal tristate_l Type Count Function assertion this signal forces 21064A signals, with exception cpuClkOut_h, high-impedance state. assertion this signal causes 21064A connect signals Vss, with exception certain clock signals vRef. Supplies reference voltage input signal sense circuits. Digital reserved; should tied Vss.
cont_l
vRef eclOut_h
Instruction
This section provides information about instructions 21064A.
Instruction Summary
This section contains summary Alpha architecture instructions. values hexadecimal radix. Table describes contents Format Opcode columns that Table Table Instruction Format Opcode Notation
Instruction Format Branch Floatingpoint Memory Memory/ function code Memory/ branch Operate PALcode Format Symbol Opcode Notation oo.fff oo.ffff Meaning 6-bit opcode field. 6-bit opcode field. 11-bit function code field. 6-bit opcode field. 6-bit opcode field. ffff 16-bit function code displacement field. 6-bit opcode field. high-order bits displacement field. 6-bit opcode field. 7-bit function code field. 6-bit opcode field; particular PALcode instruction specified 26-bit function code field.
oo.h
oo.ff
Table shows architecture instructions. Table shows qualifiers IEEE floating-point instructions Table shows qualifiers floating-point instructions. Table Architecture Instructions
Mnemonic ADDF ADDG ADDL ADDL/V ADDQ ADDQ/V ADDS ADDT BLBC BLBS CALL_PAL CMOVEQ CMOVGE CMOVGT CMOVLBC CMOVLBS CMOVLE CMOVLT CMOVNE CMPBGE CMPEQ CMPGEQ Format Opcode 15.080 15.0A0 10.00 10.40 10.20 10.60 16.080 16.0A0 11.00 11.0 11.20 11.24 11.46 11.66 11.16 11.14 11.64 11.44 11.26 10.0F 10.2D 15.0A5 Description F_floating G_floating longword longword quadword quadword S_floating T_floating Logical product Branch zero Branch zero Branch zero clear Logical Branch clear Branch Branch zero Branch zero Branch zero Unconditional branch Branch subroutine Trap PALcode CMOVE zero CMOVE zero CMOVE zero CMOVE clear CMOVE CMOVE zero CMOVE zero CMOVE zero Compare byte Compare signed quadword equal Compare G_floating equal (continued next page)
Table (Cont.) Architecture Instructions
Mnemonic CMPGLE CMPGLT CMPLE CMPLT CMPTEQ CMPTLE CMPTLT CMPTUN CMPULE CMPULT CPYS CPYSE CPYSN CVTDG CVTGD CVTGF CVTGQ CVTLQ CVTQF CVTQG CVTQL CVTQL/SV CVTQL/V CVTQS CVTQT CVTST CVTTQ CVTTS DIVF DIVG DIVS DIVT Format Opcode 15.0A7 15.0A6 10.6D 10.4D 16.0A5 16.0A7 16.0A6 16.0A4 10.3D 10.1D 17.020 17.022 17.021 15.09E 15.0AD 15.0AC 15.0AF 17.010 15.0BC 15.0BE 17.030 17.530 17.130 16.0BC 16.0BE 16.2AC 16.0AF 16.0AC 15.083 15.0A3 16.083 16.0A3 Description Compare G_floating less than equal Compare G_floating less than Compare signed quadword less than equal Compare signed quadword less than Compare T_floating equal Compare T_floating less than equal Compare T_floating less than Compare T_floating unordered Compare unsigned quadword less than equal Compare unsigned quadword less than Copy sign Copy sign exponent Copy sign negate Convert D_floating G_floating Convert G_floating D_floating Convert G_floating F_floating Convert G_floating quadword Convert longword quadword Convert quadword F_floating Convert quadword G_floating Convert quadword longword Convert quadword longword Convert quadword longword Convert quadword S_floating Convert quadword T_floating Convert S_floating T_floating Convert T_floating quadword Convert T_floating S_floating Divide F_floating Divide G_floating Divide S_floating Divide T_floating (continued next page)
Table (Cont.) Architecture Instructions
Mnemonic EXCB EXTBL EXTLH EXTLL EXTQH EXTQL EXTWH EXTWL FBEQ FBGE FBGT FBLE FBLT FBNE FCMOVEQ FCMOVGE FCMOVGT FCMOVLE FCMOVLT FCMOVNE FETCH FETCH_M INSBL INSLH INSLL INSQH INSQL INSWH INSWL JSR_COROUTINE LDAH Format Opcode 11.48 18.0400 12.06 12.6A 12.26 12.7A 12.36 12.5A 12.16 17.02A 17.02D 17.02F 17.02E 17.02C 17.02B 18.8000 18.A000 12.0B 12.67 12.2B 12.77 12.3B 12.57 12.1B 1A.0 1A.1 1A.3 Description Logical equivalence Exception barrier Extract byte Extract longword high Extract longword Extract quadword high Extract quadword Extract word high Extract word Floating branch zero Floating branch zero Floating branch zero Floating branch zero Floating branch zero Floating branch zero FCMOVE zero FCMOVE zero FCMOVE zero FCMOVE zero FCMOVE zero FCMOVE zero Prefetch data Prefetch data, modify intent Insert byte Insert longword high Insert longword Insert quadword high Insert quadword Insert word high Insert word Jump Jump subroutine Jump subroutine return Load address Load address high Load F_floating Load G_floating (continued next page)
Table (Cont.) Architecture Instructions
Mnemonic LDL_L LDQ_L LDQ_U MF_FPCR MSKBL MSKLH MSKLL MSKQH MSKQL MSKWH MSKWL MT_FPCR MULF MULG MULL MULL/V MULQ MULQ/V MULS MULT ORNOT RPCC S4ADDL S4ADDQ S4SUBL S4SUBQ S8ADDL Format Opcode 18.4000 17.025 12.02 12.62 12.22 12.72 12.32 12.52 12.12 17.024 15.082 15.0A2 13.00 13.40 13.20 13.60 16.082 16.0A2 11.28 18.E000 1A.2 18.C000 18.F000 10.02 10.22 10.0B 10.2B 10.12 Description Load sign-extended longword Load sign-extended longword locked Load quadword Load quadword locked Load unaligned quadword Load S_floating Load T_floating Memory barrier Move from FPCR Mask byte Mask longword high Mask longword Mask quadword high Mask quadword Mask word high Mask word Move FPCR Multiply F_floating Multiply G_floating Multiply longword Multiply longword Multiply quadword Multiply quadword Multiply S_floating Multiply T_floating Logical with complement Read clear Return from subroutine Read process cycle counter Read Scaled longword Scaled quadword Scaled subtract longword Scaled subtract quadword Scaled longword (continued next page)
Table (Cont.) Architecture Instructions
Mnemonic S8ADDQ S8SUBL S8SUBQ STL_C STQ_C STQ_U SUBF SUBG SUBL SUBL/V SUBQ SUBQ/V SUBS SUBT TRAPB UMULH ZAPNOT Format Opcode 10.32 10.1B 10.3B 12.39 12.3C 12.34 15.081 15.0A1 10.09 10.49 10.29 10.69 16.081 16.0A1 18.0000 13.30 18.44 11.40 12.30 12.31 Description Scaled quadword Scaled subtract longword Scaled subtract quadword Shift left logical Shift right arithmetic Shift right logical Store F_floating Store G_floating Store S_floating Store longword Store longword conditional Store quadword Store quadword conditional Store unaligned quadword Store T_floating Subtract F_floating Subtract G_floating Subtract longword Subtract longword Subtract quadword Subtract quadword Subtract S_floating Subtract T_floating Trap barrier Unsigned multiply quadword high Write memory barrier Logical difference Zero bytes Zero bytes
IEEE Floating-Point Instructions
Table lists hexadecimal value 11-bit function code field IEEE floating-point instructions, with without qualifiers. opcode these instructions 1616 Table IEEE Floating-Point Instruction Function Codes
Mnemonic ADDS ADDT CMPTEQ CMPTLT CMPTLE CMPTUN CVTQS CVTQT CVTTS DIVS DIVT MULS MULT SUBS SUBT None
(continued next page)
Table (Cont.) IEEE Floating-Point Instruction Function Codes
Mnemonic ADDS ADDT CMPTEQ CMPTLT CMPTLE CMPTUN CVTQS CVTQT CVTTS DIVS DIVT MULS MULT SUBS SUBT Mnemonic CVTST Mnemonic CVTTQ Mnemonic CVTTQ /SUC /SUM /SUD /SUI /SUIC None None /SVD /SVID /SVC
/SUIM
/SUID
/SVI /SVM
/SVIC /SVIM
21064A IEEE Floating-Point Conformance
21064A supports IEEE floating-point operations defined Alpha architecture. Support complete implementation IEEE Standard Binary Floating-Point Arithmetic (ANSI/IEEE Standard 7541985) provided combination hardware software described Alpha Architecture Reference Manual. Additional information about writing code support precise exception handling (necessary complete conformance standard) Alpha Architecture Reference Manual. following information specific 21064A: Invalid operation (INV) invalid operation trap always enabled. trap occurs, then destination register UNPREDICTABLE. This exception signaled architecture operand non-finite (reserved operand dirty zero) operation take exception. (Certain instructions, such CPYS, never take exception.) This exception signaled IEEE operand non-finite (NAN, INF, denorm) operation take exception. This trap also signaled IEEE format divide divided exception occurs, then FPCR[INV] trap signaled Ibox. Divide zero (DZE) divide-by-zero trap always enabled. trap occurs, then destination register UNPREDICTABLE. architecture format, this exception signaled whenever numerator valid denominator zero. IEEE format, this exception signaled whenever numerator valid non-zero, with denominator exception occurs, then FPCR[DZE] trap signaled Ibox. IEEE format divides, signals INV, DZE. Floating overflow (OVF) floating overflow trap always enabled. trap occurs, then destination register UNPREDICTABLE. exception signaled rounded result exceeds magnitude largest finite number that represented destination format. This applies only operations whose destination floating-point data type. exception occurs, then FPCR[OVF] trap signaled Ibox.
Underflow (UNF) underflow trap disabled. underflow occurs, then destination register forced true zero, consisting full bits zero. This done even proper IEEE result would have been exception signaled rounded result smaller magnitude than smallest finite number that represented destination format. exception occurs, then FPCR[UNF] set. trap enabled, then trap signaled Ibox.
Inexact (INE) inexact trap disabled. destination register always contains properly rounded result, whether trap enabled. exception signaled rounded result different from what would have been produced infinite precision (infinitely wide data) were available. floating-point results, this requires both infinite precision exponent fraction. integer results, this requires infinite precision integer. exception occurs, then FPCR[INE] set. trap enabled, then trap signaled Ibox. IEEE-754 specification allows occur concurrently with either UNF. Whenever signaled inexact trap enabled), also signaled. Whenever signaled inexact trap enabled), also signaled. inexact trap also occurs concurrently with integer overflow. valid opcodes that enable also enable both overflow underflow. CVTQL results integer overflow (IOV), then FPCR[INE] automatically set. (The trap never signaled Ibox because there CVTQL opcode that enables inexact trap.) DIVx/I behavior slightly different. DIVx/I instruction does take input exception (that DZE), then Fbox calculates stores correct rounded result. Fbox calculates inexact flag, setting FPCR [INE] appropriate, trapping DIVx/SI instructions only when result really inexact.
Integer overflow (IOV) integer overflow trap disabled. destination register always contains low-order bits ([64] [32]) true result (not truncated bits). Integer overflow occur with CVTTQ, CVTGQ CVTQL. conversions from floating quadword longword integer, integer overflow occurs rounded result outside range 0263 .263 conversions from quadword integer longword integer, integer overflow occurs result outside range 0231 .231 exception occurs, then appropriate FPCR set. trap enabled, then trap signaled Ibox.
Software completion (SWC) software completion signal recorded FPCR. state this signal always sent Ibox. Ibox detects assertion listed exceptions concurrent with assertion signal, then sets EXC_SUM[SWC].
Input exceptions always take priority over output exceptions. both exception types occur, then only input exception recorded FPCR, only input exception signaled Ibox. Programming Note Because underflow cannot occur CMPTxx, there difference function performance between CMPTxx/S CMPTxx/SU. intended that software generate CMPTxx/SU place CMPTxx/S.
Floating-Point Instructions
Table lists hexadecimal value 11-bit function code field floating-point instructions, with without qualifiers. opcode these instructions 1516 Table Floating-Point Instruction Function Codes
Mnemonic ADDF CVTDG ADDG CMPGEQ CMPGLT CMPGLE CVTGF CVTGD CVTQF CVTQG DIVF DIVG MULF MULG SUBF SUBG Mnemonic CVTGQ None None /SUC /SVC
Required PALcode Function Codes
opcodes listed Table required Alpha implementations. notation used oo.ffff, where hexadecimal 6-bit opcode ffff hexadecimal 26-bit function code. Table Required PALcode Function Codes
Mnemonic DRAINA HALT Type Privileged Privileged Unprivileged Function Code 00.0002 00.0000 00.0086
Opcodes Reserved PALcode
opcodes listed Table reserved Alpha architecture used implementing PALcode 21064A. Alpha Architecture Reference Manual more information. Table Opcodes Specific 21064A
21064A Mnemonic HW_MFPR HW_MTPR HW_ST Opcode Architecture Mnemonic PAL19 PAL1D PAL1F 21064A Mnemonic HW_LD HW_REI Opcode Architecture Mnemonic PAL1B PAL1E
Opcodes Reserved Digital
Table lists opcodes that reserved Digital. Table Opcodes Reserved Digital
Mnemonic OPC01 OPC04 OPC07 OPC0D Opcode Mnemonic OPC02 OPC05 OPC0A OPC0E Opcode Mnemonic OPC03 OPC06 OPC0C OPC14 Opcode
Instructions Specific 21064A
Table lists instructions that specific 21064A. Table Instructions Specific 21064A
Mnemonic HW_MTPR HW_MFPR Operation Move data processor register Move data from processor register Load data from memory Store data memory Return from PALmode exception Type PALmode, privileged PALmode, privileged
HW_LD HW_ST HW_REI
PALmode, privileged PALmode, privileged PALmode, privileged
Programming Note PALcode uses HW_LD HW_ST instructions access memory outside realm normal Alpha memory management.
Internal Processor Registers
This section describes internal processor registers 21064A microprocessor. section organized follows: Ibox Abox Internal Processor Registers PAL_TEMP Registers Lock Registers Internal Processor Registers Reset State
21064A-275-PC, Abox Control Register SPE_1 field, described Section 4.2.11, functions differently from other four 21064A microprocessors. This register field controls memory management operation mode.
Ibox Internal Processor Registers
This section describes each Ibox internal processor register (IPR). 4.1.1 Translation Buffer Register (TB_TAG) TB_TAG register write-only register that holds next translation buffer update operation Instruction Translation Buffer (ITB) Data Translation Buffer (DTB). written temporary register transferred until Instruction Translation Buffer Page Table Entry (ITB_PTE) Data Translation Buffer Page Table Entry (DTB_PTE) register written. entry written chosen time ITB_PTE DTB_PTE write operation notlast-used algorithm, implemented hardware. Figure shows TB_TAG register format. Note Writing Instruction Translation Buffer array (ITB_TAG) only performed while PALmode, regardless state hardware enable (HWE) ICCSR register.
Figure Translation Buffer Register
Small Page Format: VA[42:13]
11(bin) Format (ITB only): VA[42:22]
LJ-01834-TI0
4.1.2 Instruction Translation Buffer Page Table Entry Register (ITB_PTE) ITB_PTE register read/write register, representing twelve page table entries split into distinct arrays. first eight page table entries provide small page byte) translations while remaining four provide large page translations. entry written chosen not-last-used algorithm implemented hardware each array independently status TB_CTL. Writes ITB_PTE register memory format positions described Alpha Architecture Reference Manual, with exception that some fields ignored. ITB's array updated simultaneously from TB_Tag register when ITB_PTE register written. Reads ITB_PTE register require instructions. first instruction sends data Instruction Translation Buffer Page Table Entry Temporary register (ITB_PTE_TEMP) second instruction, reading from ITB_PTE_TEMP register, returns entry register file. Reading writing ITB_PTE register increments entry pointer corresponding large/small page selection indicated TB_CTL, which allows reading entire ITB_PTE register entries. Figure shows ITB_PTE register format. Note Reading writing ITB_PTE register only performed while PALmode regardless state ICCSR IPR.
Figure Instruction Translation Buffer Page Table Entry Register
Write Format: PFN[33:13]
Read Format: PFN[33:13]
LJ-01835-TI0
4.1.3 Instruction Cache Control Status Register (ICCSR) ICCSR register contains various Ibox hardware enables. only architecturally defined this register floating-point enable (FPE), which enables floating-point instructions. When cleared, floating-point instructions generate exceptions entry point PALcode. Most this register cleared hardware reset. Fields that cleared reset include ASN, PC0, PC1. hardware enable allows special privileged architecture library code (PALcode) instructions execute kernel mode. This intended diagnostic operating system alternative PALcode routines only. does allow access registers running PALmode. Figure shows ICCSR register format. Table lists ICCSR register fields brief description. Table lists branch states controlled Branch Prediction Enable (BPE) Branch History Enable (BHE) bits ICCSR.
Figure ICCSR Register
Write Format: ASN[5:0]
MUX1 [2:0]
MUX0 [3:0]
Read Format: [5:2] MUX0 [3:0]
LJ-01836-TI0A
ASN[5:0]
MUX1 [2:0]
Table ICCSR Fields Description
Field Type Description field used conjunction with Icache further qualify cache entries avoid some cache flushes. written Icache during fill operations compared with I-stream data fetch operations. Mismatches invalidate fetch without affecting Icache. (See Alpha Architecture Reference Manual.) state bits reserved Digital should used software. both these bits clear, they disable both performance counters. either set, both performance counters will increment their usual fashion. set, floating-point instructions issued. clear, floatingpoint instructions cause exceptions. set, allows superpage I-stream memory mapping virtual [33:13] directly Physical [33:13] essentially bypassing virtual addresses containing virtual [42:41] Superpage mapping allowed kernel mode only. Icache always set. clear, superpage mapping disabled. (continued next page)
RW,0
RW,0 RW,0
Table (Cont.) ICCSR Fields Description
Field Type RW,0 Description set, allows five reserved opcodes (PAL19, PAL1B, PAL1D, PAL1E, PAL1F) instructions issued kernel mode. cleared, attempts execute reserved opcodes instructions while PALmode result OPCDEC exceptions. set, enables dual issue. cleared, instructions only single issue. Used conjunction with BPE. Table programming information. set, enables stack push return address. cleared, stack disabled. Used conjunction with BHE. Table programming information. clear, causes hardware interlocked instructions drain machine waits write buffer empty before issuing next instruction. Examples instructions that cause pipe drain include HW_MTPR, HW_REI, conditional branches, instructions that have destination register R31. set, pipeline proceeds normally. Table programming information. Table programming information. clear, enables performance counter interrupt request after events counted. set, enables performance counter interrupt request after events counted. clear, enables performance counter interrupt request after events counted. set, enables performance counter interrupt request after events counted.
PIPE
RW,0 RW,0 RW,0 RW,0 RW,0
PCMUX1 PCMUX0
RW,0 RW,0
Note Using HW_MTPR instruction update EXC_ADDR register while native mode restricted being equal combination native mode EXC_ADDR being equal causes UNDEFINED behavior. This combination only possible through bit.
Table BHE, Branch Prediction Selection (Conditional Branches Only)
Prediction Taken Sign Displacement Branch History Table
4.1.3.1 Performance Counters performance counters reset zero upon powerup. Otherwise, they never cleared. counters intended means counting events over long period time, relative event frequency. They provide means extracting intermediate counter values. performance counters enabled disabled using ICCSR [45:44] (PCE [1:0]). Since counters continuously accumulate selected events, despite interrupts being enabled, first interrupt after selecting counter input error bound large selected overflow range. Some inputs over count events occurring simultaneously with D-stream errors that abort actual event very late pipeline. example, when counting load instructions, attempts execute load resulting miss exception will increment performance counter after first aborted execution attempt again after fill routine when load instruction reissues completes. Performance counter interrupts reported cycles after event that caused counter overflow. Additional delay occur before interrupt serviced, processor executing PALcode that always disables interrupts. Events occurring during interval between counter overflow interrupt service counted toward next interrupt. Only case complete counter wraparound while interrupts disabled will interrupt missed. cycles before interrupt triggered implies that maximum instructions have completed before start interrupt service routine. When counting Icache misses, intervening instructions complete exception contains address last Icache miss. Branch mispredictions allow maximum only instructions complete before start interrupt service routine.
Table lists performance counter inputs Table lists performance counter inputs. Table Performance Counter Input Selection ICCSR)
MUX0 [3:0] 000X 001X Input Total Issues/2 Pipeline Comment Counts total issues divided dual issue increments count Counts cycles where nothing issued lack valid I-stream data. Causes include Icache fill, misprediction, branch delay slots, pipeline drain exception. Count Load instructions. Counts cycles where nothing issued resource conflict. Counts conditional branches, unconditional branches, JSR, HW_REI instructions. Counts cycles while executing PALmode. Counts total cycles. Counts total non-issues divided ("no issue" increments count Counts external events supplied selected system clock cycle interval.
010X 011X 100X
Load Instructions Pipeline Frozen Branch Instructions
1011 1010 110X 111X
PALmode Total cycles Total Non-issues/2 PERF_CNT_H
Table Performance Counter Input Selection ICCSR)
MUX1 [2:0] Input Dcache miss Icache miss Dual issues Branch Mispredicts Comment Counts total Dcache misses. Counts total Icache misses. Counts cycles Dual issue. Counts both conditional branch mispredictions HW_REI mispredictions. Conditional branch mispredictions cost cycles others cost cycles pipeline delay. Counts total floating-point operate instructions, that branch, load, store. Counts integer operate instructions including LDAH with destination other than R31. Counts total store instructions. Counts external events supplied selected system clock cycle interval.
Instructions
Integer Operate
Store Instructions PERF_CNT_H
4.1.4 Instruction Translation Buffer Page Table Entry Temporary Register (ITB_PTE_TEMP) ITB_PTE_TEMP register read-only holding register ITB_PTE read data. Reads ITB_PTE register require instructions return data register file. instructions follows: Read ITB_PTE register data ITB_PTE_TEMP register. Read ITB_PTE_TEMP register data integer register file. ITB_PTE_TEMP register updated accesses, both read write. read ITB_PTE ITB_PTE_TEMP should followed closely read ITB_PTE_TEMP register file. Figure shows ITB_PTE_TEMP register format. Note Reading ITB_PTE_TEMP register only performed while PALmode regardless state ICCSR.
Figure ITB_PTE_TEMP Register
PFN[33:13]
LJ-01837-TI0
4.1.5 Exceptions Address Register (EXC_ADDR) EXC_ADDR register read/write register used restart system after exceptions interrupts. register read written software, HW_MTPR instruction. Also, EXC_ADDR written directly hardware. HW_REI instruction executes jump address contained EXC_ADDR register. EXC_ADDR register written hardware after exception provide return address PALcode. instruction pointed EXC_ADDR register complete execution. EXC_ADDR register used indicate PALmode hardware. When clear, HW_REI instruction executes jump native (non-PAL) mode, enabling address translation. CALL_PAL exceptions load EXC_ADDR with instruction following CALL_PAL. This function allows CALL_PAL service routines return without needing increment value EXC_ADDR register. This feature requires careful treatment PALcode. Arithmetic traps machine check exceptions preempt CALL_PAL exceptions resulting incorrect value being saved EXC_ADDR register. cases arithmetic trap machine check exception (only these cases), EXC_ADDR takes special meaning. PALcode servicing these exceptions must: Interpret EXC_ADDR indicating that EXC_ADDR [63:2] large value bytes subtract before executing HW_REI from this address. Interpret EXC_ADDR indicating that EXC_ADDR [63:2] correct clear value EXC_ADDR [1].
other PALcode entry points except reset expect EXC_ADDR
logic allows following code sequence conditionally subtract from address EXC_ADDR register without additional register. This code sequence must present arithmetic trap machine check flows only. HW_MFPR SUBQ HW_MTPR EXC_ADDR 2,Rx 2,Rx EXC_ADDR read EXC_ADDR into subtract causing borrow [1]=0 clear write back EXC_ADDR
Figure shows exception address register format. Figure Exception Address Register
PC[63:2]
LJ-01838-TI0
4.1.6 Clear Serial Line Interrupt Register (SL_CLR) SL_CLR write-only register that clears the: Serial line interrupt request Performance counter interrupt requests interrupt request
indicated must written with zero clear selected interrupt source. Figure shows clear serial line interrupt register format. Table lists register fields description. Figure Clear Serial Line Interrupt Register
LJ-01839-TI0
Table Clear Serial Line Interrupt Register Fields
Field Type Description Clears correctable read error interrupt request Clears performance counter interrupt request Clears performance counter interrupt request Clears serial line interrupt request
4.1.7 Serial Line Receive Register (SL_RCV) SL_RCV register contains single read-only (RCV). This used with interrupt control registers, sRomD_h pin, sRomClk_h provide on-chip serial line function. functionally connected sRomD_h after Icache loaded from external serial ROM. Using software timing loop, read receive external data time. serial line interrupt requested detection transition receive line that sets HIRR. serial line interrupt disabled clearing HIER register bit. Figure shows Serial Line Receive Register format. Figure Serial Line Receive Register
LJ-01840-TI0
4.1.8 Instruction Translation Buffer Register (ITBZAP) write this register invalidates twelve instruction translation buffer (ITB) entries. also resets both pointers their initial state. ITBZAP register only written PALmode.
4.1.9 Instruction Translation Buffer Register (ITBASM) write this register invalidates entries, which ITB_PTE equal zero. ITBASM register only written PALmode. 4.1.10 Instruction Translation Buffer Register (ITBIS) write ITBIS register invalidates twelve entries. also resets both pointers their initial state. ITBIS register only written PALmode. This register functions same ITBZAP register. 4.1.11 Processor Status Register (PS) register read/write register containing only current mode bits architecturally defined Figure shows register format. Alpha Architecture Reference Manual additional information. Figure Processor Status Register
Write Format:
Read Format:
LJ-01841-TI0
4.1.12 Exception Summary Register (EXC_SUM) EXC_SUM register records various types arithmetic traps that occurred since last time EXC_SUM written (cleared). When result arithmetic operation produces arithmetic trap, corresponding EXC_SUM set. register containing result operation recorded exception register write mask parameter, single 64-bit shift register specifying registers F31-F0 I31-I0. EXC_SUM register provides one-bit window exception register write mask parameter. This visible only through EXC_SUM register.
Each read EXC_SUM shifts order F31-F0 then I31-I0. read also clears corresponding bit. EXC_SUM must read times extract complete mask clear entire register. integer traps present (IOV=0), only first corresponding floating-point register bits need read cleared. write EXC_SUM clears bits [8:2] does affect write mask bit. Write Mask register clears three cycles after read. Code intended read register must allow least three cycles between reads. This allows clear shift operations complete order ensure reading successive bits. Figure shows exception summary register format. Table lists register fields descriptions. Figure Exception Summary Register
LJ-01842-TI0
Table Exception Summary Register Fields
Field Type Description Indicates software completion possible. after floating-point instruction containing modifier completes with arithmetic trap previous floating-point instructions that trapped since last MTPR EXC_SUM also contained modifier. cleared whenever floating-point instruction without modifier completes with arithmetic trap. remains cleared regardless additional arithmetic traps until register written HW_MTPR instruction. always cleared upon HW_MTPR write EXC_SUM register. Indicates invalid operation. Indicates divide zero. Indicates floating-point overflow. Indicates floating-point underflow. Indicates floating inexact error. Indicates Fbox convert integer overflow integer arithmetic overflow. Exception Register Write Mask window.
4.1.13 PAL_BASE Address Register (PAL_BASE) PAL_BASE register read/write register containing base address PALcode. This register cleared hardware reset. Figure shows PAL_BASE address register format. Figure PAL_BASE Address Register
IGN/RAZ PAL_BASE[33:14] IGN/RAZ
LJ-01843-TI0
4.1.14 Hardware Interrupt Request Register (HIRR) HIRR read-only register providing record currently outstanding interrupt requests summary bits time read. each HIRR [5:0], there corresponding Hardware Interrupt Enable register (HIER) that must request interrupt. addition returning status hardware interrupt requests, read HIRR returns state software interrupt requests. Note read HIRR return value zero hardware interrupt released before read (passive release).
register guarantees that reflects status shown HIRR bits. interrupt requests blocked while executing PALmode. Figure shows hardware interrupt request register format. Table lists register fields gives description each.
Figure Hardware Interrupt Request Register
SIRR [15:1]
LJ-01844-TI0
USEK ASTRR [3:0]
HIRR [2:0]
HIRR [5:3]
Table Hardware Interrupt Request Register Fields
Field Type Description hardware interrupt request corresponding enable software interrupt request corresponding enable request corresponding enable set. This also requires that processor mode equal higher than request mode. SIER must allow interrupt requests. correctable read error interrupt request. This interrupt cleared SL_CLR register. Contains delayed copies Irq_h [5:0] pins Performance counter interrupt request Performance counter interrupt request Serial line interrupt request. Also SL_RCV, XMIT, SL_CLR Corresponds software interrupt request through Corresponds request through (USEK)
HIRR [5:0] SIRR [15:1] ASTRR [3:0]
4.1.15 Software Interrupt Request Register (SIRR) SIRR read/write register used control software interrupt requests. each SIRR, there corresponding Software Interrupt Enable register (SIER) that must request interrupt. Reads SIRR return complete interrupt request registers summary bits (see Table details). interrupt requests blocked while executing PALmode. Figure shows SIRR format. Figure Software Interrupt Request Register
Write Format: SIRR[15:1]
Read Format: SIRR [15:1]
LJ-01845-TI0
USEK ASTRR [3:0]
HIRR [2:0]
HIRR [5:3]
4.1.16 Asynchronous Trap Request Register (ASTRR) ASTRR read/write register. contains bits request interrupts each processor modes. generate interrupt, corresponding enable ASTER must set. Also, processor must selected processor mode higher privilege described current value bits. interrupts enabled SIER set. This provides mechanism lock requests over certain levels. interrupt requests blocked while executing PALmode. Reads ASTRR return complete interrupt request registers summary bits. Table details. Figure shows ASTRR format. Figure Asynchronous Trap Request Register
Write Format:
Read Format: SIRR [15:1]
LJ-01846-TI0
USEK ASTRR [3:0]
HIRR [2:0]
HIRR [5:3]
4.1.17 Hardware Interrupt Enable Register (HIER) HIER read/write register. used enable corresponding bits HIRR requesting interrupt. PC0, PC1, SLE, bits this register enable the: Performance counters Serial line Correctable read interrupts
There one-to-one correspondence between interrupt requests enable bits. with reads interrupt request registers, reads HIER return complete interrupt enable registers. Table details. Figure shows hardware interrupt enable register format. Table lists register fields description each. Figure Hardware Interrupt Enable Register
Write Format: HIER[5:0]
Read Format: SIER [15:1]
LJ-01847-TI0
HIER [2:0]
HIER [5:3]
Table Hardware Interrupt Enable Register Fields
Field HIER [5:0] SIER [15:1] ASTER [3:0] Type Description Interrupt enables pins Irq_h [5:0] Corresponds software interrupt requests through Corresponds ASTRR enable through (USEK) Performance counter interrupt enable (continued next page)
Table (Cont.) Hardware Interrupt Enable Register Fields
Field Type Description Performance counter interrupt enable Serial line interrupt enable Also SL_RCV, SL_XMIT, SL_CLR correctable read error interrupt enable This interrupt request cleared SL_CLR register
4.1.18 Software Interrupt Enable Register (SIER) SIER read/write register. used enable corresponding bits SIRR requesting interrupts. There one-to-one correspondence between interrupt requests enable bits. with reads interrupt request registers, reads SIER return complete interrupt enable registers. Table details. Figure shows software interrupt enable register format. Figure Software Interrupt Enable Register
Write Format: SIER[15:1]
Read Format: SIER [15:1]
LJ-01848-TI0
HIER [2:0]
HIER [5:3]
4.1.19 Interrupt Enable Register (ASTER) ASTER read/write register. used enable corresponding bits ASTRR requesting interrupts. There one-to-one correspondence between interrupt requests enable bits. with reads interrupt request registers, reads ASTER return complete interrupt enable registers. Table details. Figure shows ASTER format. Figure Interrupt Enable Register
Write Format:
Read Format: SIER [15:1]
LJ-01849-TI0
HIER [2:0]
HIER [5:3]
4.1.20 Serial Line Transmit Register (SL_XMIT) SL_XMIT register contains single write-only bit. This used with interrupt control registers, sRomD_h pin, sRomClk_h provide on-chip serial line function. functionally connected sRomClk_h after Icache loaded from external serial ROM. Writing used transmit data chip, time under software timing loop. Figure shows SL_XMIT register format.
Figure Serial Line Transmit Register
LJ-01850-TI0
Abox Internal Processor Registers
following sections describe Abox internal processor registers. 4.2.1 Translation Buffer Control Register (TB_CTL) granularity hint (GH) field selects between page mapping sizes. There sizes four sizes DTB. When only sizes provided, large-page-select (GH=11(bin)) field selects largest mapping size (512 KB). other values select smallest size. field affects both reads writes DTB. Figure shows translation buffer control register format. Alpha Architecture Reference Manual additional information. Figure Translation Buffer Control Register
LJ-01851-TI0
4.2.2 Data Translation Buffer Page Table Entry Register (DTB_PTE) DTB_PTE register read/write register representing 32-entry DTB. entry written chosen not-last-used (NLU) algorithm implemented hardware. round robin (DTB_RR) algorithm selected setting ABOX_CTL [9]. Writes DTB_PTE memory format positions described Alpha Architecture Reference Manual with exception that some fields ignored. valid represented hardware.
DTB's array updated simultaneously from TB_Tag register when DTB_PTE register written. Reads DTB_PTE require instructions. first instruction sends data Data Translation Buffer Page Table Entry Temporary register (DTB_PTE_TEMP). second instruction, reading from DTB_PTE_TEMP register, returns entry register file. Reading writing DTB_PTE register increments entry pointer DTB, which allows reading entire DTB_PTE entries. Figure shows DTB_PTE register format. Figure Data Translation Buffer Page Table Entry Register
PFN[33:13]
LJ-01852-TI0
4.2.3 Data Translation Buffer Page Table Entry Temporary Register (DTB_PTE_TEMP) DTB_PTE_TEMP register read-only holding register DTB_PTE read data. Reads DTB_PTE require instructions return data register file. instructions follows: Read DTB_PTE register data DTB_PTE_TEMP register. Read DTB_PTE_TEMP register data integer register file.
Figure shows DTB_PTE_TEMP register format. Figure Data Translation Buffer Page Table Entry Temporary Register
PFN[33:13]
LJ-01853-TI0
4.2.4 Memory Management Control Status Register (MM_CSR) When D-stream faults occur information about fault latched saved MM_CSR register. virtual address register (VA) MM_CSR registers locked against further updates until software reads Virtual Address register. PALcode must explicitly unlock this register whenever entry point higher priority than miss. MM_CSR bits only modified hardware when register locked memory management error miss occurs. MM_CSR unlocked after reset. Figure shows MM_CSR register format. Table lists register fields brief description. Figure Memory Management Control Status Register
OPCODE
LJ-01854-TI0
Table Memory Management Control Status Register
Field OPCODE Type Description reference that caused error write. reference caused access violation. reference read PTE's set. reference write PTE's set. field faulting instruction. Opcode field faulting instruction.
4.2.5 Virtual Address Register (VA) When D-stream faults misses occur, effective virtual address associated with fault miss latched read-only register. MM_CSR registers locked against further updates until software reads register. register unlocked after reset. PALcode must explicitly unlock this register whenever entry point higher priority than miss. 4.2.6 Data Translation Buffer Register (DTBZAP) DTBZAP pseudo-register. write this register invalidates entries. also resets not-last-used (NLU) pointer initial state. 4.2.7 Data Translation Buffer Register (DTBASM) DTBASM pseudo-register. write this register invalidates entries which equal zero. 4.2.8 Data Translation Buffer Invalidate Single Register (DTBIS) write this pseudo-register will invalidate entry, which maps virtual address held integer register. integer register identified field HW_MTPR instruction, used perform write. 4.2.9 Flush Instruction Cache Register (FLUSH_IC) write this pseudo-register flushes entire instruction cache. 4.2.10 Flush Instruction Cache Register (FLUSH_IC_ASM) write this pseudo-register invalidates Icache blocks which clear.
4.2.11 Abox Control Register (ABOX_CTL) Figure shows Abox control register format. Table lists register fields descriptions. Figure Abox Control Register
WB_DIS MCHK_EN CRD_EN IC_SBUF_EN SPE_1 SPE_2 EMD_EN STC_NORESULT NCAHCE_NDISTURB DTB_RR DC_ENA DC_FHIT DC_16K F_TAG_ERR NOCHK_PAR DOUBLE_INVAL
MLO-012194
Table Abox Control Register Fields
Field WB_DIS Type WO,0 Description Write Buffer unload Disable. When set, this prevents write buffer from sending write data BIU. should diagnostics only. (continued next page)
Table (Cont.) Abox Control Register Fields
Field MCHK_EN Type WO,0 Description Machine Check Enable. When this set, Abox generates machine check when errors (which correctable hardware) encountered. When this cleared, uncorrectable errors cause machine check. However, BIU_STAT, DC_STAT, BIU_ADDR, FILL_ADDR registers updated locked when errors occur. Corrected read data interrupt enable. When this set, Abox generates interrupt request whenever transaction terminated with cAck_h code SOFT_ERROR. Icache stream buffer enable. When set, this enables operation single entry Icache stream buffer. When this set, enables one-to-one superpage mapping D-stream virtual addresses with [42:30] 1FFE (Hex) physical addresses with [33:30] (Hex). Access only allowed kernel mode.
CRD_EN
WO,0
IC_SBUF_EN SPE_1
WO,0 WO,0
Note 21064A-275-PC this must always when virtual-to-physical mapping enabled. Operation native mode (not PALmode) with this clear will will cause 21064A-275-PC operation UNPREDICTABLE.
SPE_2 WO,0 When this set, enables one-to-one super page mapping D-stream virtual addresses with [33:13] directly physical addresses [33:13], virtual address bits [42:41] Virtual address bits [40:34] ignored this translation. Access only allowed kernel mode. Limited hardware support provided endian data formats ABOX_CTL register. When set, this inverts physical address D-stream references. intended that chip endian mode selected during initialization PALcode only. (continued next page)
EMD_EN
WO,0
Table (Cont.) Abox Control Register Fields
Field Type Description When clear 21064A implements lock operation conformance Alpha Architecture. When 21064A does conform Alpha architecture. following items. When STC_NORESULT these items apply. result written into register identified STL_ C/STQ_C HW_ST/C instructions UNPREDICTABLE. This allows Ibox restart memory reference pipeline when STL_C/STQ_C transferred from write buffer BIU, increases repetition rate with which STL_C/STQ_C instructions processed. LDL_L/LDQ_L, STL_C/STQ_C HW_ST/C instructions will invalidate Dcache line associated with their generated address. These invalidates will visible load store instructions that issue cycles after LDL_L/LDQ_L, STL_C/STQ_C HW_ST/C issues.
STC_NORESULT WO,0
This cleared chip reset. NCACHE_ NDISTURB DTB_RR2 DC_ENA DC_FHIT WO,0 When this set, enables mode which make noncacheable only those external reads which 21064A does probe external cache. This cleared chip reset. When this set, selects round robin replacement algorithm DTB. Dcache enable. When clear, this disables flushes Dcache. When set, this enables Dcache. Dcache force hit. When set, this forces D-stream references Dcache. This takes precedence over DC_ENA. That when DC_FHIT DC_ENA clear D-stream references Dcache. select byte Dcache. Clear select byte Dcache. generate Dcache parity fills. disable checking Icache Dcache parity. When set, asserting dInvReq_h invalidates both Dcache blocks addressed iAdr_h [12:5].
WO,0 WO,0 WO,0
DC_16K F_TAG_ERR NOCHK_PAR DOUBLE_ INVAL
WO,0 WO,0 WO,0 WO,0
4.2.12 Alternate Processor Mode Register (ALT_MODE) ALT_MODE write-only register. field specifies alternate processor mode used HW_LD HW_ST instructions that have their (bit [14]) set. Figure shows alternate processor mode register format Table lists register modes. Figure Alternate Processor Mode Register
LJ-01856-TI0
Table Alternate Processor Mode Register
ALT_MODE [4:3] Mode Kernel Executive Supervisor User
4.2.13 Cycle Counter Register (CC) 21064A supports cycle counter, described Alpha Architecture Reference Manual. When enabled, increments once each cycle. HW_MTPR writes [63:32] with value held [63:32]. [31:0] changed. This register read RPCC instruction defined Alpha Architecture Reference Manual. Figure shows register format (top register) when read HW_MFPR instruction when written (bottom register) HW_MTPR instruction.
Figure Cycle Counter Register
Read Format: OFFSET COUNTER
Write Format: OFFSET
LJ-02162-TI0
4.2.14 Cycle Counter Control Register (CC_CTL) HW_MTPR CC_CTL writes [31:0] with value held [31:0]. register bits [63:32] changed. register bits [3:0] must written with zero. [32] set, then counter enabled, otherwise counter disabled. CC_CTL write-only register. Figure shows register format when written HW_MTPR CC_CTL instruction. Figure Cycle Counter Control Register
CC_CTL Register Format COUNTER ENABLE
LJ-02161-TI0
4.2.15 Interface Unit Control Register (BIU_CTL) Figure shows interface unit control register format. Table lists register fields gives description each. Figure 21064A Interface Unit Control Register
BC_WE_CTL [15:1]
BC_ENA BC_FHIT BC_RD_SPD BC_WR_SPD
DELAY_WDATA
BC_SIZE BAD_TCP BC_PA_DIS BAD_DP
BYTE_PARITY SYS_WRAP IMAP_EN BC_BURST_SPD BC_BURST_ALL FAST_LOCK
MLO-012196
Table Interface Unit Control Register Fields
Field BC_ENA Type WO,0 Description External cache enable. When this cleared, disables external cache. When Bcache disabled, does probe external cache store read/write references; launches request cReq_h immediately. (continued next page)
Table (Cont.) Interface Unit Control Register Fields
Field Type WO,0 Description When this clear, 21064A generates/expects parity four check_h pins. When this set, 21064A generates/expects check_h pins. When this set, 21064A does assert chip enable pins during write cycles, thus enabling these pins connected output enable pins cache RAMs.
WO,0
Caution output enable BIU_CTL register (BIU_CTL [2]) must system uses SRAMs output enable mode (that tagCEOE and/or dataCEOE signals connected output enable input SRAM 21064A enable always enabled). this inadvertently cleared, data SRAMs will enabled during writes, damage result.
BC_FHIT WO,0 External cache force hit. When this BC_ENA also set, READ_BLOCK WRITE_BLOCK transactions forced external cache. control parity ignored. BC_ENA takes precedence over BC_FHIT. When BC_ENA cleared BC_FHIT set, probes occur external requests directed cReq_h pins.
Note BC_PA_DIS field takes precedence over BC_FHIT bit.
(continued next page)
Table (Cont.) Interface Unit Control Register Fields
Field BC_RD_SPD Type WO,0 Description External cache read speed. This field indicates read access time RAMs used implement off-chip external cache, measured cycles. should written with value equal less than read access time external cache RAMs. 21064A access times reads must range [16:3] cycles, which means values BC_RD_SPD field range [15:2]. BC_WR_SPD WO,0 External cache write speed. This field indicates write cycle time RAMs used implement off-chip external cache, measured cycles. should written with value equal less than write cycle time external cache RAMs. access times writes must range [16:2] cycles, which means values BC_WR_SPD field range [15:1]. DELAY_WDATA BC_WE_CTL WO,0 WO,0 When this set, changes timing data during external cache writes. External cache write enable control. This field used control timing write enable chip enable pins during writes into data control RAMs. consists bits, where each determines value placed write enable chip enable pins during given cycle write access. When given BC_WE_CTL set, write enable chip enable pins asserted during corresponding cycle access. BC_WE_CTL (bit [13] BIU_CTL) corresponds second cycle write access, BC_WE_CTL (bit [14] BIU_CTL) third cycle, write enable pins will never asserted first cycle write access. Unused bits BC_WE_CTL field must written with zeros. BC_SIZE BAD_TCP WO,0 WO,0 This field used indicate size external cache. Table encodings. When set, this causes 21064A write parity into control whenever does fast external write. (Diagnostic only.) (continued next page)
Table (Cont.) Interface Unit Control Register Fields
Field BC_PA_DIS Type WO,0 Description This 4-bit field used prevent chip from using external cache service reads writes based upon quadrant physical address space that they reference. correspondence between this field physical address space shown Table When read write reference presented values BC_PA_DIS, BC_ENA, physical address bits [33:32] determine whether attempt external cache satisfy reference. external cache used given reference does probe store makes appropriate system request immediately. value BC_PA_DIS impact which portions physical address space cached primary caches. System components control this dRAck_h field bus. BAD_DP WO,0 When this set, BAD_DP causes 21064A invert value placed bits [0], [7], [14] [21] check_h [27:0] field during off-chip writes. This produces parity when 21064A parity mode, check codes when mode. (Diagnostic only.) When this set, indicates that system returns read response data wrapped around requested chunk. This cleared chip reset. When these bits cleared, timing Bcache reads controlled value BC_RD_SPD. When these bits 128-bit mode, second read takes BC_BURST_SPD+1 cycles. When these bits 64-bit mode, second fourth reads take BC_BURST_SPD+1 cycles. BC_BURST_ALL set, third read takes BC_BURST_ SPD+1 cycles also. 64-bit mode this BC_BURST_SPD should used time third four) read cycle. when BIU_CTL cleared, external byte parity selected. when BIU_CTL set, this ignored. allow dMapWE_h [1:0] assert I-stream backup cache reads. (continued next page)
SYS_WRAP
WO,0
BC_BURST_SPD
WO,0
BC_BURST_ALL
WO,0
BYTE_PARITY
WO,0
IMAP_EN
WO,0
Table (Cont.) Interface Unit Control Register Fields
Field FAST_LOCK Type WO,0 Description When set, FAST_LOCK mode operation selected. FAST_ LOCK mode only used when BIU_CTL also indicating that mode Bcache RAMs used.
Table lists encoding BC_SIZE. Table lists BIU_CTL physical addresses. Table BC_SIZE
BC_SIZE Cache Size BC_SIZE Cache Size
Table BC_PA_DIS
BIU_CTL Bits Physical Address [33:32] [33:32] BIU_CTL Bits Physical Address [33:32] [33:32]
4.2.16 Cache Status Register (C_STAT) C_STAT read-only register only used diagnostics. Figure shows 21064A Dcache status register format. Table lists register fields gives description each. Figure Cache Status Register
CHIP_ID
DC_HIT DC_ERR IC_ERR
MLO-012195
Table Cache Status Register Fields
Field CHIP_ID Type Description These bits identify devices listed here: DC_HIT 0012 -Early version 21064A 0112 -Production version 21064A
This indicates whether last load store instruction processed Abox (DC_HIT set) missed (DC_HIT clear) Dcache. Loads that miss Dcache completed without requiring external reads. (Diagnostic only.) Dcache parity error. Icache parity error.
DC_ERR IC_ERR
4.2.17 Interface Unit Status Register (BIU_STAT) BIU_STAT read-only register. Bits [6:0] BIU_STAT register locked against further updates when following bits set: BIU_HERR BIU_SERR BC_TPERR BC_TCPERR
address associated with error latched locked BIU_ ADDR register. Bits [6:0] BIU_STAT register BIU_ADDR also spuriously locked when parity error uncorrectable error occurs during primary cache fill operation. BIU_STAT bits [7:0] BIU_ ADDR unlocked when BIU_ADDR register read. When FILL_ECC FILL_DPERR set, BIU_STAT bits [13:8] locked against further updates. address associated with error latched locked FILL_ADDR register. BIU_STAT bits [14:8] FILL_ADDR unlocked when FILL_ADDR register read. This register unlocked cleared reset needs explicitly cleared PALcode. Figure shows interface unit status register format. Table lists register fields gives description each.
Figure Interface Unit Status Register
BIU_HERR BIU_SERR BC_TPERR BC_TCPERR BIU_CMD FATAL FILL_ECC FILL_CRD FILL_DPERR FILL_IRD FILL_QW FATAL
LJ-02123-TI0
Table Interface Unit Status Register Fields
Field BIU_HERR Type Description When this set, indicates that external cycle terminated with cAck_h pins indicating HARD_ ERROR. When this set, indicates that external cycle terminated with cAck_h pins indicating SOFT_ ERROR. When this set, indicates that external cache probe encountered parity address RAM. When this set, indicates that external cache probe encountered parity control RAM. This field latches cycle type cReq_h pins when BIU_HERR, BIU_SERR, BC_TPERR, BC_TCPERR error occurs. (continued next page)
BIU_SERR
BC_TPERR
BC_TCPERR BIU_CMD
Table (Cont.) Interface Unit Status Register Fields
Field FATAL1 Type Description When this set, indicates that external cycle terminated with cAck_h pins indicating HARD_ ERROR that external cache probe encountered parity address control while BIU_HERR, BIU_SERR, BC_TPERR, BC_TCPERR already set. error. When this set, indicates that primary cache fill data received from outside chip contained error. Correctable read. This only meaning when FILL_ set. When this set, indicates that information latched BIU_STAT [13:8], FILL_ADDR, FILL_SYNDROME relates error quadword which does contain multi-bit errors either component longwords. Fill Parity Error. When this set, indicates that received data with parity error from outside chip while performing either Dcache Icache fill. FILL_DPERR only meaningful when chip parity mode, opposed mode. This only meaningful when either FILL_ECC FILL_DPERR set. FILL_IRD indicate that error that caused FILL_ECC FILL_DPERR occurred during Icache fill clear indicate that error occurred during Dcache fill. This field only meaningful when either FILL_ECC FILL_DPERR set. FILL_QW identifies quadword within hexaword primary cache fill block which caused error. used together with FILL_ADDR [33:5] complete physical address quadword. When this set, indicates that primary cache fill operation resulted either multi-bit error parity error while FILL_ECC FILL_DPERR already set.
FILL_ECC
FILL_CRD
FILL_DPERR
FILL_IRD
FILL_QW
FATAL2
4.2.18 Interface Unit Address Register (BIU_ADDR) BIU_ADDR read-only register that contains physical address associated with errors reported BIU_STAT [7:0]. contents meaningful only when BIU_HERR, BIU_SERR, BC_TPERR, BC_TCPERR set. Reads BIU_ADDR register unlock both BIU_ADDR BIU_STAT [7:0]. BIU_ADDR bits [33:5] contain values adr_h bits [33:5] associated with transaction that resulted error indicated BIU_STAT [7:0]. BIU_CMD field BIU_STAT register indicates that transaction that received error READ_BLOCK load_locked, then BIU_ADDR [4:2] UNPREDICTABLE. BIU_CMD field BIU_STAT register encodes command other than READ_BLOCK load_locked, then BIU_ADDR bits [4:2] will contain zeros. BIU_ADDR bits [63:34] BIU_ ADDR bits [1:0] always read zero. Figure shows interface unit address register (BIU_ADDR) format. Figure Interface Unit Address Register
BIU_ADDR Register Format ADDRESS RB/LL
LJ-02160-TI0
4.2.19 Fill Address Register (FILL_ADDR) FILL_ADDR read-only register that contains physical address associated with errors reported BIU_STAT bits [14:8]. contents meaningful only when FILL_ECC FILL_DPERR set. Reads FILL_ ADDR unlock FILL_ADDR, BIU_STAT bits [14:8] FILL_SYNDROME. FILL_ADDR bits [33:5] identify 32-byte cache block that attempting read when error occurred. FILL_IRD BIU_STAT register clear, indicates that error occurred during D-stream cache fill. such times, FILL_ADDR bits [4:2] contain bits [4:2] physical address generated load instruction that triggered cache fill. FILL_IRD set, then FILL_ADDR bits [4:2] UNPREDICTABLE. FILL_ADDR bits [63:34] FILL_ADDR bits [1:0] will read zero. Figure shows fill address register (FILL_ADDR) format. Figure Fill Address Register
Fill_ADDR Register Format ADDRESS
LJ-02159-TI0
4.2.20 Fill Syndrome Register (FILL_SYNDROME) FILL_SYNDROME register 14-bit read-only register. chip mode error recognized during primary cache fill operation, syndrome bits associated with quadword locked FILL_SYNDROME register. FILL_SYNDROME bits [6:0] contain syndrome associated with lower longword quadword, FILL_SYNDROME bits [13:7] contain syndrome associated with upper longword quadword. syndrome value zero means that errors were found associated longword. Table list syndromes associated with correctable single-bit errors. FILL_SYNDROME register unlocked when FILL_ADDR register read. chip parity mode parity error recognized during primary cache fill operation, FILL_SYNDROME register indicates which longwords quadword parity. FILL_SYNDROME indicate that lower longword corrupted, FILL_SYNDROME indicate that upper longword corrupted. FILL_ SYNDROME bits [13:8] [6:1] parity mode. Figure shows fill syndrome register format. Figure FILL_SYNDROME Register
HI[6:0] LO[6:0]
LJ-01860-TI0
Table Syndromes Single-Bit Errors
Data Syndrome (Hex) Data Syndrome (Hex) Check Syndrome (Hex)
4.2.21 Backup Cache Register (BC_TAG) BC_TAG read-only register. Unless locked, BC_TAG register loaded with results every backup cache probe. When control parity error primary fill data error (parity ECC) occurs, this register locked against further updates. software read this register using HW_MFPR instruction. Each time HW_MFPR from BC_TAG completes, contents BC_TAG shifted position right, that entire register read using sequence MFPRs. software unlock BC_TAG register using HW_MTPR BC_TAG. Successive HW_MFPRs from BC_TAG register must separated least null cycle. Figure shows backup cache register format. Table lists register fields gives description each. Figure Backup Cache Register
[33:17]
TAGCTL_P TAGCTL_D TAGCTL_S TAGCTL_V TAGADR_P
LJ-01861-TI0
Note Unused bits field this register always clear, based size external cache determined BC_SIZE field BIU_CTL register.
Table Backup Cache Register Fields
Field TAGADR_P TAGCTL_V TAGCTL_S TAGCTL_D TAGCTL_P Type Description Reflects state tagAdrP_h signal 21064A when tag, control, data parity error occurs. Contains that being currently probed. Reflects state tagCtlV_h signal 21064A when tag, control, data parity error occurs. Reflects state tagCtlS_h signal 21064A when tag, control, parity error occurs. Reflects state tagCtlD_h signal 21064A when tag, control, data parity error occurs. Reflects state tagCtlP_h signal 21064A when tag, control, data parity error occurs. When set, indicates that there match when tag, control, data parity error occurred.
PAL_TEMP Registers
chip contains (64-bit) registers that accessible HW_MxPR instructions. These registers provide temporary storage PALcode.
Lock Registers
There registers processor that associated with LDQ_ L/LDL_L STQ_C/STL_C instructions: lock_flag register locked_physical_address register. these registers described Alpha Architecture Reference Manual. These registers required architecture implemented 21064A. They must implemented application.
Internal Processor Registers Reset State
Table lists state internal processor registers (IPRs) immediately following reset. table also specifies which registers need initialized power-up PALcode. Table Internal Process Register Reset State
TB_TAG ITB_PTE ICCSR Reset State UNDEFINED UNDEFINED cleared except ASN, PC0, Floating-point disabled, single issue mode, Pipe mode enabled, predictions disabled, branch predictions disabled, branch history table disabled, performance counters reset zero, Perf Cnt0: Total Issues/2, Perf Cnt1: Dcache Misses, superpage disabled Comments
ITB_PTE_TEMP EXC_ADDR SL_RCV ITBZAP
UNDEFINED UNDEFINED UNDEFINED PALcode must ITBZAP reset before writing (must HW_MTPR ITBZAP register).
ITBASM ITBIS EXC_SUM
UNDEFINED UNDEFINED PALcode must processor status. PALcode must clear exception summary exception register write mask doing reads. Cleared reset. PALcode must initialize. PALcode must initialize. PALcode must initialize. PALcode must initialize. (continued next page)
PAL_BASE HIRR SIRR ASTRR HIER SIER
cleared UNDEFINED UNDEFINED UNDEFINED UNDEFINED
Table (Cont.) Internal Process Register Reset State
ASTER SL_XMIT TB_CTL DTB_PTE DTB_PTE_TEMP MM_CSR DTBZAP Reset State UNDEFINED UNDEFINED UNDEFINED UNDEFINED UNDEFINED UNDEFINED UNDEFINED Unlocked reset. Unlocked reset. PALcode must DTBZAP reset before writing (must HW_MTPR DTBZAP register). Comments PALcode must initialize. PALcode must initialize. Appears external pin. PALcode must select between SP/LP prior fill.
DTBASM DTBIS BIU_ADDR BIU_STAT SL_CLR C_STAT FILL_ADDR ABOX_CTL
UNDEFINED UNDEFINED UNDEFINED UNDEFINED UNDEFINED cleared Potentially locked. Potentially locked. PALcode must initialize. Potentially locked. Potentially locked. Write buffer enabled, machine checks disabled, correctable read interrupts disabled, Icache stream buffer disabled, super pages disabled, endian mode disabled, Dcache disabled, forced mode off. (STC_NORESULT disabled, NCACHE_NDISTURB disabled) Cycle counter disabled reset. (continued next page)
ALT_MODE
UNDEFINED UNDEFINED
Table (Cont.) Internal Process Register Reset State
CC_CTL BIU_CTL Reset State UNDEFINED cleared Bcache disabled, parity mode enabled, chip enable asserts during write cycles, Bcache forcedhit mode disabled. BC_PA_DIS field cleared. BAD_TCP cleared. BAD_DP cleared. DELAY_WDATA cleared. SYS_WRAP cleared. Potentially locked. Potentially locked. Comments
FILL_SYNDROME BC_TAG PAL_TEMP [31:0]
UNDEFINED UNDEFINED UNDEFINED
Note Bcache parameters listed here undetermined reset must initialized BIU_CTL register before enabling Bcache. Bcache read speed (BC_RD_SPD) Bcache write speed (BC_WR_SPD) Bcache delay write data (DELAY_WDATA) Bcache write enable control (BC_WE_CTL) Bcache size (BC_SIZE)
Electrical Characteristics
Table lists maximum ratings 21064A. Table 21064A Maximum Ratings (PRELIMINARY ESTIMATES)
Characteristics Storage temperature Supply voltage Junction temperature Voltage applied pins tolerant pins tolerant pins Case Temperature: 21064A-200 21064A-233 21064A-275, 21064A-275-PC 21064A-300 Maximum power @Vdd=3.46 21064A-200 21064A-233 21064A-275, 21064A-275-PC 21064A-300 Ratings -55°C 125°C (-67°F 257°F) -0.5 15°C 90°C (59°F 194°F) -0.5 -0.5 73°C 71°C 67°C 65°C (32°F (32°F (32°F (32°F 167.4°F) 160°F) 153°F) 149.0°F)
24.0 28.0 33.0 36.0
Note Alpha 21064 Alpha 21064A Microprocessors Hardware Reference Manual formulas calculate peak power calculate maximum power other values clock frequency.
Caution Stress beyond absolute maximum ratings cause permanent damage 21064A. Exposure absolute maximum rating conditions extended periods time affect 21064A reliability.
Characteristics
21064A uses CMOS/TTL voltage levels. CMOS mode, pins connected pins connected nominal Caution prevent damage 21064A, important that power supply stable before input bidirectional pins allowed rise above
vRef analog input should connected +/-10% reference supply. clkIn_h clkIn_l differential signals generated from external oscillator circuit. signals coupled oscillator greater than Vdd), with nominal bias Vdd/2 high-impedance (greater than ohm) resistive network chip. signals need coupled used supply oscillator. 21064A signal input pins CMOS inputs that standard levels, vRef. Table lists input characteristics. following signals sampled before vRef stable. These signals cannot driven above power supply. dcOk_h tristate_l (3.3 cont_l (3.3 eclOut_h (GND) 21064A output pins CMOS outputs. These output signals driven between Vss. Timing specified standard levels. Table lists output characteristics. bidirectional pins ordinary CMOS bidirectional pins.
Table Input/Output Characteristics
Symbol Vihs Vdiffc Icin Description Power supply voltage High-level input voltage (except dcOk_h cont_l) High-level input voltage (static pins dcOk_h cont_l) Low-level input voltage High-level output voltage Low-level output voltage Differential clock input swing (duty cycle 45-55%) Input leakage current (except eclOut_h) Input leakage current (eclOut_h) Output leakage current (tristate) Clock input leakage 3.135 -100 -150 -100 3.465 Units
Test Conditions 0<Vin<Vdd 0<Vin<Vdd 0<Vin<3.465
Note Values this table valid only Vref
Characteristics
This section contains characteristics 21064A. Timing parameters given internal clock speed MHz. Reference Supply reference supply (vRef) analog reference voltage used 21064A input buffers signals, except following: clkIn_h clkIn_l testClkIn_h testClkIn_l dcOk_h eclOut_h tristate_l cont_l Upon power-up, reset_l cannot sampled until vRef stable. Input Clocks clkIn_h clkIn_l input clocks have differential inputs. Generally, designers apply standard input clocks clkIn_h clkIn_l. 21064A input clock circuit also allows applications that require input clocks (233 input clocks current implementation). 21064A with input clocks, designer needs drive clock inputs into clkIn pins testClkIn_h testClkIn_l Note Driving clock into testClkIn_h testClkIn_l results UNPREDICTABLE behavior.
Electrically, circuitry attached testClkIn_h testClkIn_l identical circuitry attached tristate_l. same restrictions tristate_l apply testClkIn_h testClkIn_l. Alpha 21064 Alpha 21064A Microprocessors Hardware Reference Manual these restrictions.
Table lists possible states testClkIn pins resulting functions. Table testClkIn States
testClkIn_h testClkIn_l Functions Reserved Digital Standard input clocks applied clkIn pins Standard input clocks applied clkIn pins input clocks applied clkIn pins
terminations these signals (clkIn testClkIn) designed compatible with system oscillators arbitrary bias. Figure shows clock termination. Figure Clock Termination 21064A
Diff
High (Approx.
Vbias (Vdd-Vss)/2
LJ-03928.AI
timings output signals, including clocks (except cpuClkOut_h), specified with respect their crossings midpoint from into lumped capacitive load package pin.
Interface Timing following sections show interface timing 21064A. Input Clock Timing Table lists input clock cycle times 21064A frequencies. These periods equal one-half corresponding cycle times. Table Input Clock Timing
Clock Characteristic clkIn period minimum clkIn period maximum clkIn symmetry 21064A-233 2.15 15.0 21064A-275 1.82 15.0
Figure shows timing diagram input clock. Figure Input Clock Timing Diagram
clkIn_h
CYCLE
clkIn_l
CYCLE
LJ-02774-TI0
Reset Timing Figure shows SROM timing first three samples. Figure Reset Timing
reset_l
sRomOE_l
sRomClk_h
Sample sRomD_h
LJ-01863-TI0
following list explains reset timing shown Figure When reset_l asserted, sRomOe_l deasserted sRomClk_h asserted. 21064A internal reset signal remains asserted least cycles after reset_l deasserts, when sRomOe_l asserts. first rising edge sRomClk_h occurs cycles after sRomOe_l asserts, every cycles thereafter. 21064A samples sRomD_h last half each cycle before rising edge sRomClk_h.
Figure shows Icache preload sequence. shaded area indicates UNPREDICTABLE behavior. Figure Reset Timing-End Preload Sequence
sRomOe_l sRomClk_h Sample sRomD_h
LJ-01864-TI0
refers 21064A internal clock shown cycle reference. 21064A samples final SROM when sRomClk_h rises, shown. cycles later, 21064A deasserts sRomOe_l drives sRomClk_h with value from SL_XMIT IPR. Because this initialized chip reset, value driven onto sRomClk_h UNPREDICTABLE.
External Cycle Timing Table lists times referenced sysClkOut1_h. Table External Cycles
Name Output enable, sysClkOut1_h adr_h data_h (WRITE_BLOCK) check_h (WRITE_BLOCK) -1.0 -1.0 -1.0 Minimum Maximum Units
(continued next page)
Table (Cont.) External Cycles
Name Output delay, sysClkOut1_h adr_h data_h (WRITE_BLOCK) check_h (WRITE_BLOCK) cReq_h cWMask_h holdAck_h -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 Note: This timing guaranteed design. Input setup relative sysClkOut1_h cAck_h dRAck_h dWSel_h dOE_l holdReq_h dInvReq_h iAdr_h [12:5] data_h (READ_BLOCK) check_h (READ_BLOCK) perf_cnt_h Minimum Maximum Units
(continued next page)
Table (Cont.) External Cycles
Name Input hold relative sysClkOut1_h Minimum Maximum Units
Input hold relative sysClkOut1_h cAck_h dRAck_h dWSel_h dOE_l holdReq_h dInvReq_h [1:0] iAdr_h data_h (READ_BLOCK) check_h (READ_BLOCK) perf_cnt_h Note: This timing guaranteed design.
Note signals adr_h [33:5], data_h [127:0], check_h [27:0] only synchronous sysClkOut1_h during external cycle. During time that cReq_h [2:0] field IDLE, signals change without regard clocks that drive external system logic. During time that field cReq_h [2:0] IDLE (non-zero), signals conform setup hold times. signals cReq_h [2:0], holdAck_h, cWMask_h [7:0] always synchronous external system clocks, even during those times when external cycle progress.
Output Delay Time Measurement Figure shows 21064A output delay time measurement. Figure Output Delay Time Measurement
Delay
Valid Signal
LJ-02424-TI0
Note This delay positive negative.
Setup Hold Time Measurement Figure shows 21064A setup hold time measurement. Figure Setup Hold Time Measurement
Set-up
Hold
Valid Signal
LJ-02423-TI0
READ_BLOCK Timing Figure shows 21064A READ_BLOCK timing diagram. Figure READ_BLOCK Timing Diagram
sysClkOut1_h adr_h[33:05] data_h[127:0] check_h[27:0] dRack_h[2:0] -1.0/+1.0 cReq_h[2:0] cAck_h[2:0] Idle Idle Times
MLO-012073
-1.0/+1.0
READ_BLOCK
-1.0/+1.0 Idle Idle
tcycle where tcycle period cpuClkOut_h. Indicates minimum maximum. Minimum setup time shown. hold times minimum
WRITE_BLOCK Timing Figure shows WRITE_BLOCK timing diagram. Figure WRITE_BLOCK Timing Diagram
sysClkOut1_h adr_h[33:05] -1.0/2.0 data_h[127:0] check_h[27:0] -1.0/+1.0 cReq_h[2:0] Idle -1.0/+1.0 cWMask_h[7:0] dOE_l dWSel_l[1:0] cAck_h[2:0] Idle Times
MLO-012074
-1.0/2.0
-1.0/+1.0
-1.0/+1.0 WRITE_BLOCK Idle -1.0/+1.0
Idle
tcycle where tcycle period cpuClkOut_h. Indicates minimum maximum. Minimum setup time shown. hold times minimum
BARRIER Timing Figure shows BARRIER operation timing. Figure BARRIER Timing Diagram
sysClkOut1_h adr_h cReq_h[2:0] cAck_h[2:0] -1.0/+1.0 BARRIER Idle Times
MLO-012075
Idle
Idle Idle
Indicates minimum maximum. Minimum setup time shown. hold times minimum
FETCH/FETCH_M Timing Figure shows FETCH/FETCH_M operation timing. Figure FETCH/FETCH_M Timing Diagram
sysClkOut1_h adr_h[33:05] cReq_h[2:0] cAck_h[2:0] Idle Idle Times
MLO-012076
-1.0/+1.0 -1.0/+1.0 FETCH Idle Idle
tcycle ±1.0 where tcycle period cpuClkOut_h. Indicates minimum maximum. Minimum setup time shown. hold times minimum
Thermal Considerations
Note combination airflow, heat sink design, package thermal characteristics must considered when calculating power dissipation, order exceed maximum junction temperature (Tj) 90°C (194°F).
21064A packaged 431-pin alumina-ceramic (cavity-down) package. This cavity-down design allows attached surface package, which increases ability dissipate heat through package attached heat sink surface. metal slug with mounting studs brazed ceramic package heat sink assembly. package mounting pads capacitors surface that limits heat sink contact area. meet thermal requirements, specific dimensions heat sink should determined designer. 21064A maximum power rating, which varies depending operating frequency. Power dissipation varies directly with frequency. Temperature Measurement Locations package components temperature measurement sites listed here. locations components sites indicated Figure
Heat sink temperature (Ths) Case temperature (Tc) Junction temperature (Tj) Package Alpha 21064A Microprocessor Package GRAFOIL Heat sink
Figure Package Components Temperature Measurement Locations
LJ-02416-TI0
Critical Parameters Thermal Design
Follow these guidelines placement printed-circuit board components: Orient 21064A printed-circuit board (PCB) with heat sink fins aligned with airflow direction. Avoid preheating ambient air. Place 21064A that inlet preheated other components. place other high power devices vicinity 21064A. restrict airflow across 21064A heat sink. Placement other devices must allow maximum system airflow order maximize performance heat sink.
Tables show thermal characteristics 21064A. Section heat sink information. Table 21064A-200 Thermal Characteristics Forced-Air Environment
21064A-200 73.0°C (167.4°F) Heat Sink Velocity lfpm lfpm lfpm lfpm 1000 lfpm Power 24.0 24.0 24.0 24.0 24.0 TaMax 43.0°C (109.4°F) 52.6°C (126.7°F) 58.6°C (137.5°F) 60.5°C (140.9°F) 63.4°C (146.1°F)
Heat Sink TaMax 33.4°C (92.1°F) 44.2°C (111.6°F) 52.6°C (126.7°F) 57.4°C (135.3°F) 59.6°C (139.3°F)
1.25 0.85 0.60 0.52 0.40
1.65 1.20 0.85 0.65 0.56
Table constants abbreviations 90°C (194°F). C/W. lfpm linear feet minute.
Table 21064A-233 Thermal Characteristics Forced-Air Environment
21064A-233 Tc=71.0°C (159.8°F) Heat Sink Velocity lfpm lfpm lfpm lfpm 1000 lfpm Power 28.0 28.0 28.0 28.0 28.0 TaMax 36.0°C (96.8°F) 47.2°C (117.0°F) 54.2°C (129.6°F) 56.4°C (133.5°F) 59.8°C (139.6°F)
Heat Sink TaMax 24.8°C (76.6°F) 37.4°C (99.3°F) 47.2°C (117.0°F) 52.8°C (127.0°F) 55.3°C (131.5°F)
1.25 0.85 0.60 0.52 0.40
1.65 1.20 0.85 0.65 0.56
Table constants abbreviations 90°C (194°F). C/W. lfpm linear feet minute.
Table 21064A-275 21064A-275-PC Thermal Characteristics Forced-Air Environment
21064A-275 21064A-275-PC- Tc=67.0°C (152.6°F) Heat Sink Velocity lfpm lfpm lfpm lfpm 1000 lfpm Power 33.0 33.0 33.0 33.0 33.0 TaMax 25.8°C (78.4°F) 39.0°C (102.2°F) 47.2°C (117.0°F) 49.8°C (121.6°F) 53.8°C (128.8°F)
Heat Sink TaMax 27.4°C (81.3°F) 39.0°C (102.2°F) 45.6°C (114.0°F) 48.5°C (119.3°F)
1.25 0.85 0.60 0.52 0.40
1.20 0.85 0.65 0.56
Table constants abbreviations 90°C (194°F). C/W. lfpm linear feet minute.
Table 21064A-300 Thermal Characteristics Forced-Air Environment
21064A-300 Tc=65.0°C (149.0°F) Heat Sink Velocity lfpm lfpm lfpm lfpm 1000 lfpm Power 36.0 36.0 36.0 36.0 36.0 TaMax 20.0°C (68.0°F) 34.4°C (93.9°F) 43.4°C (110.1°F) 46.3°C (115.3°F) 50.6°C (123.1°F)
Heat Sink TaMax 21.8°C (71.2°F) 34.4°C (93.9°F) 41.6°C (106.9°F) 44.8°C (112.6°F)
1.25 0.85 0.60 0.52 0.40
1.20 0.85 0.65 0.56
Table constants abbreviations 90°C (194°F). C/W. lfpm linear feet minute.
Note values Tables base upon assumption that maximum power will 24.0 28.0 33.0 33.0 36.0 21064A-200, 21064A-233, 21064A-275, 21064A-275-PC, 21064A-300 respectively.
Mechanical Specifications
This section provides detailed information about 21064A package complete pinout.
Package Information
Figure shows examples heat sinks which used help cool 21064A. primary heat sink (number Figure available from Digital. Figure Heat Sink Dimensions
7.48 (2.945
6.83 (2.690
7.48 (2.945
2.16 (0.850
6.83 (2.690
2.16 (0.850
0.050 plcs) 0.190
4.12 (1.620
0.130
3.43 (1.350
3.18 (1.250 Diameter
0.070
3.18 (1.250 Diameter
MLO-012865
Figure shows package physical dimensions without heat sink.
Figure Package Dimensions
2.54 (.100 2.54 (.100
1.27 (.050 4.95 (.195 (.035
(.018
Standoff (4x) 10-32 Stud (2x)
29.21 (1.150
.025 (.001 Minimum Radius
6.35 (.250
29.21 (1.150 61.72 (2.430 30.86 (1.215
1.78 (.070 431x 1.65 (.065 Braze
30.86 (1.215
Capacitors (0x) 21.59 (.850 31.75 (1.250 Heat Slug Base Area
MLO-012009
21064A Pins
Figure shows 21064A cavity. Figure Cavity Down View
21064A View (Pin Down)
MLO-012007
Table lists order 21064A pins location. Table List
Location Name data_h data_h data_h data_h data_h check_h data_h data_h data_h data_h data_h data_h data_h data_h check_h data_h data_h data_h check_h data_h data_h data_h data_h check_h Location Name check_h plane data_h plane data_h plane data_h plane data_h plane data_h plane data_h plane check_h plane data_h plane check_h plane data_h plane plane check_h Location Name check_h plane data_h data_h data_h check_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h check_h data_h data_h data_h check_h dRAck_h dInvReq_h (continued next page)
Table (Cont.) List
Location Name Location Name Location Name
data_h check_h check_h data_h data_h data_h data_h data_h data_h data_h check_h data_h data_h data_h data_h data_h data_h check_h data_h data_h check_h dRAck_h plane dOE_l
data_h plane data_h data_h plane plane plane plane plane plane check_h data_h data_h data_h plane plane plane plane plane plane dRAck_h dWSel_h dWSel_h cAck_h
data_h data_h data_h data_h plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane cAck_h cAck_h plane holdReq_h (continued next page)
Table (Cont.) List
Location Name Location Name Location Name
data_h plane data_h data_h plane plane plane plane holdAck_h dataCEOE_h dataCEOE_h dataCEOE_h check_h check_h check_h check_h plane plane plane plane dataCEOE_h tagCtlWE_h plane cWMask_h
data_h plane data_h data_h plane plane plane plane cWMask_h cWMask_h cWMask_h cWMask_h data_h data_h data_h data_h plane plane plane plane cWMask_h cWMask_h plane cWMask_h
check_h plane data_h data_h data_h plane plane dataWE_h dataWE_h dataWE_h dataWE_h dMapWE_h data_h data_h data_h data_h check_h plane plane cReq_h cReq_h cReq_h plane dMapWe_h (continued next page)
Table (Cont.) List
Location Name Location Name Location Name
data_h plane data_h data_h data_h plane plane tagOk_l tagOk_h dataA_h dataA_h tagCEOE_h data_h data_h data_h data_h data_h plane plane tagCtlS_h tagCtlD_h tagCtlP_h plane lockWE_h
data_h plane data_h data_h plane plane plane plane tagadr_h tagadr_h lockFlag_h tagCtlV_h check_h check_h data_h data_h plane plane plane plane tagadr_h tagadr_h plane tagadr_h
data_h plane data_h data_h plane plane plane plane tagadr_h tagadr_h tagadr_h tagadr_h data_h data_h data_h data_h plane plane plane plane tagadr_h tagadr_h plane tagadr_h (continued next page)
Table (Cont.) List
Location Name Location Name Location Name
data_h plane data_h check_h plane plane plane plane testClkIn_h testClkIn_l plane clkIn_h clkIn_l plane plane plane plane plane plane plane tagadrP_h tagadr_h tagadr_h tagadr_h
data_h data_h data_h data_h plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane adr_h adr_h plane tagadr_h
AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24
check_h plane data_h data_h data_h iAdr_h iAdr_h vRef sysClkOut2_h sysClkOut2_l resetSClk_h sysClkOut1_h sysClkOut1_l cont_l irq_h sysClkDiv_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h (continued next page)
Table (Cont.) List
Location Name Location Name Location Name
AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24
data_h data_h data_h data_h data_h iAdr_h iAdr_h reset_l sRomD_h sRomOE_l cpuClkOut_h dcOk_h triState_l icMode_h irq_h perf_cnt_h adr_h adr_h adr_h adr_h adr_h adr_h plane adr_h
AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24
data_h plane plane data_h plane iAdr_h plane iAdr_h plane sRomClk_h plane spare plane irq_h plane perf_cnt_h plane adr_h plane adr_h plane adr_h plane adr_h
AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24
data_h data_h data_h iAdr_h iAdr_h icMode_h eclOut_h dInvReq_h spare spare icMode_h irq_h irq_h irq_h Digital Reserved adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h
Signal Lists
Tables through list 21064A pinout. order pinout signal name. following list describes abbreviations used Type column lists. Bidirectional Input connected Power ground Output
Table Data Signals List
Signal data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h Location Type Signal data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h Location Type
(continued next page)
Table (Cont.) Data Signals List
Signal data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h Location Type Signal data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h data_h Location Type
(continued next page)
Table (Cont.) Data Signals List
Signal data_h data_h data_h data_h data_h data_h data_h data_h Location Type Signal data_h data_h data_h data_h data_h data_h data_h data_h Location Type
Table Address Signals List
Signal adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h Location AD17 AB17 AA17 AD18 AC18 AB18 AA18 AD19 AB19 AA19 AD20 AC20 AB20 AD21 AD22 Type Signal adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h adr_h Location AB21 AA20 AC22 AA21 AB22 AD23 AD24 AA22 AC24 AB24 AA23 AA24 Type
Table Parity/ECC Signals List
Signal check_h check_h check_h check_h check_h check_h check_h check_h check_h check_h check_h check_h check_h check_h Location Type Signal check_h check_h check_h check_h check_h check_h check_h check_h check_h check_h check_h check_h check_h check_h Location Type
Table Primary Cache Invalidate Signals List
Signal iAdr_h iAdr_h iAdr_h iAdr_h dInvReq_h Location Type Signal iAdr_h iAdr_h iAdr_h iAdr_h dInvReq_h Location Type
Table External Cache Control Signals List
Signal tagCEOE_h tagCtlV_h tagCtlS_h tagadr_h tagadr_h tagadr_h tagadr_h tagadr_h tagadr_h tagadr_h tagadr_h tagadrP_h tagOk_h dataCEOE_h dataCEOE_h dataWE_h dataWE_h dataA_h holdReq_h dMapWE_h dMapWE_h dWSel_h dRAck_h dRAck_h cReq_h Location Type Signal tagCtlWE_h tagCtlD_h tagCtlP_h tagadr_h tagadr_h tagadr_h tagadr_h tagadr_h tagadr_h tagadr_h tagadr_h tagOk_l dataCEOE_h dataCEOE_h dataWE_h dataWE_h dataA_h holdAck_h dOE_l dWSel_h dRAck_h cReq_h Location Type (continued next page)
Table (Cont.) External Cache Control Signals List
Signal cReq_h cWMask_h cWMask_h cWMask_h cWMask_h cAck_h cAck_h Location Type Signal cWMask_h cWMask_h cWMask_h cWMask_h cAck_h Location Type
Table Interrupt Signals List
Signal irq_h irq_h irq_h Location AA15 AB15 AD15 Type Signal irq_h irq_h irq_h Location AC14 AD14 AD13 Type
Table Instruction Cache Initialization Signals List
Signal icMode_h icMode_h Location AD12 Type Signal icMode_h Location AB14 Type
Table Serial Interface Signals List
Signal sRomOE_l sRomD_h Location AB10 Type Signal sRomClk_h Location AC10 Type
Table Initialization Signals List
Signal dcOk_h resetSClk_h Location AB12 AA11 Type Signal reset_l Location Type
Table Load/Lock Store/Conditional Fast Lock Mode Signals List
Signal lockFlag_h Location Type Signal lockWE_h Location Type
Table Clock Signals List
Signal clkIn_h testClkIn_h cpuClkOut_h sysClkOut1_h sysClkOut2_h Location AB11 AA12 Type Signal clkIn_l testClkIn_l sysClkDiv_h sysClkOut1_l sysClkOut2_l Location AA16 AA13 AA10 Type
Table Performance Monitoring Signals List
Signal perf_cnt_h Location AC16 Type Signal perf_cnt_h Location AB16 Type
Table Other Signals List
Signal triState_l cont_l Location AB13 AA14 Type Signal vRef eclOut_h Location Type
Table Power List
Signal plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane Location Type Signal plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane Location Type
(continued next page)
Table (Cont.) Power List
Signal plane plane plane plane plane plane plane plane Location Type Signal plane plane plane plane plane plane plane plane Location AC11 AC15 AC19 AC23 Type
Table Ground List
Signal plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane Location Type Signal plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane Location Type
(continued next page)
Table (Cont.) Ground List
Signal plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane Location Type Signal plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane plane Location AB23 AC13 AC17 AC21 Type
Table Spare List
Signal spare spare Location AD16 AC12 Type Signal spare spare Location AD10 AD11 Type
Technical Support Ordering Information
Technical Support need technical support help deciding which literature best meets your needs, call Digital Semiconductor Information Line: United States Canada Outside North America 1-800-332-2717 +1-508-628-4760
Ordering Digital Semiconductor Products order Alpha 21064A microprocessors related products, contact your local distributor. order following semiconductor products from Digital:
Product Alpha 21064A-200 Microprocessor Alpha 21064A-233 Microprocessor Alpha 21064A-275 Microprocessor Alpha 21064A-275-PC Microprocessor Alpha 21064A-300 Microprocessor AlphaPC64 Evaluation Board 275-MHz AlphaPC64 Evaluation Board Design Alpha Evaluation Board Software Developer's DECchip 21064 Evaluation Board Design Package Heat Sink Assembly Order Number 21064-AB 21064-BB 21064-DB 21064-P1 21064-EB 21A02-03 21A02-13 21B02-02 21A01-13 2106H-AA
Ordering AlphaPC64 Boards order AlphaPC64 board, contact your local distributor.
Board Product AlphaPC64 Board1 AlphaPC64 Board2 (2MB Level Cache) AlphaPC64 Board2 (512KB Level Cache)
Alpha Alpha
Order Number 21A02-A3 21A02-A4 21A02-A5
21064A microprocessors, main memory, level cache must purchased separately. 21064A microprocessors main memory must purchased separately.
Ordering Associated Literature following table lists some available Digital Semiconductor literature. complete list, contact Digital Semiconductor Information Line.
Title Alpha 21064 Alpha 21064A Microprocessors Hardware Reference Manual PALcode Alpha Microprocessors System Design Guide Designing Memory/Cache Subsystem DECchip 21064 Microprocessor: Application Note Designing System with DECchip 21064 Microprocessor: Application Note Calculating System Address DECchip 21064 Evaluation Board: Application Note DECchip 21064 Transactor User's Guide Alpha Microprocessors Evaluation Board Debug Monitor User's Guide AlphaPC64 Evaluation Board User's Guide AlphaPC64 Evaluation Board Read First DECchip 21064 Evaluation Board Product Brief Alpha Microprocessors SROM Mini-Debugger User's Guide Alpha Microprocessors Evaluation Board Software Design Tools User's Guide Order Number EC-Q9ZUA-TE EC-QFGLB-TE EC-N0301-72 EC-N0107-72 EC-N0567-72 EC-N0448-72 EC-QHUVB-TE EC-QGY2C-TE EC-QGY3C-TE EC-N0353-72 EC-QHUXA-TE EC-QHUWA-TE

Order Number: EC-QFGKC-TE This document contains information about fol

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