Cautions Keep safety first your circuit designs! Renesas Technolo

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Cautions
Keep safety first your circuit designs! Renesas Technology Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Renesas Technology Corporation product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Renesas Technology Corporation third party. Renesas Technology Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts, programs, algorithms, circuit application examples contained these materials. information contained these materials, including product data, diagrams, charts, programs algorithms represents information products time publication these materials, subject change Renesas Technology Corporation without notice product improvements other reasons. therefore recommended that customers contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor latest product information before purchasing product listed herein. information described here contain technical inaccuracies typographical errors. Renesas Technology Corporation assumes responsibility damage, liability, other loss rising from these inaccuracies errors. Please also attention information published Renesas Technology Corporation various means, including Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). When using information contained these materials, including product data, diagrams, charts, programs, algorithms, please sure evaluate information total system before making final decision applicability information products. Renesas Technology Corporation assumes responsibility damage, liability other loss resulting from information contained herein. Renesas Technology Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Renesas Technology Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. Please contact Renesas Technology Corporation further details these materials products contained therein.
Hitachi Single-Chip Microcomputer
H8/3857 Series
H8/3857 H8/3856 H8/3855 H8/3857F-ZTATHD6433857, HCD6433857 HD6433856, HCD6433856 HD6433855, HCD6433855 HD64F3857, HCD64F3857
H8/3854 Series
H8/3854 H8/3853 H8/3852 H8/3854F-ZTATHD6433854, HCD6433854 HD6433853, HCD6433853 HD6433852, HCD6433852 HD64F3854, HCD64F3854
Hardware Manual
ADE-602-175A Rev. 3/5/03 Hitachi, Ltd.
revision list viewed directly clicking title page. revision list summarizes locations revisions additions. Details should always checked referring relevant text.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8/300L Series single-chip microcomputers high-speed H8/300L core, with many necessary peripheral functions on-chip. H8/300L instruction compatible with H8/300 CPU. H8/3857 Series following on-chip peripheral functions required system configuration: maximum 1,280-dot display controller, four types timers, 14-bit PWM, 2-channel serial communication interface, 8-channel converter. H8/3854 Series following on-chip peripheral functions required system configuration: maximum 640-dot display controller, three types timers, single-channel serial communication interface, 4-channel converter. Both series used embedded microcomputers systems requiring display. H8/3857, H8/3856, H8/3855, H8/3854, H8/3853, H8/3852 available mask versions, H8/3857 H8/3854 also available F-ZTATTM* version which allows programs written after chip mounted board. Note: F-ZTAT (Flexible Zero Turn-Around Time) trademark Hitachi, Ltd. This manual describes hardware H8/3857 Series H8/3854 Series. details H8/3857 Series H8/3854 Series instruction set, refer H8/300L Series Programming Manual.
List Functions
Series Product Code H8/3857 Series F-ZTAT Version Mask Version H8/3854 Series F-ZTAT Version Mask Version
H8/3857F H8/3857 H8/3856 H8/3855 size (kbytes) size (kbytes) ports Input/output ports Input ports Interrupts External interrupts Internal interrupts Timer (for realtime clock) Timer bits) Timer bits) Timer bits) Watchdog timer 14-bit Serial communication interface (SCI) converter controller Max. display dots Display size Packages Pins Shipping form 1280 dots 2048 bits 1280 dots 2048 bits 1280 dots 2048 bits 1280 dots 2048 bits sources sources
H8/3854F H8/3854 H8/3853 H8/3852 sources sources
sources sources sources sources sources sources
sources sources sources sources sources sources
dots bits dots bits
dots bits
dots bits
FP-144H TFP-144 (F-ZTAT version: 7.08 7.31 mask version: 6.21 6.21
FP-100B TFP-100G (F-ZTAT version: 6.34 6.34 mask version: 4.69 4.69
Note: Note that H8/3854F (F-ZTAT version) H8/3854 (mask version) have different sizes. When carrying program development using H8/3854F with intention mask implementation, care must taken with sizes since maximum sizes mask version kbytes kbyte RAM.
List Items Revised Added This Version
Page Item H8/3854 Series added Figure H8/3857 Series Internal Block Diagram Figure Layout HCD64F3857 (F-ZTAT Version) Table HCD64F3857 Coordinates Figure Layout HCD6433855, HCD6433856, HCD6433857 (Mask Version) Table HCD6433855, HCD6433856, HCD6433857 Coordinates Figure Layout HCD6433854, HCD6433853, HCD6433852 (Mask Version) Table HCD6433852, HCD6433853, HCD6433854 Coordinates Table Effective Address Calculation Figure 2.16 H8/3857 Series Memory System Clock Generator Inputting External Clock 5.3.5 Notes External Input Signal Changes before/after Standby Mode 5.4.4 Notes External Input Signal Changes before/after Watch Mode 5.8.3 Notes External Input Signal Changes before/after Direct Transition Figure 6.16 HD64F3857 Socket Adapter Interconnections 6.10 Notes when Converting F-ZTAT Application Software Mask-ROM Versions Table H8/3857 Series Port Functions 8.5.2 Register Configuration Description Port Data Register 9.5.2 Register Descriptions Timer Control/ Status Register Name (TCSRF) amended 10.2.2 Register Descriptions Serial Control/Status Register 10.2.2 Register Descriptions Serial Control/Status Register description changed Description added Added Added Added "Notation" amended Added Port pins changed Changed Changed numbers changed numbers changed Model names amended Model names amended Added Added Amended Changed Added Description
Page
Item 10.2.5 Application Notes Table 10.5 Receive Error Conditions Received Data Processing 13.3.2 Interface Notes Chip-Internal Ports
Description Description changed Amended Description amended
Table 13.6 Functions According Display Mode Display Duty Figure 13.12 Module Standby Mode Standby Mode Initiation Clearing Procedures Table 15.1 Absolute Maximum Ratings Table 15.5 Serial Interface (SCI1) Timing H8/3855, H8/3856, H8/3857 Table 15.7 Converter Characteristics H8/3855, H8/3856, H8/3857 Figure 15.7 SCK3 Input Clock Timing Register Descriptions PDRB-Port data register
Title added Title corrected Note amended Amended Note amended Title corrected Changed
Figure Port Block Diagram
Amended
Contents
Section
Overview Overview. Internal Block Diagram Arrangement Functions 1.3.1 Arrangement 1.3.2 Functions.
Section
Overview. 2.1.1 Features 2.1.2 Address Space 2.1.3 Register Configuration Register Descriptions. 2.2.1 General Registers. 2.2.2 Control Registers. 2.2.3 Initial Register Values Data Formats. 2.3.1 Data Formats General Registers. 2.3.2 Memory Data Formats. Addressing Modes 2.4.1 Addressing Modes. 2.4.2 Effective Address Calculation. Instruction Set. 2.5.1 Data Transfer Instructions 2.5.2 Arithmetic Operations 2.5.3 Logic Operations 2.5.4 Shift Operations. 2.5.5 Manipulations 2.5.6 Branching Instructions. 2.5.7 System Control Instructions Basic Operational Timing. 2.6.1 Access On-Chip Memory (RAM, ROM) 2.6.2 Access On-Chip Peripheral Modules States 2.7.1 Overview 2.7.2 Program Execution State 2.7.3 Program Halt State 2.7.4 Exception-Handling State
Memory 2.8.1 Memory Map. Application Notes. 2.9.1 Notes Data Access. 2.9.2 Notes Manipulation 2.9.3 Notes EEPMOV Instruction
Section
Exception Handling. Overview. Reset 3.2.1 Overview 3.2.2 Reset Sequence. 3.2.3 Interrupt Immediately after Reset Interrupts. 3.3.1 Overview 3.3.2 Interrupt Control Registers 3.3.3 External Interrupts. 3.3.4 Internal Interrupts 3.3.5 Interrupt Operations. 3.3.6 Interrupt Response Time Application Notes. 3.4.1 Notes Stack Area Use. 3.4.2 Notes Rewriting Port Mode Registers. Clock Pulse Generators Overview. 4.1.1 Block Diagram. 4.1.2 System Clock Subclock System Clock Generator. Subclock Generator Prescalers Note Oscillators
Section
Section
Power-Down Modes Overview. 5.1.1 System Control Registers Sleep Mode. 5.2.1 Transition Sleep Mode 5.2.2 Clearing Sleep Mode Standby Mode. 5.3.1 Transition Standby Mode 5.3.2 Clearing Standby Mode. 5.3.3 Oscillator Settling Time after Standby Mode Cleared.
5.3.4 Transition Standby Mode Port States. 5.3.5 Notes External Input Signal Changes before/after Standby Mode. Watch Mode 5.4.1 Transition Watch Mode. 5.4.2 Clearing Watch Mode 5.4.3 Oscillator Settling Time after Watch Mode Cleared 5.4.4 Notes External Input Signal Changes before/after Watch Mode Subsleep Mode 5.5.1 Transition Subsleep Mode. 5.5.2 Clearing Subsleep Mode. Subactive Mode 5.6.1 Transition Subactive Mode 5.6.2 Clearing Subactive Mode 5.6.3 Operating Frequency Subactive Mode Active (medium-speed) Mode 5.7.1 Transition Active (medium-speed) Mode 5.7.2 Clearing Active (medium-speed) Mode 5.7.3 Operating Frequency Active (medium-speed) Mode. Direct Transfer. 5.8.1 Direct Transfer Overview. 5.8.2 Calculation Direct Transfer Time before Transition. 5.8.3 Notes External Input Signal Changes before/after Direct Transition.
Section
Overview. 6.1.1 Block Diagram. Overview Flash Memory. 6.2.1 Features 6.2.2 Block Diagram. 6.2.3 Flash Memory Operating Modes. 6.2.4 Configuration 6.2.5 Register Configuration Flash Memory Register Descriptions 6.3.1 Flash Memory Control Register (FLMCR1). 6.3.2 Flash Memory Control Register (FLMCR2). 6.3.3 Erase Block Register (EBR). 6.3.4 Mode Control Register (MDCR). 6.3.5 System Control Register (SYSCR3) On-Board Programming Modes 6.4.1 Boot Mode. 6.4.2 User Program Mode Flash Memory Programming/Erasing. 6.5.1 Program Mode.
6.5.2 Program-Verify Mode 6.5.3 Erase Mode. 6.5.4 Erase-Verify Mode Flash Memory Protection 6.6.1 Hardware Protection. 6.6.2 Software Protection 6.6.3 Error Protection Interrupt Handling during Flash Memory Programming Erasing Flash Memory Writer Mode. 6.8.1 Writer Mode Setting 6.8.2 Socket Adapter Memory 6.8.3 Writer Mode Operation 6.8.4 Memory Read Mode. 6.8.5 Auto-Program Mode 6.8.6 Auto-Erase Mode. 6.8.7 Status Read Mode. 6.8.8 Status Polling. 6.8.9 Writer Mode Transition Time 6.8.10 Notes Memory Programming. Flash Memory Programming Erasing Precautions 6.10 Notes when Converting F-ZTAT Application Software Mask-ROM Versions
Section
Overview. 7.1.1 Block Diagram.
Section
Ports
Overview. Port 8.2.1 Overview 8.2.2 Register Configuration Description. 8.2.3 Functions. 8.2.4 States 8.2.5 Input Pull-Up Port 8.3.1 Overview 8.3.2 Register Configuration Description. 8.3.3 Functions. 8.3.4 States Port (H8/3857 Series Only) 8.4.1 Overview 8.4.2 Register Configuration Description. 8.4.3 Functions.
8.4.4 States 8.4.5 Input Pull-Up Port 8.5.1 Overview 8.5.2 Register Configuration Description. 8.5.3 Functions. 8.5.4 States Port 8.6.1 Overview 8.6.2 Register Configuration Description. 8.6.3 Functions. 8.6.4 States 8.6.5 Input Pull-Up Port [Chip-Internal port] 8.7.1 Overview 8.7.2 Register Configuration Description. 8.7.3 Functions. 8.7.4 States Port [Chip-Internal port]. 8.8.1 Overview 8.8.2 Register Configuration Description. 8.8.3 Functions. 8.8.4 States Port 8.9.1 Overview 8.9.2 Register Configuration Description.
Section
Timers Overview. Timer 9.2.1 Overview 9.2.2 Register Descriptions. 9.2.3 Timer Operation 9.2.4 Timer Operation States. Timer 9.3.1 Overview 9.3.2 Register Descriptions. 9.3.3 Timer Operation 9.3.4 Timer Operation States Timer (H8/3857 Series Only) 9.4.1 Overview 9.4.2 Register Descriptions. 9.4.3 Timer Operation
9.4.4 Timer Operation States Timer 9.5.1 Overview 9.5.2 Register Descriptions. 9.5.3 Interface with 9.5.4 Timer Operation 9.5.5 Application Notes. Watchdog Timer [H8/3857F H8/3854F Only] 9.6.1 Overview 9.6.2 Register Descriptions. 9.6.3 Operation 9.6.4 Watchdog Timer Operating Modes.
Section Serial Communication Interface
10.1 Overview. 10.2 SCI1 (H8/3857 Series Only). 10.2.1 Overview 10.2.2 Register Descriptions. 10.2.3 Operation 10.2.4 Interrupts 10.2.5 Application Notes. 10.3 SCI3 10.3.1 Overview 10.3.2 Register Descriptions. 10.3.3 Operation 10.3.4 Operation Asynchronous Mode. 10.3.5 Operation Synchronous Mode. 10.3.6 Multiprocessor Communication Function. 10.3.7 Interrupts 10.3.8 Application Notes.
Section 14-Bit (H8/3857 Series Only)
11.1 Overview. 11.1.1 Features 11.1.2 Block Diagram. 11.1.3 Configuration 11.1.4 Register Configuration 11.2 Register Descriptions. 11.2.1 Control Register (PWCR). 11.2.2 Data Registers (PWDRU, PWDRL). 11.3 Operation
Section Converter
12.1 Overview. 12.1.1 Features 12.1.2 Block Diagram. 12.1.3 Configuration 12.1.4 Register Configuration 12.2 Register Descriptions. 12.2.1 Result Register (ADRR). 12.2.2 Mode Register (AMR). 12.2.3 Start Register (ADSR). 12.3 Operation 12.3.1 Conversion Operation. 12.3.2 Start Conversion External Trigger Input. 12.4 Interrupts. 12.5 Typical Use. 12.6 Application Notes.
Section Matrix Controller (H8/3857 Series)
13.1 Overview. 13.1.1 Features 13.1.2 Block Diagram. 13.1.3 Configuration 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Index Register (IR) 13.2.2 Control Register (LR0). 13.2.3 Control Register (LR1). 13.2.4 Address Register (LR2). 13.2.5 Frame Frequency Setting Register (LR3) 13.2.6 Display Data Register (LR4). 13.2.7 Display Start Line Register (LR5). 13.2.8 Blink Register (LR6). 13.2.9 Blink Start Line Register (LR8) 13.2.10 Blink Line Register (LR9) 13.2.11 Contrast Control Register (LRA) 13.3 Operation 13.3.1 System Overview. 13.3.2 Interface 13.3.3 Drive Functions. 13.3.4 Display Memory Configuration Display 13.3.5 Display Data Output 13.3.6 Register Display Memory Access 13.3.7 Scroll Function
13.3.8 13.3.9 13.3.10 13.3.11 13.3.12 13.3.13 13.3.14 13.3.15
Blink Function. Module Standby Mode Power-On Power-Off Procedures. Power Supply Circuit Drive Power Supply Voltages Voltage Generation Circuit. Contrast Control Circuit Drive Bias Selection Circuit.
Section Matrix Controller (H8/3854 Series)
14.1 Overview. 14.1.1 Features 14.1.2 Block Diagram. 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Index Register (IR) 14.2.2 Control Register (LR0). 14.2.3 Control Register (LR1). 14.2.4 Address Register (LR2). 14.2.5 Frame Frequency Setting Register (LR3) 14.2.6 Display Data Register (LR4). 14.3 Operation 14.3.1 System Overview. 14.3.2 Interface 14.3.3 Drive Functions. 14.3.4 Display Memory Configuration Display 14.3.5 Display Data Output 14.3.6 Register Display Memory Access 14.3.7 Module Standby Mode 14.3.8 Power-On Power-Off Procedures. 14.3.9 Power Supply Circuit 14.3.10 Drive Power Supply Voltages 14.3.11 Voltage Generation Circuit. 14.3.12 Drive Bias Selection Circuit.
Section Electrical Characteristics (H8/3857 Series)
15.1 H8/3855, H8/3856, H8/3857 Absolute Maximum Ratings (Standard Specifications). 15.2 H8/3855, H8/3856, H8/3857 Electrical Characteristics (Standard Specifications). 15.2.1 Power Supply Voltage Operating Range. 15.2.2 Characteristics.
viii
15.2.3 Characteristics. 15.2.4 Converter Characteristics 15.2.5 Characteristics 15.2.6 Flash Memory Characteristics. 15.3 Operation Timing 15.4 Output Load Circuit. 15.5 Usage Note
Section Electrical Characteristics (H8/3854 Series)
16.1 H8/3852, H8/3853, H8/3854 Absolute Maximum Ratings (Standard Specifications). 16.2 H8/3852, H8/3853, H8/3854 Electrical Characteristics (Standard Specifications). 16.2.1 Power Supply Voltage Operating Range. 16.2.2 Characteristics. 16.2.3 Characteristics. 16.2.4 Converter Characteristics 16.2.5 Characteristics 16.2.6 Flash Memory Characteristics. 16.3 Operation Timing 16.4 Output Load Circuit. 16.5 Usage Note
Appendix Instruction
Instructions Operation Code Map. Number Execution States.
Appendix Internal Registers
Register Addresses B.1.1 H8/3857 Series Addresses. B.1.2 H8/3854 Series Addresses. Register Descriptions.
Appendix Port Block Diagrams
Block Diagram Port Block Diagram Port Block Diagram Port (H8/3857 Series Only) Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port
Appendix Port States Different Processing States Appendix Appendix List Product Codes Package Dimensions
Section Overview
Overview
H8/300L Series series single-chip microcomputers (MCU: microcomputer unit), built around high-speed H8/300L equipped with peripheral system functions on-chip. Within H8/300L Series, H8/3857 Series H8/3854 Series feature on-chip liquid crystal display (LCD) controllers. Other on-chip peripheral functions include controller, timers, serial communication interface, analog-to-digital (A/D) converter. Together these functions make H8/3857 Series H8/3854 Series ideally suited embedded control systems requiring display. H8/3857 Series comprises H8/3855, with kbytes kbytes onchip, H8/3856, with kbytes kbytes RAM, H8/3857, with kbytes kbytes RAM. H8/3854 Series mask versions H8/3852, with kbytes kbyte on-chip, H8/3853, with kbytes kbyte RAM, H8/3854, with kbytes kbyte RAM. F-ZTAT versions-the H8/3857F H8/3854F-are also available, with userprogrammable on-chip flash ROM. These models have kbytes kbytes RAM. Note that H8/3854 mask F-ZTAT versions have different sizes. Table summarizes features H8/3857 Series H8/3854 Series.
Table
Item
Features
Description High-speed H8/300L General-register architecture General registers: Sixteen 8-bit registers (can used eight 16-bit registers) Operating speed Max. operating speed: Add/subtract: (operating MHz) Multiply/divide: (operating MHz) 32.768 subclock Instruction compatible with H8/300 Instruction length bytes bytes Basic arithmetic operations between registers instruction data transfer between memory registers Multiply bits bits) Divide bits bits) accumulator Register-indirect designation position external interrupt sources: IRQ4 WKP0 internal interrupt sources external interrupt sources: IRQ4, IRQ3, IRQ1, IRQ0, WKP0 internal interrupt sources System clock pulse generator: Subclock pulse generator: 32.768 Sleep mode Standby mode Watch mode Subsleep mode Subactive mode Active (medium-speed) mode
Typical instructions Interrupts Power-down modes
H8/3857 Series: interrupt sources
H8/3854 Series: interrupt sources
Clock pulse generators on-chip clock pulse generators
power-down modes
Item Memory
Description H8/3857 Series H8/3855: H8/3856: H8/3857: H8/3857F: H8/3852: H8/3853: H8/3854: H8/3854F: 40-kbyte ROM, 2-kbyte 48-kbyte ROM, 2-kbyte 60-kbyte ROM, 2-kbyte 60-kbyte ROM, 2-kbyte 16-kbyte ROM, 1-kbyte 24-kbyte ROM, 1-kbyte 32-kbyte ROM, 1-kbyte 60-kbyte ROM, 2-kbyte
H8/3854 Series
Note that H8/3854 (mask version) H8/3854F (F-ZTAT version) have different sizes. ports H8/3857 Series: port pins Timers pins: Input pins: pins: Input pins: Timer 8-bit timer Count-up timer with selection eight internal clock signals divided from system clock four clock signals divided from watch clock Timer 8-bit timer Count-up timer with selection seven internal clock signals event input from external Auto-reloading Timer 8-bit timer H8/3857 Series only) Count-up/count-down timer with selection seven internal clock signals event input from external Auto-reloading Timer 16-bit timer used independent 8-bit timers. Count-up timer with selection four internal clock signals event input from external Compare-match function with toggle output
H8/3854 Series: port pins
Four on-chip timers (three H8/3854 Series)
Item Serial communication interface
Description H8/3857 Series: channels chip SCI1: synchronous serial interface Choice 8-bit 16-bit data transfer SCI3: 8-bit synchronous asynchronous serial interface Built-in function multiprocessor communication H8/3854 Series: channel chip SCI3: 8-bit synchronous asynchronous serial interface Built-in function multiprocessor communication
14-bit H8/3857 Series only) converter
Pulse-division output reduced ripple used 14-bit converter connecting external low-pass filter. Successive approximations using resistance ladder resolution: bits 8-channel analog input port Conversion time: channel Successive approximations using resistance ladder resolution: bits 4-channel analog input port Conversion time: channel Choice three duty cycles (1/8, 1/16, 1/32) With duty selected: COM, With 1/16 duty selected: COM, With 1/32 duty selected: Built-in 2048-bit display data Built-in step-up circuit Built-in contrast control circuit Built-in power supply bleeder resistance voltage follower opamp circuits Choice duty cycles (1/8, 1/16) With duty selected: With 1/16 duty selected: Built-in 640-bit display data Built-in power supply bleeder resistance
H8/3857 Series
H8/3854 Series
controller
H8/3857 Series: segment pins common pins
H8/3854 Series: segment pins common pins
Item Product lineup
Description H8/3857 Series
Product Code Mask Version HD6433855FQ HD6433855TG HCD6433855 HD6433856FQ HD6433856TG HCD6433856 HD6433857FQ HD6433857TG HCD6433857 F-ZTAT Version HD64F3857FQ HD64F3857TG HCD64F3857 Package 144-pin (FP-144H) 144-pin TQFP (TFP-144) 144-pin (FP-144H) 144-pin TQFP (TFP-144) 144-pin (FP-144H) 144-pin TQFP (TFP-144) ROM: kbytes RAM: kbytes ROM: kbytes RAM: kbytes ROM/RAM Size ROM: kbytes RAM: kbytes
H8/3854 Series
Product Code Mask Version*2 HD6433852H HD6433852W HCD6433852 HD6433853H HD6433853W HCD6433853 HD6433854H HD6433854W HCD6433854 F-ZTAT Version HD64F3854H HD64F3854W HCD64F3854 Package 100-pin (FP-100B) ROM/RAM Size ROM: kbytes
100-pin TQFP (TFP-100G) RAM: kbyte 100-pin (FP-100B) ROM: kbytes
100-pin TQFP (TFP-100G) RAM: kbyte 100-pin (FP-100B) ROM: kbytes
100-pin TQFP (TFP-100G) RAM: kbyte 100-pin (FP-100B) ROM: kbytes
100-pin TQFP (TFP-100G) RAM: kbytes
Notes: defined section Clock Pulse Generators. Under development
Internal Block Diagram
Figures show internal block diagrams H8/3857 Series H8/3854 Series.
OSC1 OSC2
System clock oscillator
Subclock oscillator
(8-bit) Address
FLASH/ MASK
Data (upper)
P10/TMOW P11/TMOFL P12/TMOFH P14/PWM P15/IRQ1/TMIB P16/IRQ2/TMIC P17/IRQ3/TMIF P20/IRQ4/ADTRG P21/UD P30/SCK1 P31/SI1 P32/SO1
Data (lower) Port
TEST2 TEST
Port
Timer
SCI3
Port
STRB
Timer
SCI1
P57/WKP7 P56/WKP6 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 AVCC AVSS
Port
Timer
P40/SCK3 P41/RXD P42/TXD P43/IRQ0
Port
14-bit
Port
Port
Internal port
V5OUT V4OUT V3OUT V2OUT V1OUT VLCD
Port
Timer
VLOUT SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9/SEG64 COM10/SEG63 COM11/SEG62 COM12/SEG61 COM13/SEG60 COM14/SEG59 COM15/SEG58 COM16/SEG57 COM29/SEG44 COM30/SEG43 COM31/SEG42 COM32/SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33
Figure H8/3857 Series Internal Block Diagram
OSC1 OSC2
System clock oscillator
Subclock oscillator
(8-bit)
FLASH/ MASK
Address
P10/TMOW P11/TMOFL P12/TMOFH P15/IRQ1/TMIB P17/IRQ3/TMIF
Data (upper)
Data (lower) Port
TEST2 TEST
P20/IRQ4/ADTRG
Port
Timer
SCI3
P40/SCK3 P41/RXD P42/TXD P43/IRQ0
Port
Port
Port
Internal port
V1OUT V2OUT V3OUT V4OUT V5OUT
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
Figure H8/3854 Series Internal Block Diagram
STRB
Port
Timer
Port
Timer
P57/WKP7 P56/WKP6 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0
PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4
1.3.1
Arrangement Functions
Arrangement
arrangements H8/3857 Series H8/3854 Series shown figures 1.4. HCD64F3857 layout shown figure 1.5, coordinates table 1.2; HCD6433855, HCD6433856, HCD6433857 layout shown figure 1.6, coordinates table 1.3; HCD64F3854 layout shown figure 1.7, coordinates table 1.4; HCD6433852, HCD6433853, HCD6433854 layout shown figure 1.8, coordinates table 1.5.
COM17/SEG56 COM18/SEG55 COM19/SEG54 COM20/SEG53 COM21/SEG52 COM22/SEG51 COM23/SEG50 COM24/SEG49 COM25/SEG48 COM26/SEG47 COM27/SEG46 COM28/SEG45 COM29/SEG44 COM30/SEG43 COM31/SEG42 COM32/SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21
V5OUT V4OUT V3OUT V2OUT V1OUT VLOUT VLCD P32/SO1 P31/SI1 P30/SCK1 P17/IRQ3/TMIF P16/IRQ2/TMIC P15/IRQ1/TMIB P14/PWM P12/TMOFH P11/TMOFL P10/TMOW P43/IRQ0 P42/TXD P41/RXD P40/SCK3
H8/3857
(Top view) FP-144H TFP-144
SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM16/SEG57 COM15/SEG58 COM14/SEG59 COM13/SEG60 COM12/SEG61 COM11/SEG62 COM10/SEG63 COM9/SEG64 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
Figure H8/3857 Series Arrangement (FP-144H, TFP-144: View)
P57/WKP7 P56/WKP6 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 P21/UD P20/IRQ4/ADTRG AVCC PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 AVSS OSC2 OSC1 TEST TEST2
SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 V5OUT V4OUT V3OUT V2OUT V1OUT P17/IRQ3/TMIF P15/IRQ1/TMIB P12/TMOFH P11/TMOFL P10/TMOW P43/IRQ0 P42/TXD P41/RXD P40/SCK3 P57/WKP7
SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6
H8/3854
(Top view) FP-100B TFP-100G
SEG5 SEG4 SEG3 SEG2 SEG1 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4
Figure H8/3854 Series Arrangement (FP-100B, TFP-100G: View)
P56/WKP6 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 P20/IRQ4/ADTRG TEST2 OSC2 OSC1 TEST
Model
Model: HD64F3857 Chip size: 7.08mm 7.31
Figure Layout HCD64F3857 (F-ZTAT Version) (Top View)
Table
Name /WKP7 /WKP6 /WKP5 /WKP4 NC4* /WKP3 NC3* /WKP2 NC2* /WKP1 NC1* /WKP0
HCD64F3857 Coordinates
Coordinates* (µm) (µm) -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 2928 2784 2640 2506 2372 2238 2044 1854 1720 1590 1456 1316 1173 1039 -143 -273 -403 -533 -663 -793 -923 -1053 -1228 -1438 -1568 -1763 -1981 -2134 Name TEST TEST2 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9/SEG64 COM10/SEG63 COM11/SEG62 COM12/SEG61 COM13/SEG60 COM14/SEG59 COM15/SEG58 COM16/SEG57 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 Coordinates* (µm) (µm) -3348 -3348 -3348 -3348 -3348 -2862 -2700 -2536 -2374 -2210 -2046 -1884 -1720 -1556 -1394 -1231 -1069 -905 -741 -579 -415 -251 1055 1217 1380 1542 1706 1870 -2264 -2404 -2599 -2794 -2944 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 Name SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 COM32/SEG41 COM31/SEG42 COM30/SEG43 COM29/SEG44 COM28/SEG45 COM27/SEG46 COM26/SEG47 Coordinates* (µm) (µm) 2032 2196 2360 2522 2686 2848 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 -3463 -3463 -3463 -3463 -3463 -3463 -2907 -2747 -2587 -2427 -2267 -2107 -1947 -1787 -1627 -1467 -1307 -1148 -988 -828 -668 -508 -348 -188 1092 1252 1411 1571
/IRQ4 /ADTRG -3348 AVCC /AN0 /AN1 /AN2 /AN3 /AN4 /AN5 /AN6 /AN7 AVSS OSC2 OSC1 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348
COM25/SEG48 COM24/SEG49
Name COM23/SEG50 COM22/SEG51 COM21/SEG52 COM20/SEG53 COM19/SEG54 COM18/SEG55 COM17/SEG56 V5OUT V4OUT V3OUT V2OUT V1OUT
Coordinates* (µm) (µm) 3348 3348 3348 3348 3348 3348 3348 2776 2616 2456 2296 2136 1976 1816 1656 1731 2063 2223 2383 2543 2703 2863 3463 3463 3463 3463 3463 3463 3463 3463
Name VLOUT /SO1 /Sl1
Coordinates* (µm) (µm) 1471 1341 1125 -234 -386 -538 -690 -848 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463
Name /SCK1 /IRQ3/TMIF /IRQ2/TMIC /IRQ1/TMIB /PWM /TMOFH /TMOFL /TMOW /IRQ0 /TXD /RXD /SCK3
Coordinates* (µm) (µm) -982 -1116 -1250 -1383 -1611 -1761 -1911 -2045 -2180 -2447 -2587 -2737 -2888 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463
Notes: Numbers indicate coordinates center area, with accuracy origin center chip, center point halfway between pads, horizontally vertically. test pads; they should left open.
Model
Model: HD643385rccc Number denoting size 60-kbyte version 48-kbyte version 40-kbyte version ccc: code Chip size: 6.21 6.21
Figure Layout HCD6433855, HCD6433856, HCD6433857 (Mask Version) (Top View)
Table
Name /WKP7 /WKP6 /WKP5 /WKP4 /WKP3 /WKP2 /WKP1 /WKP0
HCD6433855, HCD6433856, HCD6433857 Coordinates
Coordinates* (µm) (µm) -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 2515 2365 2215 2070 1930 1795 1660 1530 1400 1271 1141 1011 -135 -265 -395 -525 -655 -785 -960 -1169 -1299 -1428 -1581 -1734 -1874 -2024 -2189 -2384 Name FWE*2 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9/SEG64 COM10/SEG63 COM11/SEG62 COM12/SEG61 COM13/SEG60 COM14/SEG59 COM15/SEG58 COM16/SEG57 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 Coordinates* (µm) (µm) -2913 -2495 -2305 -2125 -1955 -1795 -1645 -1505 -1365 -1235 -1105 -975 -845 -715 -585 -455 -325 -195 1105 1235 1365 1505 1645 1795 1955 2125 -2534 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 Name SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 COM32/SEG41 COM31/SEG42 COM30/SEG43 COM29/SEG44 COM28/SEG45 COM27/SEG46 COM26/SEG47 Coordinates* (µm) (µm) 2305 2495 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 -2913 -2913 -2495 -2305 -2125 -1955 -1795 -1645 -1505 -1365 -1235 -1105 -975 -845 -715 -585 -455 -325 -195 1105 1235 1365 1505 1645 1795 1955
/IRQ4 /ADTRG -2913 AVCC /AN0 /AN1 /AN2 /AN3 /AN4 /AN5 /AN6 /AN7 AVSS OSC2 OSC1 TEST TEST2 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913
COM25/SEG48 COM24/SEG49 COM23/SEG50 COM22/SEG51 COM21/SEG52 COM20/SEG53
Name COM19/SEG54 COM18/SEG55 COM17/SEG56 V5OUT V4OUT V3OUT V2OUT V1OUT
Coordinates* (µm) (µm) 2913 2913 2913 2435 2275 2125 1975 1825 1675 1520 1385 1255 1125 2125 2305 2495 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913
Name VLOUT /SO1 /Sl1
Coordinates* (µm) (µm) -195 -325 -455 -585 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913
Name /SCK1 /IRQ3/TMIF /IRQ2/TMIC /IRQ1/TMIB /PWM /TMOFH /TMOFL /TMOW /IRQ0 /TXD /RXD /SCK3
Coordinates* (µm) (µm) -715 -845 -975 -1105 -1235 -1365 -1505 -1645 -1795 -1955 -2125 -2305 -2495 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913
Notes: Numbers indicate coordinates center area, with accuracy origin center chip, center point halfway between pads, horizontally vertically. Connect
19-1 19-2
Model
Model: HD64F3854 Chip size: 6.34 6.34
Figure Layout HCD64F3854 (F-ZTAT Version) (Top View)
Table
Name /WKP6 /WKP5 NC1* /WKP4 /WKP3 /WKP2 NC2* /WKP1 NC3* /WKP0
HCD64F3854 Coordinates
Coordinates* (µm) (µm) -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 2494 2333 2139 1950 1788 1626 1419 1215 1054 -234 -396 -558 -716 -873 -1031 -1267 -1526 -1707 -1864 -2101 -2336 -2494 -2985 -2985 -2985 -2985 -2985 Name COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 Coordinates* (µm) (µm) -1413 -1210 -1006 -801 -597 -393 -189 1035 1240 1443 1647 1851 2055 2259 2463 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2433 -2229 -2025 -1821 -1617 -1413 -1210 -1005 -801 -597 -393 -189 Name SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 V5OUT V4OUT V3OUT V2OUT V1OUT /IRQ3 /TMIF /IRQ1 /TMIB /TMOFH /TMOFL /TMOW /IRQ0 /TXD /RXD /SCK3 Coordinates* (µm) (µm) 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2435 2234 2032 1830 1629 1427 1226 1025 -171 -372 -574 -780 -985 -1191 -1396 -1618 -1820 -2022 -2234 -2446 1036 1240 1443 1647 1851 2055 2259 2463 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985
/IRQ4 /ADTRG -2985 TEST2 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2448 -2244 -2040 -1836 -1617
19-1 SS*3 19-2 SS*3 OSC2 OSC1 TEST /AN4 /AN5 /AN6 /AN7 COM1
/WKP7
Notes: Numbers indicate coordinates center area, with accuracy origin center chip, center point halfway between pads, horizontally vertically. test pads; they should left open. Connect both 19-1 19-2
Model
Model: HD643385rccc Number denoting size 32-kbyte version 24-kbyte version 16-kbyte version ccc: code Chip size: 4.69 4.69
Figure Layout HCD6433854, HCD6433853, HCD6433852 (Mask Version) (Top View)
Table
Name /WKP6 /WKP5 /WKP4 /WKP3 /WKP2 /WKP1 /WKP0
HCD6433852, HCD6433853, HCD6433854 Coordinates
Coordinates* (µm) (µm) -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 1738 1590 1445 1305 1171 1041 -129 -259 -389 -519 -764 -1020 -1173 -1312 -1497 -1657 -1821 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 Name COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 Coordinates* (µm) (µm) -390 -260 -130 1060 1213 1383 1551 1721 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -1721 -1551 -1383 -1213 -1060 -910 -780 -650 -520 -390 -260 -130 Name SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 V5OUT V4OUT V3OUT V2OUT V1OUT /IRQ3 /TMIF /IRQ1 /TMIB /TMOFH /TMOFL /TMOW /IRQ0 /TXD /RXD /SCK3 Coordinates* (µm) (µm) 2161 2161 2161 2161 2161 2161 2161 2161 1716 1565 1422 1282 1150 1020 -193 -323 -453 -583 -713 -843 -973 -1104 -1244 -1383 -1534 -1698 1060 1213 1383 1551 1721 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161
/IRQ4 /ADTRG -2161 TEST2 OSC2 OSC1 TEST FWE* /AN4 /AN5 /AN6 /AN7 COM1 COM2 COM3 COM4 COM5 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -1722 -1552 -1395 -1236 -1060 -910 -780 -650 -520
/WKP7
Notes: Numbers indicate coordinates center area, with accuracy origin center chip, center point halfway between pads, horizontally vertically. Connect
1.3.2
Functions
Table outlines functions H8/3857 Series. Table Functions
H8/3857 Series Type Power source pins Symbol FP-144H TFP-144 H8/3854 Series FP-100B TFP-100G Input Name Functions Power supply: pins should connected system power supply Ground: pins should connected system power supply Analog power supply (H8/3857 Series only): This power supply converter. When converter used, connect this system power supply Analog ground (H8/3857 Series only): This converter ground pin. should connected system power supply This connects crystal ceramic oscillator. section Clock Pulse Generators, typical connection diagram. This connects 32.768-kHz crystal oscillator, used input external clock. section Clock Pulse Generators, typical connection diagram.
19-1, 19-2
Input
Input
Input
Clock pins
OSC1 OSC2
Input Output
Input
Output
H8/3857 Series Type System control Symbol FP-144H TFP-144
H8/3854 Series FP-100B TFP-100G Input Input Name Functions Reset: When this driven low, chip reset Flash write enable: This enables disables flash memory programming. mask version, ground this potential. Test: This test pin, application systems. should connected VSS. Test pin: This sets flash memory operating mode. mask version, ground this potential. External interrupt request (H8/3857 Series) External interrupt request (H8/3854 Series) These input pins external interrupts which there choice between rising falling edge sensing.
TEST
Input
TEST2
Input
Interrupt pins
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4
Input
WKP7 WKP0
100,
100,
Input
Wakeup interrupt request These input pins external interrupts that detected falling edge Clock output: This output waveforms generated timer output circuit Timer event counter input: This event input input timer counter Timer event counter input (H8/3857 Series only): This event input input timer counter
Timer pins
TMOW
Output
TMIB
Input
TMIC
Input
H8/3857 Series Type Timer pins Symbol FP-144H TFP-144
H8/3854 Series FP-100B TFP-100G Input Name Functions Timer up/down select (H8/3857 Series only): This selects whether timer counter used down-counting. high level selects upcounting, level down-counting. Timer event counter input: This event input input timer counter Timer output: This output waveforms generated timer output compare function Timer output: This output waveforms generated timer output compare function 14-bit output (H8/3857 Series only): This output waveforms generated 14-bit Port This 8-bit input port H8/3857 Series, 4-bit input port H8/3854 Series Port (bit This 1-bit input port Port (bits This 3-bit port. Input output designated each means port control register (PCR4). Port This 8-bit port H8/3857 Series, 5-bit port H8/3854 Series. Input output designated each means port control register (PCR1).
TMIF
Input
TMOFL
Output
TMOFH
Output
14-bit
Output
ports
Input
Input
P17, P16, P15, P14, P13,
136,
136,
H8/3857 Series Type Symbol FP-144H TFP-144
H8/3854 Series FP-100B TFP-100G Name Functions Port This 8-bit port. Input output designated each means port control register (PCR2). Port (H8/3857 Series only): This 8-bit port. Input output designated each means port control register (PCR3). Port This 8-bit port. Input output designated each means port control register (PCR5). Port This 4-bit port. Input output designated each means port control register (PCRA). connected internally pins R/W, STRB. Port This 8-bit port. Input output designated each means port control register (PCR9). connected internally pins DB0. SCI1 receive data input (H8/3857 Series only): This SCI1 data input SCI1 send data output (H8/3857 Series only): This SCI1 data output SCI1 clock (H8/3857 Series only): This SCI1 clock SCI3 receive data input: This SCI3 data input
ports
100,
100,
Internal ports
Serial communication interface (SCI)
Input
Output
SCK1
Input
H8/3857 Series Type Symbol FP-144H TFP-144
H8/3854 Series FP-100B TFP-100G Output Name Functions SCI3 send data output: This SCI3 data output SCI3 clock This SCI3 clock Analog input (channels H8/3857 Series, channels H8/3854 Series): These analog data input channels converter converter trigger input: This external trigger input converter common output: These common output pins. maximum number pins H8/3857 Series, H8/3854 Series. standby mode module standby mode, pins output level. segment output: These segment output pins. maximum number pins H8/3857 Series, H8/3854 Series. standby mode module standby mode, pins output level. bias setting pins (H8/3857 Series only): bias drive selected when shorted, bias drive when left open. test (H8/3857 Series only): This built-in resistance test pin. must shorted.
Serial communication interface (SCI)
Input
converter
ADTRG
Input
COM32 controller COM17 COM16 COM1
Output
SEG64 SEG41 SEG40 SEG1
Output
116,
116,
Input
Input
H8/3857 Series Type Symbol FP-144H TFP-144
H8/3854 Series FP-100B TFP-100G Name Functions step-up circuit capacitance connection pins (H8/3857 Series only): These pins connect external capacitances step-up. Connect capacitances according step-up factor. drive power supply level (H8/3857 Series): When OPON high, these bits output drive power supply levels built-in opamp drive capacity inadequate, connect capacitor provide stabilization. levels input from external source, OPON low. step-up circuit reference power supply (H8/3857 Series only): This doubles step-up circuit reference input voltage step-up circuit power supply, provides drive voltage. VCC. step-up circuit used, connect VCC. step-up voltage output (H8/3857 Series only): This stepup voltage output pin. Connect capacitance. drive power supply (H8/3857 Series only): This drive power supply input pin. builtin step-up circuit output voltage used drive power supply, short this VLOUT. VLCD
C1+, C1-, controller C2+,
H8/3857 V1OUT Series V5OUT power supply
Input
VLOUT
Output
VLCD
Input
H8/3857 Series Type Symbol FP-144H TFP-144
H8/3854 Series FP-100B TFP-100G Name Functions drive power supply level (H8/3854 Series): When LPS1 LPS0 bits high, these pins output drive power supply levels drive capacity inadequate, connect capacitor provide stabilization. levels input from external source, LPS1 LPS0 bits low. levels must exceed VCC. When driving with bias, short V3OUT V4OUT.
H8/3854 V1OUT Series V5OUT power supply
Section
Overview
H8/300L sixteen 8-bit general registers, which also paired eight 16-bit registers. concise, optimized instruction designed high-speed operation. 2.1.1 Features
Features H8/300L listed below. General-register architecture Sixteen 8-bit general registers, also usable eight 16-bit general registers Instruction with basic instructions, including: Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment pre-decrement Absolute address Immediate Program-counter relative Memory indirect 64-kbyte address space High-speed operation frequently used instructions executed four states High-speed arithmetic logic operations 16-bit register-register subtract: 8-bit multiply: 8-bit divide: Note: These values MHz. Low-power operation modes SLEEP instruction transfer low-power operation
2.1.2
Address Space
H8/300L supports address space kbytes storing program code data. 2.8, Memory Map, details memory map. 2.1.3 Register Configuration
Figure shows register structure H8/300L CPU. There groups registers: general registers control registers.
General registers (Rn) (SP) Stack Pointer
Control registers (CR) UHUNZ Program Counter CCR: Condition Code Register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask User User
Figure Registers
2.2.1
Register Descriptions
General Registers
general registers used both data registers address registers. When used data registers, they accessed 16-bit registers R7), high bytes (R0H R7H) bytes (R0L R7L) accessed separately 8-bit registers. When used address registers, general registers accessed 16-bit registers R7). also functions stack pointer (SP), used implicitly hardware exception processing subroutine calls. When functions stack pointer, indicated figure 2.2, (R7) points stack.
Lower address side [H'0000]
Unused area (R7) Stack area
Upper address side [H'FFFF]
Figure Stack Pointer 2.2.2 Control Registers
control registers include 16-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates address next instruction will execute. instructions fetched bits word) time, least significant ignored (always regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. These bits read written software (using LDC, STC, ANDC, ORC, XORC instructions). flags used branching conditions conditional branching (Bcc) instructions.
7-Interrupt Mask (I): When this interrupts masked. This automatically start exception handling. interrupt mask read written software. further details, section 3.3, Interrupts. 6-User (U): used freely user. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. flag used implicitly instructions. When ADD.W, SUB.W, CMP.W instruction executed, flag there carry borrow cleared otherwise. 4-User (U): used freely user. 3-Negative Flag (N): Indicates most significant (sign bit) result instruction. 2-Zero Flag (Z): indicate zero result, cleared indicate non-zero result. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when operation execution generates carry, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions carry flag also used accumulator manipulation instructions. Some instructions leave some flag bits unchanged. Refer H8/300L Series Programming Manual action each instruction flag bits.
2.2.3
Initial Register Values
When reset, program counter (PC) initialized value stored address H'0000 vector table, other bits general registers initialized. particular, stack pointer (R7) initialized. prevent program crashes stack pointer should initialized software, first instruction executed after reset.
Data Formats
H8/300L process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, 16-bit (word) data. manipulation instructions operate 1-bit data specified byte operand arithmetic logic instructions except ADDS SUBS operate byte data. MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions operate word data. instructions perform decimal arithmetic adjustments byte data packed form. Each nibble byte treated decimal digit.
2.3.1
Data Formats General Registers
general register data formats shown figure 2.3.
Data Type Register
Data Format
1-bit data
don't care
1-bit data
don't care
Byte data
don't care
Byte data
don't care
Word data
Upper digit
Lower digit
4-bit data
don't care
Upper digit
Lower digit
4-bit data
don't care
Notation: RnH: Upper byte general register RnL: Lower byte general register MSB: Most significant LSB: Least significant
Figure Register Data Formats
2.3.2
Memory Data Formats
Figure indicates data formats memory. access H8/300L CPU, word data stored memory must always begin even address. word access least significant address regarded address specified, access performed preceding even address. This rule affects MOV.W instruction, also applies instruction fetching.
Data Type Address Data Format
1-bit data Byte data
Address Address Even address address Even address address Even address address
Word data
Upper bits Lower bits
Byte data (CCR) stack
CCR*
Word data stack
CCR: Condition code register Note: Ignored return
Figure Memory Data Formats When stack accessed using address register, word access should always performed. CCR, same value stored upper bits lower bits word data. return, lower bits ignored.
2.4.1
Addressing Modes
Addressing Modes
H8/300L supports eight addressing modes listed table 2.1. Each instruction uses subset these addressing modes. Table
Addressing Modes
Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Symbol @(d:16, @Rn+ @-Rn @aa:8 @aa:16 #xx:8 #xx:16 @(d:8, @@aa:8
Absolute address Immediate Program-counter relative Memory indirect
Register Direct-Rn: register field instruction specifies 16-bit general register containing operand. Only MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions have 16-bit operands. Register Indirect-@Rn: register field instruction specifies 16-bit general register containing address operand memory. Register Indirect with Displacement-@(d:16, Rn): instruction second word (bytes containing 16-bit displacement which added contents specified general register (16-bit) obtain operand address memory. This mode used only instructions. MOV.W instruction, resulting address must even.
Register Indirect with Post-Increment Pre-Decrement-@Rn+ @-Rn: Register indirect with post-increment-@Rn+ @Rn+ mode used with instructions that load registers from memory. register field instruction specifies 16-bit general register containing address operand. After operand accessed, register incremented MOV.B MOV.W. MOV.W, original contents 16-bit general register must even. Register indirect with pre-decrement-@-Rn @-Rn mode used with instructions that store register contents memory. register field instruction specifies 16-bit general register which decremented obtain address operand memory. register retains decremented value. size decrement MOV.B MOV.W. MOV.W, original contents register must even. Absolute Address-@aa:8 @aa:16: instruction specifies absolute address operand memory. absolute address bits long (@aa:8) bits long (@aa:16). MOV.B manipulation instructions 8-bit absolute addresses. MOV.B, MOV.W, JMP, instructions 16-bit absolute addresses. 8-bit absolute address, upper bits assumed (H'FF). address range H'FF00 H'FFFF (65280 65535). Immediate-#xx:8 #xx:16: instruction contains 8-bit operand (#xx:8) second byte, 16-bit operand (#xx:16) third fourth bytes. Only MOV.W instructions contain 16-bit immediate values. ADDS SUBS instructions implicitly contain value immediate data. Some manipulation instructions contain 3-bit immediate data second fourth byte instruction, specifying number. Program-Counter Relative-@(d:8, PC): This mode used instructions. 8-bit displacement byte instruction code sign-extended bits added program counter contents generate branch destination address. possible branching range -126 +128 bytes (-63 words) from current address. displacement should even number.
Memory Indirect-@@aa:8: This mode used instructions. second byte instruction code specifies 8-bit absolute address. word located this address contains branch destination address. upper bits absolute address assumed (H'00), address range from H'0000 H'00FF 255). Note that with H8/300L Series, lower address area also used vector area. 3.3, Interrupts, details vector area. address specified branch destination operand address MOV.W instruction, least significant regarded causing word access performed address preceding specified address. 2.3.2, Memory Data Formats, further information. 2.4.2 Effective Address Calculation
Table shows effective addresses calculated each addressing modes. Arithmetic logic instructions register direct addressing (1). ADD.B, ADDX, SUBX, CMP.B, AND, instructions also immediate addressing (6). Data transfer instructions addressing modes except program-counter relative memory indirect (8). manipulation instructions register direct (1), register indirect (2), absolute addressing (8bit) specify byte operand, 3-bit immediate addressing specify position that byte. BSET, BCLR, BNOT, BTST instructions also register direct addressing specify position.
Table
Effective Address Calculation
Effective Address Calculation Method Effective Address (EA)
Addressing Mode Instruction Format Register direct,
Operand contents registers indicated rm/rn
Contents bits) register indicated
Register indirect,
Contents bits) register indicated
Register indirect with displacement, @(d:16,
disp
disp
Register indirect with post-increment, @Rn+
Contents bits) register indicated
Register indirect with pre-decrement, @-Rn
Contents bits) register indicated
Incremented decremented operand byte size, word size
Addressing Mode Instruction Format Absolute address @aa:8
Effective Address Calculation Method
Effective Address (EA)
H'FF
@aa:16
Immediate #xx:8
#xx:16
Operand 2-byte immediate data
Program-counter relative @(d:8,
contents
Sign extension
disp
disp
Addressing Mode Instruction Format
Memory indirect, @@aa:8
Effective Address Calculation Method
Effective Address (EA)
H'00
Memory contents bits)
Notation: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address
Instruction
H8/300L Series total instructions, which grouped function table 2.3. Table
Function Data transfer Arithmetic operations Logic operations Shift manipulation Branch System control Block data transfer
Instruction
Instructions MOV, PUSH* POP*
Number Total:
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc* JMP, BSR, JSR, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Notes: PUSH equivalent MOV.W @-SP. equivalent MOV.W @SP+, machine language also same. generic term conditional branch instructions.
functions instructions shown tables 2.11. meaning operation symbols used tables follows.
Notation
(EAd), <EAd> (EAs), <EAs> #IMM disp General register (destination) General register (source) General register Destination operand Source operand Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move Logical negation (logical complement) 3-bit length 8-bit length 16-bit length Contents operand indicated effective address
2.5.1
Data Transfer Instructions
Table describes data transfer instructions. Figure shows their object code formats. Table
Instruction
Data Transfer Instructions
Size* Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, @Rn+ addressing modes available byte word data. @aa:8 addressing mode available byte data only. @-R7 @R7+ modes require word operands. specify byte size these modes.
@SP+ Pops 16-bit general register from stack. Equivalent MOV.W @SP+,
PUSH
@-SP Pushes 16-bit general register onto stack. Equivalent MOV.W @-SP.
Note: Size: Operand size Byte Word
Certain precautions required data access. 2.9.1, Notes Data Access, details.
RmRn
@RmRn
disp
@(d:16, Rm)Rn
@Rm+Rn, @-Rm
@aa:8Rn
@aa:16Rn
#xx:8Rn
#xx:16Rn
Notation: Operation field Register field disp: Displacement abs: Absolute address IMM: Immediate data
PUSH, @SP+ @-SP
Figure Data Transfer Instruction Codes
2.5.2
Arithmetic Operations
Table describes arithmetic instructions. Table
Instruction
Arithmetic Instructions
Size* Function #IMM Performs addition subtraction data general registers, addition immediate data data general register. Immediate data cannot subtracted from data general register. Word data added subtracted only when both words general registers. #IMM Performs addition subtraction with carry borrow byte data general registers, addition subtraction immediate data data general register. Increments decrements general register Adds subtracts immediate data from data general register. immediate data must decimal adjust Decimal-adjusts (adjusts packed 4-bit BCD) addition subtraction result general register referring Performs 8-bit 8-bit unsigned multiplication data general registers, providing 16-bit result
ADDX SUBX
ADDS SUBS MULXU
DIVXU
Performs 16-bit 8-bit unsigned division data general registers, providing 8-bit quotient 8-bit remainder
#IMM Compares data general register with data another general register with immediate data, result stored CCR. Word data compared only between general registers.
Obtains two's complement (arithmetic complement) data general register
Note: Size: Operand size Byte Word
2.5.3
Logic Operations
Table describes four instructions that perform logic operations. Table
Instruction
Logic Operation Instructions
Size* Function #IMM Performs logical operation general register another general register immediate data
#IMM Performs logical operation general register another general register immediate data
#IMM Performs logical exclusive operation general register another general register immediate data
Obtains one's complement (logical complement) general register contents
Note: Size: Operand size Byte
2.5.4
Shift Operations
Table describes eight shift instructions. Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: Size: Operand size Byte
Shift Instructions
Size* Function shift Performs arithmetic shift operation general register contents shift Performs logical shift operation general register contents rotate Rotates general register contents rotate Rotates general register contents through carry flag.
Figure shows instruction code format arithmetic, logic, shift instructions.
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG,
MULXU, DIVXU
ADD, ADDX, SUBX, (#XX:8)
AND, (Rm)
AND, (#xx:8)
Notation: Operation field Register field IMM: Immediate data
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure Arithmetic, Logic, Shift Instruction Codes
2.5.5
Manipulations
Table describes bit-manipulation instructions. Figure shows their object code formats. Table
Instruction BSET
Bit-Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory operand. number specified 3-bit immediate data lower three bits general register.
BCLR
(<bit-No.> <EAd>) Clears specified general register memory operand. number specified 3-bit immediate data lower three bits general register.
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register.
BTST
(<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register.
BAND
(<bit-No.> <EAd>) ANDs flag with specified general register memory operand, stores result flag.
BIAND
(<bit-No.> <EAd>)] ANDs flag with inverse specified general register memory operand, stores result flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) flag with specified general register memory operand, stores result flag.
BIOR
(<bit-No.> <EAd>)] flag with inverse specified general register memory operand, stores result flag. number specified 3-bit immediate data.
Note: Size: Operand size Byte
Instruction BXOR
Size*
Function (<bit-No.> <EAd>) XORs flag with specified general register memory operand, stores result flag.
BIXOR
[~(<bit-No.> <EAd>)] XORs flag with inverse specified general register memory operand, stores result flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies specified general register memory operand flag.
BILD
(<bit-No.> <EAd>) Copies inverse specified general register memory operand flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies flag specified general register memory operand.
BIST
(<bit-No.> <EAd>) Copies inverse flag specified general register memory operand. number specified 3-bit immediate data.
Note: Size: Operand size Byte
Certain precautions required manipulation. 2.9.2, Notes Manipulation, details.
BSET, BCLR, BNOT, BTST
Operand: register direct (Rn) No.: immediate (#xx:3) Operand: register direct (Rn) No.: register direct (Rm)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: register indirect (@Rn) No.:
register direct (Rm)
Operand: absolute (@aa:8) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: register direct (Rm)
BAND, BOR, BXOR, BLD,
Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Notation: Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes
BIAND, BIOR, BIXOR, BILD, BIST
Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Notation: Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes (cont)
2.5.6
Branching Instructions
Table describes branching instructions. Figure shows their object code formats. Table
Instruction
Branching Instructions
Size Function Branches designated address specified condition true. branching conditions given below. Mnemonic (BT) (BF) (BHS) (BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address Branches subroutine specified address Branches subroutine specified address Returns from subroutine
disp
(@Rm)
(@aa:16)
(@@aa:8)
disp
(@Rm)
(@aa:16)
(@@aa:8)
Notation: Operation field Condition field Register field disp: Displacement abs: Absolute address
Figure Branching Instruction Codes
2.5.7
System Control Instructions
Table 2.10 describes system control instructions. Figure shows their object code formats. Table 2.10 System Control Instructions
Instruction SLEEP Size* Function Returns from exception-handling routine Causes transition from active mode power-down mode. section Power-Down Modes, details CCR, #IMM Moves immediate data general register contents condition code register Copies condition code register specified general register ANDC #IMM Logically ANDs condition code register with immediate data #IMM Logically condition code register with immediate data XORC #IMM Logically exclusive-ORs condition code register with immediate data Only increments program counter Note: Size: Operand size Byte
RTE, SLEEP,
LDC, (Rn)
Notation: Operation field Register field IMM: Immediate data
ANDC, ORC, XORC, (#xx:8)
Figure System Control Instruction Codes
2.5.8
Block Data Transfer Instruction
Table 2.11 describes block data transfer instruction. Figure 2.10 shows object code format. Table 2.11 Block Data Transfer Instruction
Instruction EEPMOV Size Function then repeat until else next; Block transfer instruction. Transfers number bytes specified R4L, from locations starting address specified locations starting address specified completion transfer, next instruction executed. @R5+ @R6+
Certain precautions required using EEPMOV instruction. 2.9.3, Notes EEPMOV Instruction, details.
Notation: Operation field
Figure 2.10 Block Data Transfer Instruction Code
Basic Operational Timing
operation synchronized system clock subclock (SUB). details these clock signals section Clock Pulse Generators. period from rising edge next rising edge called state. cycle consists states three states. cycle differs depending whether access on-chip memory on-chip peripheral modules. 2.6.1 Access On-Chip Memory (RAM, ROM)
Access on-chip memory takes place states. data width bits, allowing access byte word size. Figure 2.11 shows on-chip memory access cycle.
cycle state state
Internal address
Address
Internal read signal Internal data (read access)
Read data
Internal write signal Internal data (write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
2.6.2
Access On-Chip Peripheral Modules
On-chip peripheral modules accessed states three states. data width bits, access byte size only. This means that accessing word data, instructions must used. Figures 2.12 2.13 show on-chip peripheral module access cycle. Two-State Access On-Chip Peripheral Modules
cycle state state
Internal address
Address
Internal read signal Internal data (read access)
Read data
Internal write signal Internal data (write access)
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
Three-State Access On-Chip Peripheral Modules
cycle state state state
Internal address Internal read signal Internal data (read access) Internal write signal Internal data (write access) Write data Read data
Address
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
2.7.1
States
Overview
There four states: reset state, program execution state, program halt state, exception-handling state. program execution state includes active (high-speed mediumspeed) mode subactive mode. program halt state there sleep mode, standby mode, watch mode, sub-sleep mode. These states shown figure 2.14. Figure 2.15 shows state transitions.
state
Reset state initialized. Program execution state
Active (high speed) mode executes successive program instructions high speed, synchronized system clock Active (medium speed) mode executes successive program instructions reduced speed, synchronized system clock Subactive mode executes successive program instructions reduced speed, synchronized subclock
Low-power modes
Program halt state state which some chip functions stopped conserve power
Sleep mode
Standby mode
Watch mode
Subsleep mode
Exceptionhandling state transient state entered when changes processing flow reset interrupt exception handling source. Note: section Power-Down Modes, details modes their transitions.
Figure 2.14 Operation States
Reset cleared Reset state Reset occurs Exception-handling state
Reset occurs
Reset occurs
Interrupt source
Interrupt source
Exceptionhandling complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.15 State Transitions 2.7.2 Program Execution State
program execution state executes program instructions sequence. There three modes this state, active modes (high speed medium speed) subactive mode. Operation synchronized with system clock active mode (high speed medium speed), with subclock subactive mode. section Power-Down Modes details these modes. 2.7.3 Program Halt State
program halt state there four modes: sleep mode, standby mode, watch mode, subsleep mode. section Power-Down Modes details these modes. 2.7.4 Exception-Handling State
exception-handling state transient state occurring when exception handling started reset interrupt changes normal processing flow. exception handling caused interrupt, (R7) referenced values saved stack. details interrupt handling, section Interrupts.
2.8.1
Memory
Memory
memory maps H8/3857 Series H8/3854 Series shown figures 2.16 (b).
H8/3855 H8/3856 H8/3857 H8/3857F H'0000 H'0029 H'002A Interrupt vector bytes)
On-chip
kbytes
kbytes
kbytes
kbytes
H'9FFF
H'BFFF
H'EDFF used H'F77F H'F780
On-chip
2,048 bytes
H'FF7F H'FF80 Internal registers (128 bytes) H'FFFF
Figure 2.16 H8/3857 Series Memory
H8/3852 H'0000 H'0029 H'002A Interrupt vector bytes) kbytes On-chip H'3FFF
H8/3853
H8/3854*1 H8/3854F*1
kbytes
kbytes
kbytes
H'5FFF
H'7FFF
H'EDFF used H'F77F H'F780 On-chip H'FB7F H'FB80 H8/3852 H8/3853 H8/3854 1,024 bytes*2 H8/3854F 2,048 bytes*2
H'FF7F H'FF80 Internal registers (128 bytes) H'FFFF Notes: Note that H8/3854 (mask version) H8/3854F (F-ZTAT version) have different sizes. start address 2-kbyte H'F780, start address 1-kbyte H'FB80.
Figure 2.16 H8/3854 Series Memory
2.9.1
Application Notes
Notes Data Access
Access Empty Areas: address space H8/300L includes empty areas addition RAM, registers, areas available user. these empty areas mistakenly accessed application program, following results will occur. Data transfer from empty area transferred data will lost. This action also cause misoperate. Data transfer from empty area Unpredictable data transferred. Access Internal Registers: Internal data transfer from on-chip modules other than areas makes 8-bit data width. word access attempted these areas, following results will occur. Word access from register area Upper byte: Will written register. Lower byte: Transferred data will lost. Word access from register Upper byte: Will written upper part register. Lower byte: Unpredictable data will written lower part register. Byte size instructions should therefore used when transferring data from registers other than on-chip areas. Figure 2.17 shows data size number states which on-chip peripheral modules accessed.
Access States Word H'0000 H'0029 H'002A kbytes*1 On-chip Interrupt vector area bytes) Byte
H'EDFF
used
H'F780 On-chip H'FF7F H'FF80 Internal registers (128 bytes) H'FFA8 H'FFAD H'FFFF 2048 bytes*2
Notes: above example description H8/3857, H8/3857F, H8/3854F. H8/3855 kbytes on-chip ROM, ending address H'9FFF, H8/3856 kbytes, ending address H'BFFF, H8/3852 kbytes, ending address H'3FFF, H8/3853 kbytes, ending address H'5FFF, H8/3854 (mask version) kbytes, ending address H'7FFF. H8/3857 Series H8/3854F have 2,048 bytes on-chip RAM, H8/3854 Series (mask version) 1,024 bytes, starting address H'FB80.
Figure 2.17 Data Size Number States Access from On-Chip Peripheral Modules
2.9.2
Notes Manipulation
BSET, BCLR, BNOT, BST, BIST instructions read byte data, modify data, then write data byte again. Special care required when using these instructions cases where registers assigned same address, case registers that include writeonly bits, when instruction accesses I/O.
Order Operation Read Modify Write Operation Read byte data designated address Modify designated read data Write altered byte data designated address
Manipulation Registers Assigned Same Address Example Timer load register timer count manipulation Figure 2.18 shows example which timer registers share same address. When manipulation instruction accesses timer load register timer counter reloadable timer, since these registers share same address, following operations take place.
Order Operation Read Modify Write Operation Timer counter data read (one byte) modifies (sets resets) designated instruction altered byte data written timer load register
timer counter counting, value read necessarily same value timer load register. result, bits other than intended timer load register modified timer counter value.
Count clock Timer counter Reload Timer load register Read Write
Internal
Figure 2.18 Timer Configuration Example
Example When BSET instruction executed port designated input pins, with low-level signal input high-level signal remaining pins, P30, output pins output low-level signals. this example, BSET instruction used change high-level output. Prior executing BSET]
Input/output state PCR3 PDR3 Input level Input High level Output level Output level Output level Output level Output level Output level
BSET instruction executed] BSET @PDR3 BSET instruction executed designating port
After executing BSET]
Input/output state PCR3 PDR3 Input level Input High level Output level Output level Output level Output level Output level Output High level
Explanation BSET operates] When BSET instruction executed, first reads port Since input pins, reads states (low-level high-level input). output pins, reads value PDR3. this example PDR3 value H'80, value read H'40. Next, sets read data changing PDR3 data H'41. Finally, writes this value (H'41) PDR3, completing execution BSET.
result this operation, PDR3 becomes outputs high-level signal. However, bits PDR3 with different values. avoid this problem, store copy PDR3 data work area memory. Perform manipulation data work area, then write this data PDR3. Prior executing BSET] MOV. MOV. MOV. #80, R0L, R0L,
Input/output state PCR3 PDR3 RAM0 Input level
@RAM0 @PDR3
Input High level
PDR3 value (H'80) written work area memory (RAM0) well PDR3.
Output level
Output level
Output level
Output level
Output level
Output level
BSET instruction executed] BSET @RAM0 BSET instruction executed designating PDR3 work area (RAM0).
After executing BSET] MOV. MOV. @RAM0, R0L, @PDR3
Input/output state PCR3 PDR3 RAM0 Input level Input High level
work area (RAM0) value written PDR3.
Output level
Output level
Output level
Output level
Output level
Output High level
Manipulation Register Containing Write-Only Example When BCLR instruction executed PCR3 port examples above, input pins, with low-level signal input high-level signal P36. remaining pins, P30, output pins that output low-level signals. this example, BCLR instruction used change input port. assumed that high-level signal will input this input pin. Prior executing BCLR]
Input/output state PCR3 PDR3 Input level Input High level Output level Output level Output level Output level Output level Output level
BCLR instruction executed] BCLR @PCR3 BCLR instruction executed designating PCR3.
After executing BCLR]
Input/output state PCR3 PDR3 Output level Output High level Output level Output level Output level Output level Output level Input High level
Explanation BCLR operates] When BCLR instruction executed, first reads PCR3. Since PCR3 write-only register, reads value H'FF, even though PCR3 value actually H'3F. Next, clears read data changing data H'FE. Finally, this value (H'FE) written PCR3 BCLR instruction execution ends.
result this operation, PCR3 becomes making input port. However, bits PCR3 change that change from input pins output pins. avoid this problem, store copy PCR3 data work area memory. Perform manipulation data work area, then write this data PCR3. Prior executing BCLR] MOV. MOV. MOV. #3F, R0L, R0L,
Input/output state PCR3 PDR3 RAM0 Input level
@RAM0 @PCR3
Input High level
PCR3 value (H'3F) written work area memory (RAM0) well PCR3.
Output level
Output level
Output level
Output level
Output level
Output level
BCLR instruction executed] BCLR @RAM0 BCLR instruction executed designating PCR3 work area (RAM0).
After executing BCLR] MOV. MOV. @RAM0, R0L, @PCR3
Input/output state PCR3 PDR3 RAM0 Input level Input High level
work area (RAM0) value written PCR3.
Output level
Output level
Output level
Output level
Output level
Output High level
Table 2.12 lists registers that share same address, table 2.13 lists registers that contain write-only bits.
Table 2.12 Registers with shared addresses
Register Name Timer counter timer load register Timer counter timer load register Port data register Port data register
Abbreviation TCB/TLB TCC/TLC PDR1 PDR2 PDR3 PDR4 PDR5 PDR9 PDRA
Address H'FFB3 H'FFB5 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFDC H'FFDD
Port data register Port data register Port data register Port data register
Port data register
Notes: These port registers used also input. function H8/3857 Series only; provided H8/3854 Series. Some bits present H8/3854 Series.
Table 2.13 Registers with write-only bits
Register Name Port control register Port control register Port control register Port control register Port control register Port control register Port control register Timer control register control register* data register data register
Abbreviation PCR1 PCR2 PCR3 PCR4 PCR5 PCR9 PCRA TCRF PWCR PWDRU PWDRL
Address H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFEC H'FFED H'FFB6 H'FFD0 H'FFD1 H'FFD2
Notes: Some bits present H8/3854 Series. function H8/3857 Series only; provided H8/3854 Series.
2.9.3
Notes EEPMOV Instruction
EEPMOV instruction block data transfer instruction. moves number bytes specified from address specified address specified
When setting make sure that final destination address R4L) does exceed H'FFFF. value must change from H'FFFF H'0000 during execution instruction.
H'FFFF allowed
Section Exception Handling
Overview
Exception handling performed H8/3857 Series when reset interrupt occurs. Table shows priorities these types exception handling. Table
Priority High
Exception Handling Types Priorities
Exception Source Reset Interrupt Time Start Exception Handling Exception handling starts soon reset state cleared When interrupt requested, exception handling starts after execution present instruction exception handling progress completed
3.2.1
Reset
Overview
reset highest-priority exception. internal state registers onchip peripheral modules initialized. 3.2.2 Reset Sequence
soon goes low, processing stopped H8/3857 enters reset state. make sure chip reset properly, observe following precautions. power Hold until clock pulse generator output stabilizes. Resetting during operation: Hold least system clock cycles. When goes high again after being held given period, reset exception handling begins. Reset exception handling takes place follows: internal state registers on-chip peripheral modules initialized, with condition code register (CCR) loaded from reset exception handling vector address (H'0000 H'0001), after which program starts executing from address indicated When system power turned off, should held low.
Figure shows reset sequence.
Reset cleared Program initial instruction prefetch Vector fetch Internal processing
Internal address Internal read signal Internal write signal Internal data (16-bit)
Reset exception handling vector address (H'0000) Program start address First instruction program
Figure Reset Sequence 3.2.3 Interrupt Immediately after Reset
After reset, interrupt were accepted before stack pointer (SP: initialized, would pushed onto stack correctly, resulting program runaway. prevent this, immediately after reset exception handling interrupts masked. this reason, initial program instruction always executed immediately after reset. This instruction should initialize stack pointer (e.g. MOV.W #xx: SP).
3.3.1
Interrupts
Overview
H8/3857 Series, sources that initiate interrupt exception handling include external interrupts (WKP7 WKP0, IRQ4 IRQ0), internal interrupts from on-chip peripheral modules. H8/3854 Series, sources that initiate interrupt exception handling include external interrupts (WKP7 WKP0, IRQ4, IRQ3, IRQ1, IRQ0), internal interrupts from on-chip peripheral modules. Table shows interrupt sources, their priorities, their vector addresses. When more than interrupt requested, interrupt with highest priority processed. interrupts have following features: Both internal external interrupts masked CCR. When this interrupt request flags interrupts accepted. external interrupt pins IRQ0 IRQ4 each independently either rising edge sensing falling edge sensing.
Table
Priority High
Interrupt Sources Priorities
Interrupt Source IRQ0 IRQ1 IRQ2* IRQ3 IRQ4 WKP6 SCI1*
Interrupt Reset IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 SCI1 transfer complete Timer overflow Timer overflow
Vector Number
Vector Address* H'0000 H'0001 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013
H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0024 H'0025
Timer Timer Timer Timer Timer SCI3
Timer overflow underflow Timer compare match Timer overflow Timer compare match Timer overflow SCI3 transmit SCI3 transmit data empty SCI3 receive data full SCI3 overrun error SCI3 framing error SCI3 parity error
converter (SLEEP instruction executed)
conversion Direct transfer
H'0026 H'0027 H'0028 H'0029
Notes: Vector addresses H'0002 H'0007 H'0020 H'0023 reserved cannot used. Applies H8/3857 Series. H8/3854 Series, these vector addresses reserved.
3.3.2
Interrupt Control Registers
Table lists registers that control interrupts. Table Interrupt Control Registers
Abbreviation
Register Name edge select register*
R/W* R/W* R/W*
Initial Value H'E0 H'00 H'00 H'20 H'00 H'00
Address H'FFF2 H'FFF3 H'FFF4 H'FFF6 H'FFF7 H'FFF9
IEGR IENR1 IENR2 IRR1 IRR2 IWPR
Interrupt enable register Interrupt enable register
Interrupt request register Interrupt request register
Wakeup interrupt request register
Notes: Write enabled only writing clear flag. There some differences functions between H8/3857 Series H8/3854 Series. details, individual register descriptions.
Edge Select Register (IEGR)
Initial value Read/Write IEG4 IEG3 IEG2* IEG1 IEG0
Note: Applies H8/3857 Series. H8/3854 Series, this must always cleared
IEGR 8-bit read/write register, used designate whether pins IRQ0 IRQ4 rising edge sensing falling edge sensing. Bits 5-Reserved Bits: Bits reserved; they always read cannot modified. 4-IRQ4 Edge Select (IEG4): selects input sensing IRQ4/ADTRG.
IEG4 Description Falling edge IRQ4/ADTRG input detected Rising edge IRQ4/ADTRG input detected (initial value)
3-IRQ3 Edge Select (IEG3): selects input sensing IRQ3/TMIF.
IEG3 Description Falling edge IRQ3/TMIF input detected Rising edge IRQ3/TMIF input detected (initial value)
2-IRQ2 Edge Select (IEG2): used H8/3857 Series select input sensing IRQ2/TMIC. H8/3854 Series, this must always cleared
IEG2 Description Falling edge IRQ2/TMIC input detected Rising edge IRQ2/TMIC input detected (initial value)
1-IRQ1 Edge Select (IEG1): selects input sensing IRQ1/TMIB.
IEG1 Description Falling edge IRQ1/TMIB input detected Rising edge IRQ1/TMIB input detected (initial value)
0-IRQ0 Edge Select (IEG0): selects input sensing IRQ0.
IEG0 Description Falling edge IRQ0 input detected Rising edge IRQ0 input detected (initial value)
Interrupt Enable Register (IENR1)
IENTA Initial value Read/Write IENS1* IENWP IEN4 IEN3 IEN2* IEN1 IEN0
Note: Applies H8/3857 Series. H8/3854 Series, this must always cleared
IENR1 8-bit read/write register that enables disables interrupt requests.
7-Timer Interrupt Enable (IENTA): enables disables timer overflow interrupt requests.
IENTA Description Disables timer interrupts Enables timer interrupts (initial value)
6-SCI1 Interrupt Enable (IENS1): used H8/3857 Series enable disable SCI1 transfer complete interrupt requests. H8/3854 Series, this must always cleared
IENS1 Description Disables SCI1 interrupts Enables SCI1 interrupts (initial value)
5-Wakeup Interrupt Enable (IENWP): enables disables WKP7 WKP0 interrupt requests.
IENWP Description Disables interrupt requests from Enables interrupt requests from (initial value)
Bits 0-IRQ IRQ3, IRQ1, Interrupt Enable (IEN4, IEN3, IEN1, IEN0): Bits enable disable IRQ4, IRQ3, IRQ1, IRQ0 interrupt requests.
IENn Description Disables interrupt request IRQn Enables interrupt request IRQn (initial value)
2-IRQ2 Interrupt Enable (IEN2): used H8/3857 Series enable disable IRQ2 interrupt requests. H8/3854 Series, this must always cleared
IEN2 Description Disables interrupt request IRQ2 Enables interrupt request IRQ2 (initial value)
Interrupt Enable Register (IENR2)
IENDT Initial value Read/Write IENAD IENTFH IENTB
IENTFL IENTC*
Note: Applies H8/3857 Series. H8/3854 Series, this must always cleared
IENR2 8-bit read/write register that enables disables interrupt requests. 7-Direct Transfer Interrupt Enable (IENDT): enables disables direct transfer interrupt requests.
IENDT Description Disables direct transfer interrupt requests Enables direct transfer interrupt requests (initial value)
6-A/D Converter Interrupt Enable (IENAD): enables disables converter interrupt requests.
IENAD Description Disables converter interrupt requests Enables converter interrupt requests (initial value)
Bits 4-Reserved Bits: Bits reserved; they should always cleared 3-Timer Interrupt Enable (IENTFH): enables disables timer compare match overflow interrupt requests.
IENTFH Description Disables timer interrupts Enables timer interrupts (initial value)
2-Timer Interrupt Enable (IENTFL): enables disables timer compare match overflow interrupt requests.
IENTFL Description Disables timer interrupts Enables timer interrupts (initial value)
1-Timer Interrupt Enable (IENTC): used H8/3857 Series enable disable timer overflow underflow interrupt requests. H8/3854 Series, this must always cleared
IENTC Description Disables timer interrupts Enables timer interrupts (initial value)
0-Timer Interrupt Enable (IENTB): enables disables timer overflow underflow interrupt requests.
IENTB Description Disables timer interrupts Enables timer interrupts (initial value)
SCI3 interrupt control covered 10.4.2, description serial control register (SCR3). Interrupt request register (IRR1)
IRRTA Initial value Read/Write R/W*
IRRS1* R/W*
IRRI4 R/W*
IRRI3 R/W*
IRRI2* R/W*
IRRI1 R/W*
IRRI0 R/W*1
Notes: Only write flag clearing possible. Applies H8/3857 Series. H8/3854 Series, this must always cleared
IRR1 8-bit read/write register, which corresponding when timer SCI1, IRQ0 interrupt requested. flags cleared automatically when interrupt accepted. necessary write clear each flag. 7-Timer Interrupt Request Flag (IRRTA)
IRRTA Description Clearing conditions: When IRRTA cleared writing (initial value)
Setting conditions: When timer counter value overflows (goes from H'FF H'00)
6-SCI1 Interrupt Request Flag (IRRS1): used H8/3857 Series. H8/3854 Series, this must always cleared
IRRS1 Description Clearing conditions: When IRRS1 cleared writing Setting conditions: When SCI1 transfer completed (initial value)
5-Reserved Bit: reserved; always read cannot modified. Bits 0-IRQ IRQ3, IRQ1, Interrupt Request Flags (IRRI4, IRRI3, IRRI1, IRRI0)
IRRIn Description Clearing conditions: When IRRIn cleared writing IRRIn (initial value)
Setting conditions: IRRIn when IRQn interrupt input, designated signal edge detected
2-IRQ2 Interrupt Request Flag (IRRI2): used H8/3857 Series. H8/3854 Series, this must always cleared
IRRI2 Description Clearing conditions: When IRRI2 cleared write IRRI2 (initial value)
Setting conditions: IRRI2 when IRQ2 interrupt input, designated signal edge detected
Interrupt Request Register (IRR2)
IRRDT Initial value Read/Write R/W*1 IRRAD R/W*1 IRRTFH R/W*1
IRRTB R/W*1
IRRTFL IRRTC* R/W*1 R/W*1
Notes: Only write flag clearing possible. Applies H8/3857 Series. H8/3854 Series, this must always cleared
IRR2 8-bit read/write register, which corresponding when direct transfer, converter, timer timer timer timer interrupt requested. flags cleared automatically when interrupt accepted. necessary write clear each flag. 7-Direct Transfer Interrupt Request Flag (IRRDT)
IRRDT Description Clearing conditions: When IRRDT cleared writing (initial value)
Setting conditions: When DTON direct transfer made immediately after SLEEP instruction executed
6-A/D Converter Interrupt Request Flag (IRRAD)
IRRAD Description Clearing conditions: When IRRAD cleared writing Setting conditions: When conversion completed ADSF reset (initial value)
Bits 4-Reserved Bits: Bits reserved; they should always cleared 3-Timer Interrupt Request Flag (IRRTFH)
IRRTFH Description Clearing conditions: When IRRTFH cleared writing (initial value)
Setting conditions: When counter matches output compare register 8-bit timer mode, when 16-bit counter (TCFL, TCFH) matches output compare register (OCRFL, OCRFH) 16-bit timer mode
2-Timer Interrupt Request Flag (IRRTFL)
IRRTFL Description Clearing conditions: When IRRTFL cleared writing (initial value)
Setting conditions: When counter matches output compare register 8-bit timer mode
1-Timer Interrupt Request Flag (IRRTC): used H8/3857 Series. H8/3854 Series, this must always cleared
IRRTC Description Clearing conditions: When IRRTC cleared writing (initial value)
Setting conditions: When timer counter value overflows (goes from H'FF H'00) underflows (goes from H'00 H'FF)
0-Timer Interrupt Request Flag (IRRTB)
IRRTB Description Clearing conditions: When IRRTB cleared writing (initial value)
Setting conditions: When timer counter value overflows (goes from H'FF H'00)
Wakeup Interrupt Request Register (IWPR)
IWPF7 Initial value Read/Write R/W* IWPF6 R/W* IWPF5 R/W* IWPF4 R/W* IWPF3 R/W* IWPF2 R/W* IWPF1 R/W* IWPF0 R/W*
Note: Only write flag clearing possible.
IWPR 8-bit read/write register, which corresponding when pins WKP0 wakeup input receives falling edge input. flags cleared automatically when interrupt accepted. necessary write clear each flag.
Bits 0-Wakeup Interrupt Request Flags (WKPF7 WKPF0)
IWPFn Description Clearing conditions: When IWPFn cleared writing IWPFn Setting conditions: IWPFn when wakeup interrupt input, falling edge input detected
3.3.3
External Interrupts
H8/3857 Series external interrupt sources, WKP0, IRQ4 IRQ0. H8/3854 Series external interrupt sources, WKP0, IRQ4, IRQ3, IRQ1, IRQ0. Interrupts WKP0 WKP7: Interrupts WKP7 requested falling edge inputs pins WKP0 WKP7. When these pins designated WKP0 WKP7 pins port mode register (PMR5) falling edge input detected, corresponding wakeup interrupt request register (IWPR) requesting interrupt. Wakeup interrupt requests disabled clearing IENWP IENR1 also possible mask interrupts setting When interrupt exception handling request received interrupts WKP0 WKP7, vector number interrupts WKP0 WKP7 Since eight interrupts assigned same vector number, interrupt source must determined exception handling routine. Interrupts IRQ0 IRQ4: Interrupts IRQ0 IRQ4 requested into pins inputs IRQ0 IRQ4. These interrupts detected either rising edge sensing falling edge sensing, depending settings bits IEG0 IEG4 edge select register (IEGR). IRQ2 interrupt function H8/3857 Series only, provided H8/3854 Series. When these pins designated pins IRQ0 IRQ4 port mode registers (PMR1 PMR2) designated edge input, corresponding IRR1 requesting interrupt. Interrupts IRQ0 IRQ4 disabled clearing bits IEN0 IEN4 IENR1 interrupts masked setting When IRQ4 interrupt exception handling initiated, Vector numbers assigned interrupts IRQ0 IRQ4. order priority from IRQ0 (high) IRQ4 (low). Table gives details. H8/3854 Series, exception handling vector number reserved. 3.3.4 Internal Interrupts
There internal interrupts that requested on-chip peripheral modules H8/3857 Series, H8/3854 Series. When peripheral module requests interrupt, corresponding IRR1 IRR2 Individual interrupt requests disabled clearing corresponding IENR1 IENR2 interrupts masked setting When internal interrupt request accepted, Vector numbers assigned these interrupts. Table shows order priority interrupts from on-chip peripheral modules. H8/3854 Series, exception handling vector numbers reserved.
3.3.5
Interrupt Operations
Interrupts controlled interrupt controller. Figure shows block diagram interrupt controller. Figure shows flow interrupt acceptance. Interrupt operation described follows. When interrupt condition while interrupt enable register interrupt request signal sent interrupt controller. When interrupt controller receives interrupt request, sets interrupt request flag. From among interrupts with interrupt request flags interrupt controller selects interrupt request with highest priority holds others pending. (Refer table list interrupt priorities.) interrupt controller checks CCR. selected interrupt request accepted; interrupt request held pending. interrupt accepted, after processing current instruction completed, both pushed onto stack. state stack this time shown figure 3.4. value pushed onto stack address first instruction executed upon return from interrupt handling. masking further interrupts. vector address corresponding accepted interrupt generated, interrupt handling routine located address indicated contents vector address executed. Notes: When disabling interrupts clearing bits interrupt enable register, when clearing bits interrupt request register, always while interrupts masked above clear operations performed while result conflict arises between clear instruction interrupt request, exception processing interrupt will executed after clear instruction been executed.
Interrupt controller
External internal interrupts
Priority decision logic
Interrupt request
External interrupts internal interrupt enable signals
(CPU)
Figure Block Diagram Interrupt Controller
Program execution state
IRRI0 IEN0
IRRI1 IEN1
IRRI2 IEN2
IRRDT IENDT
contents saved contents saved Branch interrupt handling routine Notation: Program counter CCR: Condition code register
Note: IRQ2, SCI1, timer interrupts functions H8/3857 Series only, provided H8/3854 Series.
Figure Flow Interrupt Acceptance
(R7) Stack area
(R7)
CCR* Even address
Prior start interrupt exception handling
saved stack
After completion interrupt exception handling
Notation: PCH: Upper bits program counter (PC) PCL: Lower bits program counter (PC) CCR: Condition code register Stack pointer Notes: shows address first instruction executed upon return from interrupt handling routine. Register contents must always saved restored word access, starting from even-numbered address. Ignored return from interrupt.
Figure Stack State after Completion Interrupt Exception Handling Figure shows typical interrupt sequence where program area on-chip stack area on-chip RAM.
Interrupt accepted Instruction prefetch Internal processing Stack access Vector fetch Prefetch instruction Internal interrupt-handling routine processing (10)
Interrupt level decision wait instruction
Interrupt request signal
Internal address
Internal read signal
Internal write signal
Figure Interrupt Sequence
Internal data bits)
Instruction prefetch address (Instruction executed. Address saved contents, becoming return address.) (2)(4) Instruction code (not executed) Instruction prefetch address (Instruction executed.) Vector address Starting address interrupt-handling routine (contents vector address) (10) First instruction interrupt-handling routine
3.3.6
Interrupt Response Time
Table shows number wait states after interrupt request flag until first instruction interrupt handler executed. Table
Item Waiting time completion executing instruction* Saving stack Vector fetch Instruction fetch Internal processing Total Note: including EEPMOV instruction.
Interrupt Wait States
States
3.4.1
Application Notes
Notes Stack Area
When word data accessed H8/3857 Series, least significant address regarded Access stack always takes place word size, stack pointer (SP: should never indicate address. PUSH (MOV.W @-SP) (MOV.W @SP+, save restore register values. Setting address cause program crash. example shown figure 3.6.
H'FEFC H'FEFD H'FEFF
instruction H'FEFF
MOV. R1L, @-R7 Contents lost
Stack accessed beyond
Notation: PCH: Upper byte program counter PCL: Lower byte program counter R1L: General register Stack pointer
Figure Operation when Address When contents saved stack during interrupt exception handling restored when executed, this also takes place word size. Both upper lower bytes word data saved stack; return, even address contents restored while address contents ignored. 3.4.2 Notes Rewriting Port Mode Registers
When port mode register rewritten switch functions external interrupt pins, following points should observed. When external interrupt function switched rewriting port mode register that controls these pins (IRQ4, IRQ3, IRQ2*, IRQ1, IRQ0, WKP7 WKP0), interrupt request flag time function switched, even valid interrupt input pin. sure clear interrupt request flag after switching functions. Table shows conditions under which interrupt request flags this way. Note: Applies H8/3857 Series; provided H8/3854 Series.
Table
Conditions under which Interrupt Request Flag
Conditions IRRI3 IRRI2* IRRI1 IRRI0 When PMR2 IRQ4 changed from while IRQ4 IEGR IEG4 When PMR2 IRQ4 changed from while IRQ4 IEGR IEG4 When PMR1 IRQ3 changed from while IRQ3 IEGR IEG3 When PMR1 IRQ3 changed from while IRQ3 IEGR IEG3 When PMR1 IRQ2 changed from while IRQ2 IEGR IEG2 When PMR1 IRQ2 changed from while IRQ2 IEGR IEG2 When PMR1 IRQ1 changed from while IRQ1 IEGR IEG1 When PMR1 IRQ1 changed from while IRQ1 IEGR IEG1 When PMR2 IRQ0 changed from while IRQ0 IEGR IEG0 When PMR2 IRQ0 changed from while IRQ0 IEGR IEG0
Interrupt Request Flags IRR1 IRRI4
IWPR
IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
When PMR5 WKP7 changed from while When PMR5 WKP6 changed from while When PMR5 WKP5 changed from while When PMR5 WKP4 changed from while When PMR5 WKP3 changed from while When PMR5 WKP2 changed from while When PMR5 WKP1 changed from while When PMR5 WKP0 changed from while
Note: Applies H8/3857 Series. H8/3854 Series, this flag must always cleared
Figure shows procedure setting port mode register clearing interrupt request flag. When switching function, mask interrupt before setting port mode register. After accessing port mode register, execute least instruction (e.g., NOP), then clear interrupt request flag from instruction clear flag executed immediately after port mode register access without executing intervening instruction, flag will cleared. alternative method avoid setting interrupt request flags when functions switched keeping pins high level that conditions table occur.
Interrupts masked. (Another possibility disable relevant interrupt interrupt enable register
port mode register Execute instruction Clear interrupt request flag After setting port mode register bit, first execute least instruction (e.g., NOP), then clear interrupt request flag
Interrupt mask cleared
Figure Port Mode Register Setting Interrupt Request Flag Clearing Procedure
Section Clock Pulse Generators
Overview
Clock oscillator circuitry (CPG: clock pulse generator) provided on-chip, including both system clock pulse generator subclock pulse generator. system clock pulse generator consists system clock oscillator system clock dividers. subclock pulse generator consists subclock oscillator circuit subclock divider. 4.1.1 Block Diagram
Figure shows block diagram clock pulse generators.
System clock oscillator
(fOSC
System clock divider (1/2) System clock divider (1/8)
System clock pulse generator
Prescaler bits)
/8192
Subclock oscillator
Subclock divider (1/2, 1/4, 1/8)
Subclock pulse generator
Prescaler bits)
/128
Figure Block Diagram Clock Pulse Generators 4.1.2 System Clock Subclock
basic clock signals that drive on-chip peripheral modules SUB. Four clock signals have names: system clock, subclock, oscillator clock, watch clock. clock signals available peripheral modules /16, /32, /64, /128, /256, /512, /1024, /2048, /4096, /8192, W/2, W/4, W/8, W/16, W/32, W/64, W/128. clock requirements differ from module another.
System Clock Generator
Clock pulse supplied system clock divider either connecting crystal ceramic oscillator, providing external clock input. Connecting Crystal Oscillator: Figure shows typical method connecting crystal oscillator.
±20% ±20%
Figure Typical Connection Crystal Oscillator Figure shows equivalent circuit crystal oscillator. oscillator having characteristics given table should used.
Figure Equivalent Circuit Crystal Oscillator Table Crystal Oscillator Parameters
Frequency (MHz) (max) (max)
Connecting Ceramic Oscillator: Figure shows typical method connecting ceramic oscillator.
±20% ±10% ±10% Ceramic oscillator: Murata
Figure Typical Connection Ceramic Oscillator Notes Board Design: When generating clock pulses connecting crystal ceramic oscillator, careful attention following points. Avoid running signal lines close oscillator circuit, since oscillator adversely affected induction currents. (See figure 4.5.) board should designed that oscillator load capacitors located close possible pins OSC1 OSC2.
avoided
Signal Signal
Figure Board Design Oscillator Circuit
Inputting External Clock: When inputting external clock, connect OSC1 resistance leave OSC2 open. example connection this case shown figure 4.6.
OSC1 External clock input
OSC2
Open ±30%
Figure Example Connection when Inputting External Clock
Frequency Duty clock osc)
Subclock Generator
Connecting 32.768-kHz Crystal Oscillator: Clock pulses supplied subclock divider connecting 32.768-kHz crystal oscillator, shown figure 4.7. Following same connection precautions mentioned section 4.2.3, Notes Board Design.
(typ.)
Figure Typical Connection 32.768-kHz Crystal Oscillator
Figure shows equivalent circuit 32.768-kHz crystal oscillator.
32.768 Crystal oscillator: MX38T (Nihon Denpa Kogyo)
Figure Equivalent Circuit 32.768-kHz Crystal Oscillator Inputting External Clock Circuit configuration external clock input pin. should left open. example connection this case shown figure 4.9.
External clock input
Open
Figure Example Connection when Inputting External Clock External clock Input square waveform pin. When using CPU, timer timer LCD, with subclock clock selected, stop clock supply pin. Note: This function H8/3857 Series only, provided H8/3854 Series.
Figure 4.10 External Subclock Timing characteristics timing external clock input shown table 4.2. Table Characteristics Timing
AVCC AVSS -20°C 75°C*, unless otherwise specified, including subactive mode)
Applicable Symbol 32.768kHz Test Conditions Values Unit Notes Figure 4.10
Item Input high voltage Input voltage External subclock rise time External subclock fall time
-0.3 -0.3 12.0 12.0 38.4kHz 10.0 10.0 32.768 38.4
+0.3
Figure 4.10
External subclock oscillation frequency External subclock high width External subclock width
Figure 4.10
External subclock oscillation frequency External subclock high width External subclock width
Figure 4.10
Note: guaranteed temperature electrical characteristic shipped products 75°C.
Prescalers
H8/3857 Series H8/3854 Series equipped with on-chip prescalers having different input clocks (prescaler prescaler Prescaler 13-bit counter using system clock input clock. prescaled outputs provide internal clock signals on-chip peripheral modules. Prescaler 5-bit counter using 32.768-kHz signal divided (W/4) input clock. prescaled outputs used timer time base timekeeping. Prescaler (PSS): Prescaler 13-bit counter using system clock input clock. incremented once clock period. Prescaler initialized H'0000 reset, starts counting exit from reset state. standby mode, watch mode, subactive mode, subsleep mode, system clock pulse generator stops. Prescaler also stops initialized H'0000. cannot read write prescaler output from prescaler shared timer timer timer timer SCI1*, SCI3, converter, controller, 14-bit PWM*. divider ratio separately each on-chip peripheral function. active (medium-speed) mode clock input prescaler OSC/16. Note: This function H8/3857 Series only, provided H8/3854 Series. Prescaler (PSW): Prescaler 5-bit counter using 32.768 signal divided (W/4) input clock. Prescaler initialized H'00 reset, starts counting exit from reset state. Even standby mode, watch mode, subactive mode, subsleep mode, prescaler continues functioning long clock signals supplied pins Prescaler reset setting bits TMA3 TMA2 timer mode register (TMA). Output from prescaler used drive timer which case timer functions time base timekeeping.
Note Oscillators
Oscillator characteristics both masked F-ZTAT versions closely related board design should carefully evaluated user, referring examples shown this section. Oscillator circuit constants will differ depending oscillator element, stray capacitance interconne

Cautions Keep safety first your circuit designs! Renesas Technolo

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