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LH77790B

Embedded Microcontroller

LH77790B
Embedded Microcontroller
Thermal & Electrical Specification
Version 1.0
SHARP reserves the right to make changes in specifications described herein at any time and without notice in order to improve design or reliability. SHARP does not assume any responsibility for the use of any circuitry described no circuit patent licenses are implied. SHARP assumes no responsibility for damage caused by misuse or improper use of devices.
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions, safety equipment (or similar applications where component failure would result in loss of life or physical harm), aerospace equipment, telecommunication equipment (trunk lines) or nuclear power control equipment. Contact a SHARP representative or sales office before using SHARP devices for any applications other than those recommended by SHARP.
LIMITED WARRANTY
Reference No. SMA99104
Thermal & Electrical Specification
Overview
Thermal & Electrical Specification
LH77790B
Features
Thermal & Electrical Specification
LH77790B · Flexible Memory Interface - Six Multiplexeled Chip Enables / CAS pins - Two RAS pins - Fully Programmable - Six SRAM Banks (64MB each) - Two DRAM Banks (128MB each) - Access Privileges (System / User) · On-Chip DRAM Controller - Fast Page Mode - Normal Mode - CAS before RAS Refresh · Programmable Peripheral Interface (PPI) - 24 Programmable I / O Signals - Three Modes of Operation · Three 16-Bit Counter / Timer Channels - Six Modes of Operation - Binary or BCD Counting · Hardware Watchdog Timer - Eight Time-out Intervals - Protection Mechanism - Three Time-out Actions · Little Endian · JTAG Interface · Dual Supply Voltage - 5 V TTL - 25 MHz - 3.3 V LVTTL - 16.7 MHz
Development Environment
The 790B Evaluation Board (part number LU7790AH2A) and the ARM Software Development ToolKit (part number LU7V211H1) give users full access to the power and features of the 790B and provide a complete integrated environment for development. Users will be able to develop, benchmark, and profile both hardware and software easily and quickly.
Thermal & Electrical Specification
LH77790B
Block Diagram
CLOCK(S) JTAG INTERRUPTS RESET LCD DISPLAY
CLOCK / POWER MANAGEMENT
ARM7DI TAP CONTROLLER
INT / RESET CONTROLLER
LCD CONTROLLER
ARM7DI CPU AND CACHE 32-BIT INTERNAL BUS
2K BYTES SCRATCH PAD SRAM EXTERNAL MEMORY INTERFACE
BUS CONTROLLER
82C55 PROGRAMMABLE PERIPHERAL INTERFACE
16C450 UARTS
82C54 COUNTER / TIMERS
WATCH DOG TIMER
IrDA / DASK
3 CHANNELS
24 BITS
ARM-8
Figure 1. LH77790B Block Diagram
Thermal & Electrical Specification
LH77790B
Pin Description
Table 1. Pin Descriptions
CE5:0 / CAS5:0
RAS1:0
COUNTERS / TIMERS INTERFACE 123, 121, 117 124, 122, 118 CTGATE2:0 CTOUT2:0 I O
Thermal & Electrical Specification
LH77790B Table 1. Pin Descriptions
PROGRAMMABLE PERIPHERAL INTERFACE 139 - 135, 128 - 126 149 - 145, 142 - 140 159 - 155, 152 - 150 PA7:0 PB7:0 PC7:0
RESET AND EXTERNAL CLOCKS
RESETI
RESETO
XCLKDIS
UCLK CTCLK
Thermal & Electrical Specification
LH77790B Table 1. Pin Descriptions
TDI TDO
Ground. All ground pins must be used.
NO CONNECT
No connection.
NOTE: JTAG Reset, TRST, is internally connected to RESETI. IEEE 1149.1 - 1990 Standard requires JTAG Inputs to be pulled up to a good logic level to achieve normal operations.
Thermal & Electrical Specification
LH77790B Table 2. Pinout
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SIGNAL NC NC XCLK VSS A0 A1 A2 A3 VCC VSS A4 A5 A6 A7 A8 A9 A10 A11 VCC VSS A12 A13 A14 A15 A16 A17 A18 A19 VCC VSS A20 A21 A22 A23 A24 A25 D0 D1 VCC VSS D2 D3 NC NC PIN 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 SIGNAL NC NC D4 D5 D6 D7 D8 D9 VCC VSS D10 D11 D12 D13 D14 D15 RAS0 RAS1 VCC VSS CE0 / CAS0 CE1 / CAS1 CE2 / CAS2 CE3 / CAS3 CE4 / CAS4 CE5 / CAS5 WE OE BW WAIT VCC VSS VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VCC VSS NC NC PIN 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 SIGNAL NC NC CP2 CP1 MCLK S LCDCNTL PWM0 PWM1 PWM2 VCC VSS RESETI INT0 INT1 INT2 INT3 INT4 INT5 RxD0 VCC VSS TxD0 RxD1 TxD1 RxD2 TxD2 UCLK CTGATE0 CTOUT0 RESETO VSS CTGATE1 CTOUT1 CTGATE2 CTOUT2 CTCLK PA0 PA1 PA2 VCC VSS NC NC PIN 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 SIGNAL NC NC PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 / RI1 VCC VSS PB3 / CTS1 PB4 / CTS0 PB5 / RI0 PB6 / DCD0 PB7 / DSR0 PC0 / RTS1 PC1 / RTS0 PC2 / DTR0 VCC VSS PC3 PC4 PC5 PC6 PC7 TCK TMS XCLKDIS VCC VSS TDI TDO TEST0 TEST1 BB ADBE TEST2 TEST3 VCC VSS NC NC
Thermal & Electrical Specification
LH77790B
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings
PARAMETER Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation (Package Limit) SYMBOL VCC VIN VOUT TSTG PDPKG RATING -0.3 to 6.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -40 to +125 1 UNIT V V V °C W
NOTE: These are stress ratings for transient conditions only. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device.
Recommended Operating Conditions
Table 4. LH77790B (5 V Operation) Recommended Operating Conditions
PARAMETER Supply Voltage Supply Voltage Clock Frequency Operating Temperature SYMBOL VCC VSS FXCLK TOPR MIN. 4.5 0 0 0 TYP. 5.0 0 - - MAX. 5.5 0 25 70 UNIT V V MHz °C
NOTE: Unused input pins should be pulled LOW or HIGH to their inactive state.
Table 5. LH77790B (3.3 V Operation) Recommended Operating Conditions
PARAMETER Supply Voltage Supply Voltage Clock Frequency Operating Temperature SYMBOL VCC VSS FXCLK TOPR MIN. 3.0 0 0 0 TYP. 3.3 0 - - MAX. 3.6 0 16.7 70 UNIT V V MHz °C
NOTE: Unused input pins should be pulled LOW or HIGH to their inactive state.
Thermal & Electrical Specification
LH77790B
DC Specifications
Over recommended operating voltage and temperature conditions, unless otherwise specified. Table 6. LH77790B DC Specifications
Thermal & Electrical Specification
LH77790B
AC Test Conditions
Table 7. AC Test Conditions1
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load NOTE: 1. Applies to LH77790B (3.3 V and 5.0 V ranges). 2. Includes scope and jig capacitance. RATING VSS to VCC 5 1.5 50 UNIT V ns V pF 2 NOTE
Pin Capacitance
Table 8. Pin Capacitance1
PARAMETER Input Capacitance Output Capacitance I / O Capacitance SYMBOL CIN COUT CIO MAX. 10 20 20 UNIT pF pF pF NOTE 2 2 2
NOTE: 1. Applies to LH77790B (3.3 V and 5.0 V ranges). 2. Measurement Condition: All pins are set to 0 V except measured pin.
AC Specifications
Over Recommended operating voltage, temperature and AC test conditions.
External Clocks
tXCLK tXCLKL tXCLKH
ARM2-99
Figure 2. System Clock AC Timing
Thermal & Electrical Specification
LH77790B
tCTCLK tCTCLKH tCTCLKL
ARM2-100
Figure 3. External Counters / Timers Clocks AC Timing
tUCLK tUCLKH tUCLKL
ARM2-101
Figure 4. External UARTs / DASK Clock AC Timing Table 9. External Clocks AC Specifications
PARAMETER tXCLK tXCLKH tXCLKL tCTCLK tCTCLKH tCTCLKL tUCLK tUCLKH tUCLKL DESCRIPTION XCLK (System Clock) Period XCLK HIGH Time XCLK LOW Time CTCLK (Counters / Timers External Clock) Period CTCLK HIGH Time CTCLK LOW Time UCLK (UARTs / DASK External Clock) Period UCLK HIGH Time UCLK LOW Time 3.3 V RANGE MIN. 60 1 / 2 1 / 2 2 1 1 2 1 1 MAX. - - - - - - - - - 5.0 V RANGE MIN. 40 1 / 2 1 / 2 2 1 1 2 1 1 MAX. - - - - - - - - - UNIT ns tXCLK tXCLK tXCLK tXCLK tXCLK tXCLK tXCLK tXCLK
Thermal & Electrical Specification
CYCLE 1 CYCLE 2 CYCLE 3
Thermal & Electrical Specification
tXA tXAH
VALID VALID VALID
SRAM / DRAM Interface
D15 - D0 tXCE tDS
VALID tDH
VALID tXCEH
CE tXOE tXOEH
WE tXBW
tXBWH
Figure 5. SRAM Read Access AC Timing
tWTS1 tWTH1
LH77790B
ARM2-102
CYCLE 1 CYCLE 2 CYCLE 3
tXA tXAH
LH77790B
VALID
tACEH tDCEH
D15 - D0 VALID
VALID
tXDH tXCEH
tXWE tXWEH tDWEH
tAWEH tXBW
Figure 6. SRAM Write Access AC Timing
tWTS1 tWTH1
tXBWH
ARM2-103
Thermal & Electrical Specification
CYCLE 1 CYCLE 3 CYCLE 4
CYCLE 2
tXA tXAH
Thermal & Electrical Specification
A25 - A0 DRAM ROW COLUMN
tDS tDH
tXRAS
VALID
tXRASH
tASR tXCAS tXCASH
tASC tXOE tXOEH
Figure 7. DRAM Read Access AC Timing
tXBWH
tWTS1 tWTH1
LH77790B
ARM2-104
CYCLE 1 CYCLE 3 CYCLE 4 CYCLE 2
LH77790B
tXA tXAH
A25 - A0 DRAM
COLUMN
VALID VALID
tXRAS
tXRASH
tASR tXCAS tDSC tXCASH
tXWE tASC tXWEH
Figure 8. DRAM Write Access Timing
tXBWH
tWTS1 tWTH1
Thermal & Electrical Specification
ARM2-105
LH77790B Table 10. SRAM / DRAM AC Specifications
PARAMETER tXA tXAH tXCE tXCEH tXWE (SRAM) tXWE (DRAM) tXWEH tWTS tWTH tXD tXDH tXOE tXOEH tDS tDH tXBW tXBWH tAWEH tDWEH tACEH tDCEH tXRAS tXRASH tXCAS tXCASH tASR tASC tDSC DESCRIPTION XCLK to Address Valid Address Hold relative to XCLK XCLK to CE Active CE Hold relative to XCLK XCLK to WE Active (SRAM) XCLK to WE Active (DRAM) WE Hold relative to XCLK WAIT Setup relative to XCLK WAIT Hold relative to XCLK XCLK to Write Data Valid Write Data Hold relative to XCLK XCLK to OE Active OE Hold relative to XCLK Read Data Setup relative to XCLK Read Data Hold relative to XCLK XCLK to BW Valid BW Hold relative to XCLK Address Hold relative to WE Inactive Data Hold relative to WE Inactive Address Hold relative to CE Inactive Data Hold relative to CE Inactive XCLK to RAS Valid RAS Hold relative to XCLK XCLK to CAS Valid CAS Hold relative to XCLK DRAM Row Address Setup relative to RAS DRAM Column Address Setup relative to CAS DRAM Write Data Setup relative to CAS 3.3 V RANGE MIN. - 4 - 4 - - 4 10 6 - 4 - 4 13 21 - 4 0 0 0 0 - 2 - 4 10 10 10 MAX. 41 - 41 - 35 40 - - - 44 - 31 - - - 35 - - - - - 26 - 32 - - - - 5.0 V RANGE MIN. - 4 - 4 - - 4 10 6 - 4 - 4 9 19 - 4 0 0 0 0 - 2 - 4 4 5 5 MAX. 33 - 27 - 30 35 - - -32 - 25 - - - 28 - - - - - 21 - 26 - - - - UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 1, 3, 4 1 NOTE
NOTES: 1. Measures hold time on data bus until data changes. The change could either be a state change or HIGH Impedance change. 2. This parameter is the setup time when both data and CAS become valid in the same cycle (Burst CAS cycles in Page Mode). 3. Minimum Data Hold Time with respect to CE, OE, and address invalid is 0 ns (SRAM). 4. Minimum Data Hold Time with respect to CAS and OE invalid is 0 ns (DRAM).
Thermal & Electrical Specification
LH77790B
Programmable Peripheral Interface, PPI
The PPI has three different modes of operation shown in Figure 9 through Figure 13. Modes 1 and 2 assign alias names to port C when used as control signals depending on the mode of operation. Table 11 shows a cross reference between the alias names which are used in the AC timing diagrams for modes 1 and 2 and the 790B external I / O names.
ARM2-108
INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL ADDRESS BUS
VALID DATA OUT FROM 790
PPI Port (A, B, or C)
Figure 9. Programmable Peripheral Interface (MODE 0, Output) AC Timing
Thermal & Electrical Specification
NOTE:
Thermal & Electrical Specification
tXA tXAH
INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL ADDRESS BUS
PORT INPUT SAMPLED
tP0IS
tP0IH
Figure 10. Programmable Peripheral Interface (MODE 0, Input) AC Timing
PPI PORT (A, B, or C)
VALID DATA IN FROM PERIPHERAL
NOTE:
LH77790B
ARM2-109
tXA tXAH
INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL BUS
LH77790B
790 READS CAPTURED DATA
tSTIB tXIBF
tSTIN tXINT1
tPIS tPIH
Figure 11. Programmable Peripheral Interface (Mode 1, Input) AC Timing
VALID DATA IN FROM PERIPHERAL
PPI PORT (A or B)
Thermal & Electrical Specification
ARM2-110
Thermal & Electrical Specification
INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL ADDRESS BUS
tXOBF
tACOB tACK
tXINT2
tXPO tACIN
Figure 12. Programmable Peripheral Interface (Mode 1, Output) AC Timing
VALID DATA OUT FROM 790B
PPI PORT (A or B)
LH77790B
ARM2-111
tXAH tXA
INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL ADDRESS BUS
LH77790B
A25 - A0 INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL ADDRESS BUS
tXOBF tACOB
tXNT2
tSTIN
tSTIB tXIBF
tPIS tPIH tACD tACDH
Figure 13. Programmable Peripheral Interface (Mode 2, Bi-directional) AC Timing
VALID DATA IN FROM PERIPHERAL VALID DATA OUT FROM 790B
PPI PORT (A ONLY)
Thermal & Electrical Specification
ARM2-112
LH77790B Table 11. PPI Cross Reference
ALIAS STB IBF INTR OBF ACK MODE 1 (INPUT) PORT A PC4 PC5 PC3 - - PORT B PC2 PC1 PC0 - - MODE 1 (OUTPUT) Port A - - PC3 PC7 PC6 Port B - - PC0 PC1 PC2 MODE 2 (BI-DIRECTIONAL) Port A PC4 PC5 PC3 PC7 PC6
Table 12. PPI AC Specification
PARAMETER tXPO tP0IS tSTIB tPIS tP0IH tPIH tSTIN tXINT1 tXIBF tSTB tXINT2 (Bit A) tXOBF tACK tACIN tACOB tACD tACDH DESCRIPTION XCLK to Data Out Valid Port Input Setup relative to XCLK (MODE 0) STB to IBF Port Input Setup relative to STB (MODES 1 & 2) Port Input Hold relative to XCLK (MODE 0) Port Input Hold relative to STB (MODES 1 & 2) STB to INTR XCLK to INTR (MODE 1 Input) XCLK to IBF STB Pulse Width XCLK to INTR (MODE 1 Output & MODE 2) XCLK to OBF ACK Pulse Width ACK to INTR ACK to OBF ACK to Data Out Valid Data Out Hold relative to ACK 3.3 V RANGE MIN. - 40 - 12 10 10 - - - 17 - - - 15 - - - 6 MAX. 54 - 34 - - - 32 78 52 - 86 57 57 - 34 44 39 - 5.0 V RANGE MIN. - 41 - 12 7 7 - - - 14 - - - 12 - - - 6 MAX. 41 - 27 - - - 25 57 40 - 56 44 44 - 27 28 27 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tXINT2 (Port B) XCLK to INTR (MODE 1 Output & MODE 2)
Thermal & Electrical Specification
LH77790B
External Reset
tRSTIW
RESETI
tRSTOV tRSTOH
RESETO
ARM2-120
Figure 14. LH77790B External Reset AC Timing Table 13. External Reset AC Specifications
PARAMETER tRSTIW tRSTOV tRSTOH DESCRIPTION RESETI Pulse Width (Once Sampled Low) RESETO Valid (Once RESETI Sampled Low) RESETO Hold (Once RESETI Sampled High) (3.3 V RANGE) MIN. 8.5 - - TYP. - 3.5 1 MAX. - - - (5.0 V RANGE) MIN. 8.5 - - TYP. - 3.5 1 MAX. - - - UNIT XCLK XCLK XCLK
Thermal & Electrical Specification
LH77790B
LCD Controller
The following equations (see above note) and parameters describe the relationship between LCD input Clock, S, CP1, CP2, and MCLK.
Thermal & Electrical Specification
LH77790B Table 15. Typical AC Timing for LCD Controller (3.3 V and 5.5 V Ranges)
Other timing parameters are shown in Table 16. Table 16. Other Typical LCD Timing Parameters (3.3 V and 5.5 V Ranges)
Thermal & Electrical Specification
LAST ROW
ROW 1 INVALID DATA DATA DATA DATA INVALID DATA DATA DATA
VD7:0 tDS tDH tPXFR
Thermal & Electrical Specification
CP2 tCP1W t12F tCP2 t21 t12 CP1 tSS tSH S MCLK VD7:0
INVALID DATA INVALID DATA INVALID DATA
LAST ROW
INVALID DATA
Figure 15. LCD Controller AC Timing
tCP1 CP1 S
NEW FRAME
tS t1M
LH77790B
ARM2-86
LH77790B
Package Specifications
NC NC VSS VCC TEST3 TEST2 ADBE BB TEST1 TEST0 TDO TDI VSS VCC XCLKDIS TMS TCK PC7 PC6 PC5 PC4 PC3 VSS VCC PC2 / DTR0 PC1 / RTS0 PC0 / RTS1 PB7 / DSR0 PB6 / DCD0 PB5 / RI0 PB4 / CTS0 PB3 / CTS1 VSS VCC PB2 / RI1 PB1 PB0 PA7
176-PIN TQFP
TOP VIEW
PA6 PA5 PA4 PA3 NC NC
NC NC XCLK VSS A0 A1 A2 A3 VCC VSS A4 A5 A6 A7 A8 A9 A10 A11 VCC VSS A12 A13 A14 A15 A16 A17 A18 A19 VCC VSS A20 A21 A22 A23 A24 A25 D0 D1 VCC VSS D2 D3 NC NC
LH77790B Embedded Microcontroller
NC NC VSS VCC PA2 PA1 PA0 CTCLK CTOUT2 CTGATE2 CTOUT1 CTGATE1 VSS RESETO CTOUT0 CTGATE0 UCLK TxD2 RxD2 TxD1 RxD1 TxD0 VSS VCC RxD0 INT5 INT4 INT3 INT2 INT1 INT0 RESETI VSS VCC PWM2 PWM1 PWM0 LCDCNTL S MCLK CP1 CP2 NC NC
NC NC D4 D5 D6 D7 D8 D9 VCC VSS D10 D11 D12 D13 D14 D15 RAS0 RAS1 VCC VSS CE0 / CAS0 CE1 / CAS1 CE2 / CAS2 CE3 / CAS3 CE4 / CAS4 CE5 / CAS5 WE OE BW WAIT VCC VSS VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VCC VSS NC NC
Figure 16. LH77790B 176-Pin TQFP (Thin Quad Flat Pack) Pin Assignment
Thermal & Electrical Specification
LH77790B
176TQFP (TQFP-176-P-2424)
26.30 25.70 24.20 23.80 0.10 1.00 REF. 1.00 REF.
0.175 0.075 1.70 MAX.
DETAIL
0.50 TYP.
0.20 0.00 DIMENSIONS IN MM
176TQFP
Figure 17. LH77790B Package Specification
Thermal & Electrical Specification
NORTH AMERICA
EUROPE
SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Facsimile: (360) 834-8903 http://www.sharpsma.com
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: (07436) 5-1321 Facsimile: (07436) 5-1532 http://www.sharp.co.jp