Mapper 7-Channel TXC-04201B DATA SHEET FEATURES Seven independent

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DS1MX7 Device
Mapper 7-Channel TXC-04201B DATA SHEET FEATURES
Seven independent 1.544 Mbit/s mappers Single byte-parallel Telecom 6.48 Slots) 19.44 Slots) Floating VT1.5 byte-synchronous mapping with signaling only with without slip buffer Asynchronous mapping SONET mapping (VT1.5) mapping (TU-11 AU-3 TU-11 TUG-3) AMI, B8ZS codec DS1s Serial control line interface transceivers framers Telecom loopbacks with integral PRBS generator analyzer VT1.5/TU-11 pointer tracking generation VT1.5/TU-11 overhead processing insertion one-second latched performance registers counters alarm detection generation Auxiliary port Z6/N2, Z7/K4 O-bit access Ring port USHR/P support Gapped clock option Internet Applications without need framer Intel Motorola-compatible microprocessor interface 3-bit support Boundary Scan capability (IEEE 1149.1) Single power supply 208-pin plastic quad flat package
Line Transceiver Common Control Interface
DESCRIPTION
DS1MX7 seven-channel byte-synchronous asynchronous mapper. Both SONET mappings provided Bellcore GR-253-CORE (VT1.5) ITU-T G.707 3-96 (TU-11). single add/drop Telecom provided that operate either 6.48 19.44 MHz, which compatible with other TranSwitch devices. VT1.5/TU-11 pointer tracking overhead extraction/processing with full error alarm control provided. VT1.5/TU-11 pointer calculation overhead assembly also provided. Alarm error mappings from drop SONET/SDH to/from provided. Jitter performance achieved with fully digital threshold modulator DPLL that meets GR-253-CORE MTIE requirements without external de-jitter buffers. line, AMI, B8ZS line codes supported with full alarm detection generation ANSI T1.231-1997 draft. Each channel independently programmable mixed service applications. Access status control bits provided Intel/Motorolacompatible microprocessor interface. Diagnostic, test, maintenance functions provided, including boundary scan, PRBS generator/analyzer loopbacks.
APPLICATIONS
SONET/SDH terminal add/drop multiplexers supporting both asynchronous byte-synchronous modes Unidirectional bidirectional ring applications SONET Remote Digital Terminal Equipment SONET Equipment requiring access DS0s SONET/SDH Test Equipment Internet Access Equipment
LINE SIDE
Dual Rail Data Clocks
Ring Port
SYSTEM SIDE
Line Transceiver Serial Interface
DS1MX7 Mapper 7-Channel TXC-04201B
Microprocessor Interface
Telecom Interface Drop
U.S. Patents 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218 U.S. and/or foreign patents issued pending Copyright 2001 TranSwitch Corporation TranSwitch registered trademarks TranSwitch Corporation
System Test Access Auxiliary Port Clocks Port Interface Boundary Scan
Document Number: TXC-04201B-MB September 2001
TranSwitch Corporation Enterprise Drive Shelton, Connecticut 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
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DS1MX7 TXC-04201B
DATA SHEET TABLE CONTENTS
Section
Page
List Figures Feature List. Features that Independently Selectable each Mappers. Features that only Selectable Seven Mappers Group. Block Diagram Block Diagram Description Diagram Descriptions. Absolute Maximum Ratings Environmental Limitations. Thermal Characteristics. Power Requirements Input, Output Input/Output Parameters. Timing Characteristics Operation General Mapper Application Overview Line Interface Selection Asynchronous Operation with Line Interface. Byte-synchronous Operation with Line Interface. Receive Data Signaling Highway Operation Transmit Data Signaling Highway Operation Synchronizer, Mapper Overhead Generator Pointer Generation Telecom Slot Selection VT/TU Pointer Tracking Telecom Slot Selection. Demapper Desynchronization Pointer Leak Rate Calculations Jitter Measurements Microprocessor Interface Common Control/Status I/O. Serial Port Control Interface DS1MX7 Channel Testing using PRBS Generator Analyzer Telecom Interface. Multiplex Format Mapping Information Auxiliary Port Ring Port. Test Access Port Boundary Scan Support Device Reset Procedure. Memory Map. Memory Descriptions Common Memory Channel Control Registers. Channel Status Registers Application Diagrams. Package Information. Ordering Information. Related Products Standards Documentation Sources List Data Sheet Changes. Documentation Update Registration Form* Please note that TranSwitch provides documentation products. Current editions many documents available from Products page TranSwitch site www.transwitch.com. Customers using TranSwitch Product, planning should register with TranSwitch Marketing Department receive relevant updated supplemental documentation issued. They should also contact Applications Engineering Department ensure that they provided with latest available information about product, especially before undertaking development designs incorporating product.
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DATA SHEET LIST FIGURES
Figure
DS1MX7 TXC-04201B
Page
DS1MX7 TXC-04201B Block Diagram. VT1.5/ TU-11 Asynchronous Byte-synchronous Mappings. DS1MX7 TXC-04201B Diagram Tributary Input Timing Tributary Output Timing. Signaling Highway Structure Serial Control Port Structure Timing Telecom Input Timing 6.48 Operation Telecom Input Timing 19.44 Operation Telecom Output Timing 6.48 Operation Telecom Output Timing 19.44 Operation Auxiliary Port Timing Ring Port Timing. Datacom Mode Output Timing Datacom Mode Input Timing Intel Microprocessor Read Cycle Timing. Motorola Microprocessor Read Cycle Timing Intel Microprocessor Write Cycle Timing Motorola Microprocessor Write Cycle Timing. Boundary Scan Timing Line Interface Dual Unipolar Mode. Line Interface Mode Byte-synchronous Interface Framer System Interface Receive Framing Format. System Interface Receive Signaling Format System Interface Transmit Framing Format. System Interface Transmit Signaling Format VT/TU Pointer Tracking State Machine. Pointer Leak Rate Algorithm Jitter Tolerance Test Setup Jitter Tolerance Measurements. Jitter Transfer Test Setup. Jitter Transfer Measurements Jitter Generation Test Setup Standard Pointer Test Sequences Shadow Register Operation Serial Interface Operation Loopbacks Built-in PRBS Testing DS1MX7 Telecom Structure; SONET VC-3 SDH; Telecom 6.48 Telecom Structure; TUG-3 SDH; Telecom 19.44 STS-1 Mapping STS-3/AU-3 Mapping STM-1/VC-4 Mapping. Auxiliary Port Operation Auxiliary Port Address Designation Ring Port Operation. Boundary Scan Schematic DS1MX7 TXC-04201B Applications. Some DS1MX7 TXC-04201B Byte-synchronous Applications. DS1MX7 TXC-04201B 208-Pin Plastic Quad Flat Package
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DS1MX7 TXC-04201B FEATURE LIST
DATA SHEET
DS1MX7 device highly-featured seven-channel (T1) mapper wide variety interface, transmission switching applications. Seven independent asynchronous byte-synchronous mappers provided single monolithic VLSI device using sub-micron CMOS technology. Powered from single +5.0 volt supply, device dissipates less than watt typically. DS1MX7 provided 208-pin plastic quad flat package. ambient operating temperature range extends from with ft/min airflow. DS1MX7 device been designed meet latest industry standards, namely: ANSI T1.102- 1993 ANSI T1.105- 1991 ANSI T1.107- 1995 ANSI T1.231 (1993 1997 draft) ANSI T1.403-1995 AT&T Pub. 62411 (December 1990) Bellcore GR-253-CORE (Issue Bellcore TR-NWT-000496 (Issue Bellcore GR-499-CORE (Issue IEEE 1149.1- 1990, -1994 ITU-T G.707 3-96 ITU-T G.783 FEATURES THAT INDEPENDENTLY SELECTABLE EACH MAPPERS Line Interface Options Meets ANSI Bellcore input jitter requirements Rail (for asynchronous mapping only) B8ZS ANSI compliant detector ANSI compliant detector 12-Bit counters with excessive zeros option option (for asynchronous byte-synchronous mapping) Clock polarity selection clock in/out data inversion clock edge options (separate transmit receive control) asynchronous use, negative rail used count externally detected code violations Programmable clock edges transmit receive data External channel status (may programmed combine with internal support external detector) Clock slave asynchronous input; clock multiframe synchronization ms), master slave, byte-synchronous input Separate signaling highway byte-synchronous, carries ABCD signaling bits Yellow alarm information DS1MX7 External pin-controlled shut down line drive pins card protection Gapped clock option place signaling 1536 datacom byte-synchronous operation CRC-6 generation (DS1 input) error counting (DS1 output) byte-synchronous mapping
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DATA SHEET
Mapping Synchronizer Features Mapping SONET columns according GR-253-CORE G.709
DS1MX7 TXC-04201B
channel selectable asynchronous byte-synchronous mapping floating VT1.5 TU-11 both mapping demapping Overhead assembly with BIP-2 calculation, REI-FEBE (microprocessor received BIP-2 error), signal label (microprocessor value), (microprocessor value received signal label mismatch, AIS, LOP, unequipped) (microprocessor value Yellow from signaling highway) Pointer calculation (fixed asynchronous, calculated byte-synchronous mode) with generated pointer increment decrement counters bits each) byte-synchronous mode, line clock input ('modified byte-synchronous') output ('true byte-synchronous') Multiplexing signaling bits from signaling highway with P0/P1 generation Unequipped Unassigned payload generation generation (microprocessor value, from signaling highway, loss frame bytesynchronous, external from line decoder) Threshold modulator reduce demapping jitter wander Tracking input multiframe pulses pointer movements byte-synchronous mode Demapping Desynchronizer Features Asynchronous byte-synchronous channel, programmable match mapper mode Digital with pass filter track nominal signal providing smooth clock output with need external de-jitter buffer Separate byte pointer leak buffer with programmable dual slope leak rate 2048 steps, automatically doubled 4096 steps within bits center pointer leak buffer) Power down with all-zeros all-ones sent line interface Demapping SONET columns according GR-253-CORE G.709 Asynchronous byte-synchronous demapping floating VT1.5 TU-11 Pointer tracking extraction overhead Z7/K4), AIS, with received pointer increment decrement counters bits each) Overhead processing with BIP-2 calculation error counting (12-bit, with overflow), (FEBE) counting (12-bit, with overflow), 3-bit)/ signal label de-bouncing detection, signal label mismatch unequipped detection De-multiplexing signaling bits signaling highway with multiframe generation bytesynchronous from microprocessor value, AIS, signal label mismatch unequipped Yellow signaling highway from Fractional Frame Relay, AAAL1 Access Framer required many applications Receive transmit gapped clock (1536 kbit/s) mapper byte-synchronous mode CRC-6 generation checking Direct connection multichannel HDLC Adevices kbit/s service Internal DPLL minimize received jitter TXC-04201B-MB September 2001
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DS1MX7 TXC-04201B
DATA SHEET
Signaling Support Byte-synchronous Mapping Receive transmit temporary buffers align VT1.5/TU-11 payloads signaling highway Signaling bits mapped demapped from specific locations GR-253-CORE G.709 ABCD signaling support Byte synchronous operation with TranSwitch QT1F-Plus VLSI device: Signaling positions received DS0s optionally replaced with ones QT1F-Plus (Yellow) respectively (Yellow) respectively Unicode support (DS0 alarms) byte-synchronous operation planned future framers Alarms Errors Detection AIS, RFI, unequipped, signal label mismatch, loss pointer, single-bit RDI, 3-bit RDI, demap error demap direction Detection AIS, loss signal, error, external alarm, mapping direction Counting code violations (with without excessive zeros) CRC-6 errors, BIP-2, (FEBE), pointer generation receive pointers with presets overflow indications Microprocessor enable insert alarms detected from line, calculated, overhead Maintenance Loopbacks line remote (toward line), line local (toward Telecom Bus), Telecom (toward line seven channels once) PBRS generator transmit framer analyzer receive path channel 215-1 pattern. Separate control bits with software indication Power-down modes force transmit leads low, high tristate Microprocessor Interface Nineteen-bit status register AIS, RFI, unequipped, signal label mismatch, loss pointer, single-bit RDI, 3-bit RDI, AIS, loss signal, error, demap error, external alarm, counter overflow bits code violation/CRC-6, BIP-2, (FEBE), pointer generation receive pointers Latched event registers interrupt mask registers individually control each condition Twelve-bit CRC-6 (byte-synchronous)/ code violation (asynchronous), BIP-2, (FEBE) error counters Four-bit increment decrement pointer generation receive pointer counters Shadow registers counters Full control alarm mapping through enable bits Microprocessor forcing alarm conditions channel reset resynchronization Register access Z6/N2, Z7/K4 bytes O-bits read write Performance Fault Monitoring second basis, backplane second clock Shadow registers alarms counters Separate registers indicate alarm changes (performance) hard conditions (faults) updated every second simplify performance report generation
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DATA SHEET
FEATURES THAT ONLY SELECTABLE SEVEN MAPPERS GROUP Telecom Interface Single drop with individual timing Operation 6.48 Mbyte/s 19.44 Mbyte/s Compatible with TranSwitch SOT-1E SOT-3 functional version devices
DS1MX7 TXC-04201B
Parity generation detection with device alarm (odd even) data C1J1V1 SONET mapping VT1.5 6.48 19.44 Mbyte/s mappings TU-11 AU-3 TUG-3 19.44 Mbyte/s Uses C1J1V1 locate individual Separate STS-1 phases permitted STS-3 asynchronous modified bytesynchronous operation Each transmit receive time slot programmable including internal external contention monitors with global alarm timing programmable zero clock delay Drop clock edges programmable enable plus control pins optional and/or drive signal failure input common Clock C1J1V1 presence detectors system system buses, which generate device alarms failure External Line Interface Transceiver Support Three-wire serial port read/write control seven line interface transceivers ('host mode') Designed support integrated microprocessor control loopbacks, alarms line build channel broadcast data Internal registers drive read external devices Common Microprocessor Support Microprocessor global reset, masks, polling registers, interrupt polarity latch edge control Motorola split address/data Intel split address/data Global alarm Indications ('or' channel alarms same type) with channel pointer register indicating channels with active alarms Global interrupt mask bits, alarm type Interrupt alarm changes: positive edge, negative edge both edges Device level alarms Telecom signals reference clocks using status latched event registers with interrupt mask registers Device level alarms enabled appear separate interrupt line card protection hardware software mechanisms Error insertion microprocessor parity testing Telecom Timed error insertion (FEBE) BIP-2 global value Hardware interrupt polarity selection Common hardware reset global software reset register
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DS1MX7 TXC-04201B
Auxiliary Port Common
DATA SHEET
Access from optional overhead bytes special purposes with microprocessor enables Access Z6/N2, Z7/K4 bytes O-bits received shared serial port Insertion Z6/N2, Z7/K4 bytes O-bits mapping direction shared serial port Ring Port Common Permits (FEBE) single/three-bit values sent from DS1MX7 another USHR/P support Shared serial port with clock frame transmit receive Pair DS1MX7s provides dual Telecom applications Protection, Test Maintenance Support IEEE 1149.1 boundary scan Ability tristate outputs in-circuit testing with single control Loss clock detectors parity generator/error detector drop Telecom Buses Internal alarm output programmable variety fault clock fault conditions card switch-off feature assist implementing protection switching External shadow register clock input (1Hz ppm) PRBS generator analyzer switchable seven mapper channels
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DATA SHEET BLOCK DIAGRAM
Note: n=1-7 (Channel blocks) From PRBS
DS1MX7 TXC-04201B
SRCLK
CONFIGI
TELECOM SIDE
LRCLKn RSYNCn
TRIBUTARY SIDE CLK,MF Input Timing DATA PRBS Decoder
ABCD,
APAR AADD Telecom ACLK
DATA
Synchronizer/ Mapper
Inc./Dec. alarms
Interface
AC1J1V1 ASPE AD(0-7)
RPOSn
Termination block
RNEGn/ RSIGLn/ RCVn/ RGCOn
Trib. LPBK
SLOT TIMING CLK,SPE, C1J1V1 AIS,
DATEN BUSCHK
Signaling Store
DCLK DC1J1V1 DSPE
LAISn
Alarm Control
DD(0-7)
Facility
DFAIL MASTER DPAR
LTCLKn TSYNCn
AIS,YEL Loopback (FEBE)
SRCLK
Alarm Control
Output Timing
CLK,MF
DATA
TPOSn TNEGn/ TSIGLn/ TGCOn
Desynchronizer/ Demapper
SLOT TIMING C1J1V1, CLK,SPE
Coder
DATA ABCD,
Mapper Timing
OAPCKO OAPAVO OAPADO OAPDVO OAPDTO IAPCKO IAPAVO IAPADO IAPDVO IAPDTI ORPCKO ORPFMO ORPDTO IRPCKI IRPFMI IRPDTI
Store Channel block
AIS,
Signaling
Auxiliary Port
LCSn
Alarm Control
Ring Port
PRBS Gen. Anal. RSTI LSCLK LSDO LSDI
Microprocessor Interface Common Control/Status
Test Access Port Interface (Boundary Scan)
HIGHZ TSTA TSTB
Serial RDYO/ INTO/ SELI Port (0-7) DTACKO IRQO Control READI PCKI ADDR MOTOI T1SI Interface (0-8) READI/WRI marks eight parts Line Interface block.
LINE SIDE
SYSTEM SIDE
Figure DS1MX7 TXC-04201B Block Diagram TXC-04201B-MB September 2001
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DS1MX7 TXC-04201B
DATA SHEET
BLOCK DIAGRAM DESCRIPTION
simplified block diagram DS1MX7 device shown Figure major blocks seven Channel blocks, Microprocessor Interface, Serial Port Control Interface, Ring port, Auxiliary port, PRBS (Pseudo-Random Binary Sequence) Generator Analyzer, Test Access Port Interface, Mapper Timing block Telecom Interface. Each seven Channel blocks consists following component blocks: Decoder/Coder Input/Output Timing (for Receive Transmit Line Interfaces), Receive Transmit Alarm Control, Receive Transmit Signaling Store, Synchronizer/ Mapper Desynchronizer/ Demapper, Termination, Telecom Input Output Control blocks. Receive Transmit Line Interface blocks connect each seven mapper channels external line interface transceiver, which performs clock recovery functions asynchronous mode operation. interface transceiver configured interface modes: dual unipolar (rail) interface interface. When byte-synchronous mode operation used, clock synchronization signals from external framer handled these blocks; data always mode. These blocks also provide tributary (transmit receive) loopback facility remote (receive line transmit line) loopback. When dual unipolar interface mode selected, input data from external line interface transceiver clocked into DS1MX7 pins RPOSn RNEGn using recovered receive clock present LRCLKn input pins, where n=1-7 identifies seven mappers (note: RNEGn several pins that multiple functions, with signal symbol each). transmit direction, unipolar data clocked DS1MX7 pins TPOSn TNEGn transmit line clock present LTCLKn output pins. Global control bits provided memory which enable unipolar data clocked DS1MX7 either edge clocks. dual unipolar interface mode, DS1MX7 provides either Bipolar with Eight Zero Substitution (B8ZS), Alternate Mark Inversion (AMI), coder decoder function, Loss Signal detection. Loss Signal detector meets requirements specified ANSI T1.231 document listed above DS1MX7 Features section. unframed detector also provided assist network fault isolation. 12-bit performance counter provided each mapper, counting B8ZS coding violation errors. option provided also include excessive zeros coding violations counter. When interface mode selected mapper channel programmed asynchronous mapping, data clocked RPOSn recovered received clock input LRCLKn pin. data clocked DS1MX7 TPOSn pins transmit system clock present LTCLKn pins. Global control bits provided memory which enable data inverted clocked DS1MX7 either edge clocks. Bipolar violations which detected external line interface transceiver clocked into DS1MX7 RNEGn/RCVn pins counted associated 12-bit coding violation performance counter. TNEGn output used mode spare drive bit. Remote Line Loopback function each framer also implemented Line Interface blocks. When interface mode selected mapper channel programmed byte-synchronous mapping, data clocked RPOSn pins clock present pins LRCLKn. DS1MX7 generate clock LRCLKn multiframe synchronization signal pins RSYNCn external slip buffer provided framer source signal clock slaved DS1MX7. LRCLKn RSYNCn inputs, DS1MX7 translates clock phase movements with respect SONET/SDH clock VT/TU pointer movements. applications that require framer where CRC-6 performance monitoring function desired (true byte-synchronous mode only), DS1MX7 calculates inserts CRC-6 into defined frame positions VT1.5/ TU-11 structure mapping direction. After demapping, CRC-6 checked errors found counted 12-bit counter shared code violation counting. Byte-synchronous mapping supports independent transmission signaling through defined nibbles VT1.5/ TU-11 structure, shown Figure DS1MX7 provides Receive Transmit Signaling Stores synchronize signaling framing bits from Framer switching stage with Mapper
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DATA SHEET
DS1MX7 TXC-04201B
Demapper blocks. Signaling received through RNEGn/RSIGLn pins byte-synchronous mode, being clocked with LRCLKn. Signaling sent TNEGn/TSIGLn pins byte-synchronous mode, using LTCLKn. TranSwitch framers like QT1F-Plus (TXC-03103) utilize signaling bits signaling highways automatic signaling propagation between SONET/SDH byte-synchronous mapping lines. applications using full payload byte-synchronous mode, RNEGn/RSIGLn pins programmed supply gapped clock (RGCOn), TNEGn/TSIGLn pins (TGCOn). Receive Transmit Alarm Control blocks work conjunction with Receive Transmit Line Interface blocks well Receive Transmit Signaling Store blocks move alarm signals DS1MX7. Receive Alarm Control block detects specific bits from receive signaling highway, such (Yellow), forwarding Mapper block RFI. also gathers from Receive Line Interface. LAISn input used forwarding externally detected Loss Signal Loss Clock, general interrupt input. Transmit Alarm Control block translates from Demapper block along with microprocessor controls specific bits transmit signaling highway. TranSwitch framers like QT1F-Plus (TXC-03103) utilize control bits signaling highways automatic alarm propagation between SONET/SDH lines. card protection schemes, control input CSO, when driven low, causes output pins seven Line Interfaces low. Synchronizer/ Mapper block takes clock data from Receive Line Interface asynchronous mode, threshold modulates with SRCLK, buffers FIFO inserts data bits information positions asynchronous VT1.5/ TU-11, stuffs using stuff opportunity bits with indication bits, shown Figure stuffing matches received clock positions available based SONET/SDH network clock supplied DS1MX7 Telecom Clock, ACLK AC1J1V1 signal. Optional overhead bytes Z6/N2, part taken from microprocessor-written values Auxiliary Port. Synchronizer/ Mapper block takes clock, frame data from Receive Line Interface byte-synchronous mode, buffers FIFO writes defined byte positions byte-synchronous VT1.5/ TU-11 along with optional overhead bytes Z6/N2 part which taken from microprocessorwritten values Auxiliary Port. byte-synchronous mode signaling bits taken from Receive Signaling Store mapped correct positions VT1.5/ TU-11. 500-microsecond long superframe shown Figure repeated times, being synchronized RSYNCn millisecond input. P1P0 bits generated indicate which signaling bits being carried specific superframe related RSYNCn. FIFO conditions monitored lead increment decrement requests Termination block. Synchronization changes RSYNCn monitored possible requests. Termination block takes mapped data optional overhead together with frame, increment decrement indications associated with byte-synchronous mode from Synchronizer/ Mapper block. bytes built from several received alarm sources (the receive alarms, Ring Port error conditions, microprocessor-written values). Parity then calculated over payload. positioning just after asynchronous mode only. byte-synchronous mode (true byte-synchronous modified byte-synchronous), bytes generated track phase incoming signal relative ACLK; four-bit counters provided keep track pointer increments pointer decrements generated. position RSYNCn pulse generated, this block will generate along with pointer. DS1MX7 acts clock source, will used provide this clock must frequency locked STS-1 STM-1 clock, pointer justifications and/or mapping errors will result. generated entire payload ones. unassigned (Idle) generated, allzeros payload with valid generated. unequipped generated, all-zeros payload including generated. termination block also provides pointer tracking, overhead location VT1.5/ TU-11 alarm detection de-bouncing functions. alarms (RDI four flavors, RFI, Unequipped, Signal Label Mismatch, LOP, AIS, REI, BIP-2 errors, etc.) made available common microprocessor block latching, shadowing, counting interrupting purposes. Alarms provided Ring Port support ring applications. also identifies payload Desynchronizer/ Demapper block well pointer movements. TXC-04201B-MB September 2001
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DS1MX7 TXC-04201B
DATA SHEET
Byte-synchronous Floating Mode Channels Channels Channels Channels
Legend: Stuff Control Frame Information Path Trace
Asynchronous Floating Mode Information Bytes
Overhead Bits P1P0 Signaling Phase Fixed Stuff Signaling
Information Bytes
Stuff Opportunity pointer Inc/Dec opportunity
Information Bytes
unused Overhead Reserved Byte Reserved 3-bit Byte
Information Bytes
Byte Data Flag Size
Byte
Pointer Range decimal
normal shown (new data flag 1001); S1S2 Positive Justification Invert I-bits; Negative Justification Invert D-bits; shown (bit first.
BIP-2 Byte REI-V RFI-V Signal Label RDI-V
Shown (bit first. REI-V also known FEBE. RDI-V Unequipped, AIS-V LOP-V.
Byte 3-bit RDI-V
3-bit RDI-V Codes: defects; Signal label mismatch; AIS-V LOP-V; Unequipped. Figure VT1.5/ TU-11 Asynchronous Byte-synchronous Mappings
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DATA SHEET
DS1MX7 TXC-04201B
Desynchronizer/ Demapper block takes data alarm information, along with pointer information, extracts signal. This block extracts optional overhead bytes sends Z6/N2, Auxiliary Port asynchronous mode. byte-synchronous mode, bytes omitted signaling bits sent Transmit Signaling Store instead. both modes data sent pointer leak buffer which programmable leak rate. This used minimize jitter wander asynchronously mapped signals well smooth byte-synchronously mapped signals that utilize pointer movements frequency adjustment. pointer leak rate adjusted meet MTIE requirements with simple software algorithm which uses second latched pointer increment decrement counters. Desynchronizer uses DPLL operated from signal SRCLK (48.636 MHz) that smooths stuffing jitter compensates demapping gapped positions used orders overhead. Desynchronizer outputs clock along with data Transmit Line Interface block ready transmission framing without additional de-jittering. byte-synchronous mode Frame pulse (3.0 decoded from P1P0 bits used align signaling highway Transmit Signaling Store, becomes signal TSYNCn. correct P1P0 pattern must supplied proper operation even signaling used. Alarm information (RFI AIS) sent Transmit Alarm block forwarding signaling highway. used cause DPLL output in-frequency-range all-ones signal. Telecom Input Output Control blocks buffer assembled VT1.5/ TU-11 bytes insertion extraction from Telecom Interface. Each seven mapper channels independently placed independently taken from three STS-1s TUG-3s (19.44 Telecom only), seven groups TUG-2s, four VT1.5 TU-11s. Enable control bits allow channel disconnected transmit and/or receive from Telecom Bus. Telecom Interface block combines signals from seven mapper channels synchronizes them half Telecom based ACLK, AC1J1V1 ASPE signals. configured single STS-1 (6.48 MHz), STS-3 (19.44 MHz) STM-1 (19.44 MHz). Contention checks made seven mapper channels; this feature extended using BUSCHK pins additional DS1MX7 devices sharing Bus. Parity (pin APAR) indication (pin AADD) included with byte-wide data (pins AD(0-7)). DATEN MASTER pins allow optional drive overhead stuff columns, when data delay option used. Drop part Telecom provides DCLK, DC1J1V1 DSPE signals along with failure indication (pin DFAIL) indicate seven mapper channels that received data errored higher order path, section line failures. Parity (pin DPAR) included with data (pins DD(0-7)). Parity covers drop data optionally C1J1V1 signals. signals monitored failure maskable interrupts generated both microprocessor interrupt separate failure (IAO). DS1MX7 PRBS Generator Analyzer block. Generator Analyzer supports 215-1 pattern. Generator output substituted place data stream output from each Receive Line Interface Decoder. Analyzer monitors data stream outputs from seven Receive Line Interface Decoders. setting Telecom Loopback function Telecom Interface block) Tributary Loopback seven channels, entire channel's transmit receive path verified (Synchronizer/ Mapper, Termination, Telecom Interface, Desynchronizer/ Demapper, Transmit Line Interface Receive Line Interface). moving loopbacks Framers, LIUs, Switches remote Mappers entire path verified. Line Interface Control block common block seven mapper channels that provides serial port communicating with external line interface transceiver that supports 'Host Mode' operation. This allows system microprocessor control transceiver through DS1MX7. interface consists data output (LSDO), clock output (LSCLK), data input (LSDI). These signals shared between transceivers. Each transceiver selected DS1MX7, using chip select output signals (LCSn). addition, general purpose input (LAISn) used mode generate maskable interrupt.
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DS1MX7 TXC-04201B
DATA SHEET
Test Access Port block common seven mapper channels includes five-pin Test Access Port (TAP) that conforms IEEE 1149.1 standard. This block provides external boundary scan read write DS1MX7 input output pins from board component testing. addition, four-byte read only memory location provided reading JEDEC manufacturer DS1MX7 part number, version number part. non-boundary scan testing HIGHZ provided tristate output pins. DS1MX7 provides common six-wire Ring Port block. pair DS1MX7 devices operate dual bus-based Drop Multiplexer. Since each DS1MX7 configured operate single direction ring, (FEBE) values need sent mate DS1MX7 that they returned opposite direction. Ring Port shared among seven mapper channels facilitate function sending, receiving buffering (FEBE) values from each seven mapper channels. (FEBE) information used Mapper either come from demap direction within DS1MX7 (non-ring mode), from microprocessor-forced value, from Ring Port. Ring Port outputs clock, data frame (pins ORPCKO, ORPDTO ORPFMO), expects clock, data frame inputs (pins IRPCKI, IRPDTI IRPFMI). common Auxiliary Port block provided that makes optional reserved overhead bytes from each seven mapper channels available multiplexed DS1MX7 device pins. Auxiliary Port outputs Z6/N2, Z7/K4 bytes they arrive, enabled. When mapping opportunities Z6/N2, Z7/K4 bytes come Auxiliary Port requests inputs these bytes, enabled. Microprocessor read write access these bytes also provided. DS1MX7 configured operate with either Intel Motorola-compatible microprocessors Microprocessor Input/Output Interface block. Separate address, data control pins provided. Interrupt capability provided with global individual framer mask bits well activity registers guide software exact cause interrupt most expeditious manner. wide variety alarms provided global level well mapper channel level. Each alarm error reflected current status register counter well latched value register that rising, falling both edges alarm. Shadow registers alarms counters provided, with alarm shadow registers doubled indicate either change (performance item) persistent condition (fault). latched value trigger interrupt, unless masked prevent causing interrupt. option provided software which permits interrupt polarity inverted. external system clock provided PCKI used internal state machines.
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DATA SHEET DIAGRAM
DS1MX7 TXC-04201B
LRCLK5 RNEG5/RSIGL5/RCV5/RGCO5 RPOS5 LAIS5 LCS4 TSYNC4 LTCLK4 TNEG4/TSIGL4/TGCO4 TPOS4 RSYNC4 LRCLK4 RNEG4/RSIGL4/RCV4/RGCO4 RPOS4 LAIS4 LCS3 TSYNC3 LTCLK3 TNEG3/TSIGL3/TGCO3 TPOS3 RSYNC3 LRCLK3 RNEG3/RSIGL3/RCV3/RGCO3 RPOS3 LAIS3 LCS2 TSYNC2 LTCLK2 TNEG2/TSIGL2/TGCO2 TPOS2 RSYNC2 LRCLK2 RNEG2/RSIGL2/RCV2/RGCO2 RPOS2 LAIS2 LCS1 TSYNC1 LTCLK1 TNEG1/TSIGL1/TGCO1 TPOS1 RSYNC1
RSYNC5 TPOS5 LTCLK5 TSYNC5 LCS5 LAIS6 RPOS6 LRCLK6 RSYNC6 TPOS6 LTCLK6 TSYNC6 LCS6 LAIS7 RPOS7 LRCLK7 RSYNC7 TPOS7 LTCLK7 TSYNC7 LCS7 ORPCKO ORPFMO ORPDTO IRPCKI IRPFMI IRPDTI SRCLK T1SI
TNEG5/TSIGL5/TGCO5
RNEG6/RSIGL6/RCV6/RGCO6
TNEG6/TSIGL6/TGCO6
DS1MX7
RNEG7/RSIGL7/RCV7/RGCO7
(Top View)
TNEG7/TSIGL7/TGCO7
LRCLK1 RNEG1/RSIGL1/ RPOS1 LAIS1 MASTER DATEN CONFIGI LSCLK LSDI LSDO BUSCHK2 BUSCHK1 BUSCHK0 ACLK AADD AC1J1V1 ASPE APAR DFAIL DSPE DC1J1V1 DCLK DPAR
TSTA TSTB HIGHZ RSTI ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 DTB0 DTB1 DTB2 DTB3 DTB4 DTB5 DTB6 DTB7 RDYO/DTACKO INTO/IRQO READI READI/WRI SELI MOTOI PCKI OAPCKO IAPADO IAPAVO IAPDTI IAPDVO OAPADO IAPCKO OAPAVO OAPDTO OAPDVO
Figure DS1MX7 TXC-04201B Diagram
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RCV1/RGCO1
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DS1MX7 TXC-04201B DESCRIPTIONS
Power Supply Ground Symbol
DATA SHEET
I/O/P*
Type
Name/Function VDD: volt supply,
115, 127, 139, 151, 167, 179, 191, 109, 121, 133, 145, 161, 173, 185, 101, 117, 129, 141, 153, 169, 181, 198,
GND: Ground
Connected. Leave floating. make external connections these pins connect them another. Connection impair performance cause damage device.
*Note: Input; Output; Power; Tristate
Channel Tributary Symbol LRCLKn 104, 116, 130, 143, 156, 168, I/O/P Type CMOS Name/Function Line Receive Clock Input: 1.544 clock from DSX-1 receiver asynchronous mapping mode; (tolerance ANSI Bellcore bytesynchronous operation). Global control RCAE (bit register 007H determines active edge this clock. Input jitter tolerance peak peak from peak peak from kHz. Bellcore TR-TSY-000499. byte-synchronous operation with external slip buffer which control bits MODE1,0 (bits register X+00H LRCLKn output derived from Receive Frame Sync.: millisecond multi-frame sync from framer, framer byte-synchronous mode. Sampled LRCLKn falling edge global control RCAE (bit register 007H byte-synchronous operation with external slip buffer which control bits MODE1,0 (bits register X+00H RSYNCn output derived from Tributary Receive Data (Positive): NRZ/Positive rail. data from framer DSX-1 Receiver. RPOSn sampled LRCLKn falling edge global control RCAE (bit register 007H mode, global control RXNRZP (bit register selects polarity selects logical one).
RSYNCn
105, 118, 131, 144, 157, 170,
CMOS
RPOSn
102, 113, 126, 140, 154, 165,
CMOS
*Note: Input, Output Input/Output Parameters section below Type definitions.
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DATA SHEET
Symbol RNEGn/ 103, 114, 128, 142, 155, 166, I/O/P Type CMOS Name/Function
DS1MX7 TXC-04201B
Tributary Receive Data (Negative): Negative rail data from DSX-1 receiver. This sampled LRCLKn falling edge global control RCAE (bit register 007H Receive Signaling Highway Input: Signaling Highway from framer. Sampled LRCLKn falling edge global control RCAE (bit register 007H Tributary Receive Code Violations: Code violation counter input. Sampled LRCLKn falling edge global control RCAE(bit register 007H Receive Gapped Clock Output: When datacom mode selected (only available byte-synchronous operation) control DATACOM (bit channel register X+00H being this provides gapped clock output which appears Frame times RPOSn.
RSIGLn/
RCVn
RGCOn
LAISn
100, 112, 125, 138, 152, 164,
CMOS
Line Alarm Input: Line transceiver interrupt, Loss Signal Clock from DSX-1 receiver.The active level determined global control RXNRZP (bit register 007, which selects polarity selects logical one). channel control EXPLOS (bit register X+00H enables this Control LOS2AIS (bit register X+01H, when causes this signal propagate upstream. When EXPLOS status (bit register X+10H becomes separate status indication with latched, mask, performance fault registers plus global mask status capability. Line Transmit Clock Output: 1.544 clock DSX-1 line driver framer. Global control TCAE (bit register 007H determines active edge this clock. below. output frequency tracks input frequency defined synchronized payload. Output jitter caused desynchronization single pointer movements less peak peak above (0.075 peak peak less from kHz). Tributary Transmit Data (Positive): NRZ/Positive data DSX-1 line driver framer. Output LTCLKn rising edge global control TCAE (bit register 007H mode, global control TXNRZP (bit register 007H selects polarity selects logical one). Also below.
LTCLKn
108, 122, 135, 148, 160, 174,
CMOS
TPOSn
106, 119, 132, 146, 158, 171,
CMOS
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DS1MX7 TXC-04201B
Symbol TNEGn/ 107, 120, 134, 147, 159, 172, I/O/P
DATA SHEET
Type CMOS Name/Function Tributary Transmit Data (Negative): Negative rail data DSX-1 line driver output LTCLKn rising edge global control TCAE (bit register 007H When mode used asynchronous mode this used spare output (e.g., select B8ZS/AMI line transceiver). Also below. Transmit Signaling Highway Output: Signaling highway framer. Output LTCLKn rising edge global control TCAE (bit register 007H Also below. Transmit Gapped Clock Output: When Datacom mode selected (only available byte-synchronous operation) control DATACOM (bit channel register X+00H being this provides gapped clock output which appears frame times TPOSn.
TSIGLn
TGCOn
TSYNCn
110, 123, 136, 149, 162, 175, 111, 124, 137, 150, 163, 176,
CMOS
Transmit Frame Sync: millisecond multi-frame sync framer. Output LTCLKn rising edge global control TCAE (bit register 007H Also below. Line Interface Transceiver Chip Select: active signal that enables communications both directions between external line interface transceiver channel DS1MX7. This under control global register 01AH where ENSRP (bit enables transmission channel which selected BDCST (bit select channels channel selection controls (bits 2-0) which select channels.
LCSn
CMOS
Tributary Common Control Symbol I/O/P Type CMOS Name/Function Local Oscillator: 1.544 system clock input used byte-synchronous mode. 1.544 synchronized system (ASPE, ACLK specific AC1J1V1) byte-synchronous operation where LRCLKn RSYNCn outputs. This signal also used generate serial port clock output LSCLK. System Reference Clock: 48.636 (31.5 times 1.544 MHz) system clock input used operate synchronizer, desynchronizer, PRBS generator/ analyzer, generate AIS.
SRCLK
CMOS
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DATA SHEET
Symbol LSDO I/O/P Type CMOS Name/Function
DS1MX7 TXC-04201B
Line Interface Transceiver Data Output Signal: Common serial control data output shared seven channels. command byte followed data byte, stored control registers 017H 018H respectively, transmitted line interface transceiver selected LCSn. Line Interface Transceiver Data Input Signal: Common serial control data input. data byte coincident with data byte LSDO clocked into DS1MX7 stored register 019H from line interface transceiver selected LCSn. Line Interface Transceiver Clock Signal: Common serial control clock output. 1.544 clock derived from LSDO clocked DS1MX7 falling edge LSCLK LSDI clocked into DS1MX7 rising edge LSCLK. Second Performance Clock Input: Shadow register latch. This input operates latched counters PM/FM registers. following parameter value limits suggested prevent counters from overflowing when operating noisy environments other unfavorable conditions: min. high time 0.50 min. time max. time Operation ppm, high time, recommended. This clock used conjunction with global control ENPMFM (bit register 006H clear channel event registers (not device event registers) after registers have been updated.
LSDI
CMOS
LSCLK
CMOS
T1SI
CMOS open Internal Alarm Output: Internal Alarm detected, active drain output. Control bits registers 01BH 01CH, enable Telecom clock, payload synch. failures, well parity errors PRBS lock, generate alarm interrupt this pin. Card Switch Off: When driven low, LTCLKn, TPOSn, TNEGn/TSIGLn TSYNCn driven logic level.
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DS1MX7 TXC-04201B
System Interface Symbol DCLK I/O/P
DATA SHEET
Type
Name/Function Drop Clock: Telecom clock data from system; 6.48 CONFIGI tied high 19.44 CONFIGI tied low. Control TBRCI (bit register 01EH selects rising edge DCLK active edge. Drop C1J1V1 Indicator: Telecom C1#1, J1#1, V1#1 valid from system. Valid rising edge DCLK when control TBRCI (bit register 01EH Used with DSPE identify start payload. Drop Indicator: Telecom valid from system. Valid rising edge DCLK when control TBRCI (bit register 01EH This signal high during VT1.5 TU-11 bytes from system. Drop Data: Telecom data from system; LSB. Valid rising edge DCLK when control TBRCI (bit register 01EH Drop Parity Bit: Telecom parity received over DD(0-7), DSPE DC1J1V1. Valid rising edge DCLK when control TBRCI (bit register 01EH odd/even selectable control TBPE (bit register 007H; when even parity selected. When control TBPIS (bit register 007H only DD(0-7) checked parity. Drop Signal Fail: Signal fail indication valid rising edge DCLK when control TBRCI (bit register 01EH DFAIL high specific slot contains invalid data (DD(0-7)); alarms invalid masked; generated. Clock: Telecom clock data system; 19.44 CONFIGI tied high 6.48 CONFIGI tied low. When control TBTCI (register 01EH, ASPE AC1J1V1 signals clocked rising edge ACLK. falling edge ACLK used clock AD(0-7), APAR AADD signals that these signals sampled next rising edge. When TBTCI opposite clock edges used. C1J1V1 Indicator: Telecom C1#1, J1#1, V1#1 valid data system. This signal sampled rising edge ACLK when control TBTCI (register 01EH, Used with ASPE indicate start payload system.
DC1J1V1
DSPE
DD(0-7)
DPAR
DFAIL
ACLK
AC1J1V1
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DATA SHEET
Symbol ASPE I/O/P Type Name/Function
DS1MX7 TXC-04201B
Indicator: Telecom valid data system. This signal sampled rising edge ACLK when control TBTCI (register 01EH, This signal high during VT1.5 TU-11 bytes system. Data: Telecom data system; LSB. DS1MX7 will output data falling edge ACLK when control TBTCI (register 01EH, Control TBDD (bit register 01EH selects zero ACLK clock period delay single ACLK clock period delay These signals tristate condition when DS1MX7 driving Bus. Parity Bit: Telecom parity generated AD(0-7), ASPE AC1J1V1 placed Telecom Bus. DS1MX7 will output parity falling edge ACLK when control TBTCI (register 01EH, Control TBPE (register 007H, selects odd/even parity. When TBPE parity selected. When control TBPIS (bit register 007H only AD(0-7) included parity calculation. Control TBDD (bit register 01EH selects zero ACLK clock period delay single ACLK clock period delay This signal tristate condition when DS1MX7 driving Bus. Data Present Indicator: Telecom device outputs valid. This signal goes falling edge ACLK when control TBTCI (register 01EH, This signal active when DS1MX7 writes Telecom Bus, allowing external drivers used. Control TBDD (bit register 01EH selects zero ACLK clock period delay single ACLK clock period delay This signal high when DS1MX7 driving Bus. Check: Used determine another DS1MX7 same Telecom driving same slot. Each BUSCHK input connected AADD another DS1MX7. collision detected, status TBXES (bit register 00BH Latched value, mask register bits also supplied. Master: When tied ground, stuff columns driven zero AD(0-7) with correct parity. Telecom Operations subsection. Data Enable: When high, AD(0-7), APAR AADD enabled. normally tied ASPE float Telecom during TOH.
AD(0-7)
O(T)
APAR
O(T)
AADD
BUSCHK(0-2)
MASTER
TTLp
DATEN
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DS1MX7 TXC-04201B
Symbol CONFIGI I/O/P
DATA SHEET
Type Name/Function Add/Drop Configuration Input: Configuration Telecom Bus. CONFIGI high, Telecom slot/6.48 MHz. CONFIGI low, Telecom slot/ 19.44 MHz.
Auxiliary Port Symbol OAPCKO I/O/P Type CMOS Name/Function Output Auxiliary Port Clock: DCLK divided when CONFIGI high. DCLK divided when CONFIGI low. Output Auxiliary Port Address Valid: OAPAVO High during AddreSS-bits OAPADO. Information clocked falling edge OAPCKO. Output Auxiliary Port Address: Address information identifying O-bits, Z6/N2, Z7/K4 information that will output OAPDTO. Information clocked falling edge OAPCKO. Output Auxiliary Port Data Valid: OAPDVO High during eight Data Bits OAPDTO. Information clocked falling edge OAPCKO. Output Auxiliary Port Data: This provides data byte specified preceding OAPADO Address. Information clocked falling edge OAPCKO. Input Auxiliary Port Clock: ACLK divided when CONFIGI high. ACLK divided when CONFIGI low. Input Auxiliary Port Address Valid: IAPAVO High during Address Bits IAPADO. Information clocked falling edge IAPCKO. Input Auxiliary Port Address: Address information identifying O-bits, Z6/N2, Z7/K4 information that will input IAPDTI. Information clocked falling edge IAPCKO. Input Auxiliary Port Data Valid: IAPDVO High during eight Data Bits IAPDTI. Information clocked falling edge OAPCKO. Input Auxiliary Port Data: This accepts data byte specified preceding IAPADO Address. Information clocked second rising edge IAPCKO after rising edge IAPDVO.
OAPAVO
CMOS
OAPADO
CMOS
OAPDVO
CMOS
OAPDTO
CMOS
IAPCKO
CMOS
IAPAVO
CMOS
IAPADO
CMOS
IAPDVO
CMOS
IAPDTI
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DATA SHEET
Ring Port Symbol ORPCKO ORPFMO I/O/P Type CMOS CMOS Name/Function
DS1MX7 TXC-04201B
Output Ring Port Clock: Burst clock pulses 1.944 Mbit/s. Output Ring Port Frame: Active High signal during Channel ORPFMO clocked falling edge ORPCKO. Output Ring Port Data: REI-V (FEBE), RDI-VPD, RDI-VSD, RDI-VCD data from seven channels Ring applications. Information clocked falling edge ORPCKO. Input Ring Port Clock: Burst clock pulses 1.944 Mbit/s. Input Ring Port Frame: Active High signal during Channel IRPFMI clocked rising edge IRPCKI. Input Ring Port Data: REI-V (FEBE), RDI-VPD, RDI-VSD, RDI-VCD data seven channels Ring applications. Information clocked rising edge IRPCKI.
ORPDTO
CMOS
IRPCKI IRPFMI
IRPDTI
Microprocessor Interface Symbol RSTI I/O/P Type TTLp Name/Function Hardware Reset: Device reset. This active signal will reset seven mappers. should held minimum clock periods PCKI. Motorola Mode: Motorola Intel microprocessor mode select. High selects Motorola. selects Intel. Data: Microprocessor bidirectional, tristate data bus; DTB0 LSB. Address Bus: Microprocessor address bus; ADDR0 LSB. Select: Microprocessor Interface select. selects interface allows transfer information between DS1MX7 microprocessor. Read: Read Read/Write. Intel: read DS1MX7. Motorola: high read/low write. Write: Intel mode only; write DS1MX7.
MOTOI DTB(0-7)
ADDR(0-8)
SELI
TTLp
READI READI/WRI
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DS1MX7 TXC-04201B
Symbol RDYO/ I/O/P O(T)
DATA SHEET
Type Name/Function Ready: Intel mode: high acknowledges that data transfer take place this cycle. indicates wait states. Data Transfer Acknowledge: Motorola mode: during read indicates data valid. during write indicates data accepted. Interrupt: Intel mode: control IPOL (bit register 006H high indicates interrupt request microprocessor. Interrupt Request: Motorola mode: control IPOL (bit register 006H indicates interrupt request microprocessor. Processor Clock: Processor Clock Input. Required device operation; MHz. DS1MX7 will continue pass data loss PCKI, microprocessor access will blocked.
DTACKO
INTO/
IRQO
PCKI
Boundary Scan Test Port Symbol I/O/P Type Name/Function Test Clock: IEEE 1149.1 Boundary Scan Clock input. This clock used shift data into rising edge falling edge. Test Data Input: Boundary Scan Data input. Serial test instructions data clocked into this rising edge TCK. Test Data Output: Boundary Scan Data output. Serial data test instructions clocked this falling edge TCK. Test Mode Select: Boundary Scan Test Mode Select input; sampled rising edge DS1MX7 into test mode. Test Reset: Boundary Scan Reset input. This will asynchronously reset Test Access Port (TAP) controller held minimum duration This held low, asserted pulsed reset controller DS1MX7 power-up. High Impedance Select: Grounding this causes outputs except high impedance alters internal registers. Test Device test pin. Must connected ground. Test Device test pin. Must connected ground.
TTLp
O(T)
TTLp
TTLp
HIGHZ
CMOS
TSTA TSTB
CMOS CMOS
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DATA SHEET ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL LIMITATIONS
Parameter Supply voltage input voltage Storage temperature range Ambient operating temperature Moisture Exposure Level Relative Humidity, during assembly Relative Humidity, in-circuit Classification Symbol -0.3 -0.5 +7.0 Unit
DS1MX7 TXC-04201B
Conditions Note Note Note ft/min linear airflow EIA/JEDEC JESD22-A112-A Note non-condensing Note
Level
absolute value 2000
Notes: Conditions exceeding values cause permanent failure. Exposure conditions near values extended periods impair device reliability. Pre-assembly storage non-drypack conditions recommended. Please refer instructions "CAUTION" label drypack which devices supplied. Test method MIL-STD-883D, Method 3015.7.
THERMAL CHARACTERISTICS
Parameter Thermal resistance from junction ambient, Unit
oC/W
Test Conditions ft/min linear airflow
POWER REQUIREMENTS
Parameter supply voltage supply current 4.75 5.25 Unit Asynchronous mapping; CONFIGI High. Asynchronous mapping; CONFIGI High. Byte-synchronous mapping; CONFIGI Low. 5.25V. Byte-synchronous mapping; CONFIGI Low. 5.25V. Test Conditions
supply power
supply current
supply power
1500
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DS1MX7 TXC-04201B
DATA SHEET
INPUT, OUTPUT INPUT/OUTPUT PARAMETERS
Input Parameters CMOS Parameter Input leakage current Input capacitance Unit Test Conditions 4.75 <VDD 5.25 4.75 <VDD 5.25 5.25
Input Parameters Parameter Input leakage current Input capacitance Unit Test Conditions 4.75 <VDD 5.25 4.75 <VDD 5.25
Input Parameters TTLp Parameter Input leakage current Input capacitance
Note: Input (nominal) internal pull-up resistor.
Unit
Test Conditions 4.75 <VDD 5.25 4.75 <VDD 5.25 5.25; Input volts
Output Parameters CMOS Parameter tRISE tFALL Leakage tristate -4.0 Unit CLOAD CLOAD 5.25 input Test Conditions 4.75; -4.0 4.75;
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DATA SHEET
Output Parameters CMOS Open Drain Parameter tFALL High leakage current Unit CLOAD 5.25
DS1MX7 TXC-04201B
Test Conditions 4.75;
Note: Open Drain requires 4.7k external pull-up resistor. this resistor provided output behaves tristate.
Output Parameters Parameter tRISE tFALL -8.0 Unit CLOAD CLOAD Test Conditions 4.75; -8.0 4.75;
Input/output Parameters CMOS Parameter Input leakage current Input capacitance tRISE tFALL -4.0 Unit CLOAD CLOAD 4.75; -4.0 4.75; Test Conditions 4.75 <VDD 5.25 4.75 <VDD 5.25 5.25
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DS1MX7 TXC-04201B
DATA SHEET
Input/output Parameters Parameter Input leakage current Input capacitance tRISE tFALL -8.0 Unit CLOAD CLOAD 4.75; -8.0 4.75; Test Conditions 4.75 <VDD 5.25 4.75 <VDD 5.25 5.25
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DATA SHEET TIMING CHARACTERISTICS
DS1MX7 TXC-04201B
Detailed timing diagrams DS1MX7 illustrated Figures through with values timing intervals tabulated below each diagram. output times measured with maximum load capacitance, unless otherwise indicated. Timing parameters measured voltage levels (VOH VOL)/2 output signals (VIH VIL)/2 input signals. Figure Tributary Input Timing
tCYC tPWH tPWL
LRCLKn (see Notes RPOSn RNEGn RSIGLn RCVn
tSU(1)
tH(1)
RSYNCn (see Notes
Note: n=1-7
tH(2) tSU(2)
Parameter LRCLKn clock period LRCLKn high time LRCLKn time RPOS/RNEG/RSIGL/RCV setup time LRCLK RPOS/RNEG/RSIGL/RCV hold time after LRCLK RSYNC pulse width input RSYNC pulse width output RSYNC setup input before LRCLK RSYNC hold input after LRCLK RSYNC delay output after LRCLK
Symbol tCYC tPWH tPWL tSU(1) tH(1) tSU(2) tH(2)
Unit
Notes: true byte-synchronous mode (control bits MODE0 MODE1 LRCLKn RSYNCn outputs. other modes LRCLKn RSYNCn inputs. LRCLKn active edge inverted control RCAE (bit register 007H; shown RCAE RPOSn, RNEGn, RSIGLn, RSYNCn RCVn clocked falling edge LRCLKn. true byte-synchronous mode operation, LRCLKn RSYNCn outputs. RSYNCn output delayed from rising edge LRCLKn when control RCAE
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DS1MX7 TXC-04201B
DATA SHEET
Figure Tributary Output Timing
tCYC LTCLKn* TPOSn TNEGn TSIGLn TSYNCn
Note: n=1-7
tPWH
Parameter LTCLKn clock period LTCLKn duty cycle, tPWH/tCYC TPOS/TNEG/TSIGL output delay after LTCLK TSYNC delay after LTCLK TSYNC pulse width
Symbol tCYC -tOD
-5.0 -5.0
Unit
LTCLKn inverted control TCAE (bit register 007H; shown TCAE
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DATA SHEET
Figure Signaling Highway Structure
DS1MX7 TXC-04201B
LRCLK LTCLK tCYC RSYNC TSYNC RPOS/ RNEG TPOS/ TNEG RSIGL*
-DS0
F1/M1
S1/C1
TSIGL*
F1/M1
S1/C1
Multi-frame Number 4630 4631 Multi-frame
Note: n=1-7
Note shown 16-state signaling. Operation section. Note TPOS, TNEG, RPOS, RNEG, RSIGL, TSIGL unused bits (see Operation section). Note present positions through (DS0 24); bits through unused.
Parameter TSYNCn/RSYNCn clock period (n=1-7) TSYNCn/RSYNCn pulse width (n=1-7)
Symbol tCYC
3.000 clock period LTCLK LRCLK*
Unit
TSYNC RSYNC should valid active edge LTCLK LRCLK, respectively.
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DS1MX7 TXC-04201B
DATA SHEET
Figure Serial Control Port Structure Timing
LCSn
tCYC tD(1)
tPWH
tH(2)
LSCLK
tPWL
tH(1)
LSDI
Data Input/Output
LSDO
addr
addr
addr
addr
addr
addr
addr
Address/Command Byte
tD(2)
Parameter LSCLK clock period LSCLK high time LSCLK time LCSn delay time LSCLK LCSn inactive pulse width LSDI setup time LSCLK LSDI hold time after LSCLK LSCLK LCSn inactive LSDO delay after LSCLK LSCLK rise fall times (10% 90%)
Symbol tCYC tPWH tPWL tD(1) tH(1) tH(2) tD(2)
Unit
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DATA SHEET
Figure Telecom Input Timing 6.48 Operation
tCYC DCLK (Input) tPWH DD(0-7) DPAR (Input) tSU(1) tH(2) tSU(3) tPWL tH(1) tSU(2) V1#1
DS1MX7 TXC-04201B
V4#1
DSPE (Input) DC1J1V1 (Input)
tH(3) V1#1
Parameter DCLK clock period DCLK high time DCLK time DD(0-7)/DPAR setup time DCLK DD(0-7)/DPAR hold time after DCLK DSPE setup time DCLK DSPE hold time after DCLK DC1J1V1 setup time DCLK DC1J1V1 hold time after DCLK DC1J1V1 pulse width
Symbol tCYC tPWH tPWL tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3)
154.32
Unit
116*
gapped clock applications, skipping rising (and next falling) edge DCLK will extend current time twice listed value. data clocked rising clock edge unless control TBRCI (bit register 01EH which case data clocked falling clock edge.
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DS1MX7 TXC-04201B
DATA SHEET
Figure Telecom Input Timing 19.44 Operation
tCYC
DCLK (Input) tPWH DD(0-7) DPAR (Input) tSU(1) tH(2) tSU(3)
tPWL C1#1
tH(1) J1#1 tSU(2) V1#1 V4#1
DSPE (Input) DC1J1V1 (Input)
tH(3) C1#1 J1#1
V1#1
Parameter DCLK clock period DCLK high time DCLK time DD(0-7)/DPAR setup time DCLK DD(0-7)/DPAR hold time after DCLK DSPE setup time DCLK DSPE hold time after DCLK DC1J1V1 setup time DCLK DC1J1V1 hold time after DCLK DC1J1V1 pulse width individual pulse (e.g., isolated DC1J1V1 J1#1 V1#1 delay (STS-3 mode) DC1J1V1 J1#1 V1#1 delay (STM-1 mode)
Symbol tCYC tPWH tPWL tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3)
51.44
Unit
cycles DCLK cycles DCLK
gapped clock applications, skipping rising (and next falling) edge DCLK will extend current time twice listed value. data clocked rising clock edge unless control TBRCI (bit register 01EH which case data clocked falling clock edge.
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DATA SHEET
Figure Telecom Output Timing 6.48 Operation
tCYC ACLK (Input) AD(0-7) APAR (Output) ASPE (Input) tH(2) AC1J1V1 (Input) AADD (Output) DATEN (Input) V1#1 tPWL tD(1) tSU(1) tSU(2) tH(1) V1#1
DS1MX7 TXC-04201B
tPWH
tD(2) DATA tD(3)
tD(4)
tD(5)
tD(6)
Parameter ACLK clock period ACLK high time ACLK time AD(0-7)/APAR delay time after ACLK AD(0-7)/APAR float time after ACLK ASPE setup time ACLK ASPE hold time after ACLK AC1J1V1 setup time ACLK AC1J1V1 hold time after ACLK AD(0-7)/APAR delay time after DATEN AD(0-7)/APAR delay time after DATEN AADD delay time after DATEN AADD delay time after DATEN AADD delay time after ACLK AC1J1V1 pulse width AD(0-7)/APAR rise/fall times (10% 90%)
Symbol tCYC tPWH tPWL tD(1) tSU(1) tH(1) tSU(2) tH(2) tD(2) tD(3) tD(4) tD(5) tD(6)
154.32
116*
Unit
15.9 13.6 13.1 13.2 10.9 16.8
gapped clock applications, skipping rising (and next falling) edge ACLK will extend current time twice listed value. control TBTCI (bit register 01EH data clocked rising ACLK clock edge falling ACLK clock edge, shown timing diagram. control TBTCI data clocked falling clock edge rising clock edge ACLK. control TBDD AD(0-7), APAR AADD delayed clock period from what shown timing diagram with reference ASPE AC1J1V1; Input DATEN must also delayed clock period ACLK.
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Figure Telecom Output Timing 19.44 Operation
tCYC ACLK (Input) AD(0-7) APAR (Output) ASPE (Input)
tPWH
tPWL tD(1) tSU(1) tSU(2) tH(2) tD(7) J1#1 V1#1 tD(4) tD(5) C1#1 tH(1) J1#1 V1#1 tD(2) DATA tD(3)
AC1J1V1 (Input) AADD (Output) DATEN (Input)
C1#1
tD(6)
Parameter ACLK clock period ACLK high time ACLK time AD(0-7)/APAR delay time after ACLK AD(0-7)/APAR float time after ACLK ASPE setup time ACLK ASPE hold time after ACLK AC1J1V1 setup time ACLK AC1J1V1 hold time after ACLK AD(0-7)/APAR delay time after DATEN AD(0-7)/APAR delay time after DATEN AADD delay time after DATEN AADD delay time after DATEN AADD delay time after ACLK AC1J1V1 pulse width individual pulse (e.g., isolated AD(0-7)/APAR rise/fall times (10% 90%) AC1J1V1 J1#1 V1#1 delay (STS-3 mode) AC1J1V1 J1#1 V1#1 delay (STM-1 mode)
Symbol tCYC tPWH tPWL tD(1) tSU(1) tH(1) tSU(2) tH(2) tD(2) tD(3) tD(4) tD(5) tD(6) tD(7) tD(7)
51.44
Unit
15.9 13.6 13.1 13.2 16.8 10.9 cycles DCLK cycles DCLK
gapped clock applications, skipping rising (and next falling) edge ACLK will extend current time twice listed value. control TBTCI (bit register 01EH data clocked rising ACLK clock edge falling ACLK clock edge, shown timing diagram. control TBTCI data clocked falling clock edge rising clock edge ACLK. control TBDD AD(0-7), APAR AADD delayed clock period from what shown timing diagram with reference ASPE AC1J1V1; Input DATEN must also delayed clock period ACLK. TXC-04201B-MB September 2001
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Figure Auxiliary Port Timing
tCYC OAPCKO IAPCKO tPWL OAPAVO IAPAVO tPWH
DS1MX7 TXC-04201B
OAPADO IAPADO
OAPDVO IAPDVO
OAPDTO
IAPDTI
Parameter OAPCKO IAPCKO period times DCLK ACLK clock period) Delay OAPCKO OAPAVO, OAPADO, OAPDVO OAPDTO IAPCKO IAPAVO, IAPADO, IAPDVO Fall Time (90% 10%)-OAPAVO, OAPADO, OAPDVO, OAPDTO, IAPAVO, IAPADO, IAPDVO Hold IAPDTI after IAPCKO OAPCKO IAPCKO High time OAPCKO IAPCKO time Rise Time (10% 90%) OAPAVO, OAPADO, OAPDVO, OAPDTO, IAPAVO, IAPADO, IAPDVO Setup IAPDTI IAPCKO Wait OAPAVO IAPAVO time
Symbol tCYC
308.64/ 102.88*
Unit
-2.0
tPWH tPWL
tCYC tCYC tCYC
Notes: first number 6.48 operation; second 19.44 operation. load Auxiliary port transfers depend Telecom drop assignments controlled registers X+04H X+05H being valid, with control TBTVAL (bit register X+05H auxiliary input timing (IAPAVO, IAPADO, IAPADO) control TBRVAL (bit register X+04H auxiliary output timing (OAPAVO, OAPADO, OAPDVO, OAPDTO). Also, input byte fetched, related control bits OBAPEN, J2APEN, Z6APEN Z7APEN (bits 3-0) register X+0BH must
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Figure Ring Port Timing
tCYC tPWL tPWH
ORPCKO IRPCKI
ORPFMO IRPFMI ORPDTO IRPDTI
CH1, REI-V
CH1, RDI-VPD
Parameter ORPCKO IRPCKI period Delay ORPCKO ORPFMO ORPDTO Fall Time (90% 10%) OPRCKO, ORPFMO ORPDTO Hold IRPFMI IRPDTI after IRPCKI Rise Time (10% 90%) ORPCKO, ORPFMO ORPDTO ORPCKO IRPCKI High time ORPCKO IRPCKI time Setup IRPFMI IRPDTI IRPCKI
*Note: load
Symbol tCYC tPWH tPWL
514.4
Unit
tCYC tCYC
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Figure Datacom Mode Output Timing
DS1MX7 TXC-04201B
tCYC tPWL tPWH
LTCLKn
tD(1)
TGCOn (TNEG)
tD(2) Time
TPOSn
TSYNCn
Note:
Parameter LTCLKn period Delay LTCLKn
Symbol tCYC
-5.0
Unit tCYC tCYC
TGCOn
tD(1) tD(2) tPWH tPWL
Delay LTCLKn TPOSn TSYNCn Fall Time (90% 10%) LTCLKn, TGCOn, TPOSn TSYNCn LTCLKn TGCOn High time LTCLKn TGCOn time Rise Time (10% 90%) LTCLKn, TGCOn, TPOSn TSYNCn
Notes: LTCLKn inverted with control TCAE (bit register 007H. LTCLKn shown with TCAE load
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Figure Datacom Mode Input Timing
tCYC tPWL tPWH
LRCLKn (see Note RGCOn
tD(1)
tD(2)
RSYNCn (Output)
RSYNCn (Input)
Time
RPOSn
Note:
Parameter LRCLKn period Delay LRCLKn1,2 RGCOn Delay LRCLKn1,2 RSYNCn Output Fall Time (90% 10%)3- RGCOn, LRCLKn RSYNCn Outputs
Symbol tCYC tD(1) tD(2) tPWH tPWL
Unit
Hold RPOSn RSYNCn input after LRCLKn1,2 LRCLKn RGCO High time LRCLKn RGCO time Rise Time (10% 90%)3RGCOn, LRCLKn RSYNCn Outputs
Set-up RPOSn RSYNCn input LRCLKn1,2
Notes: LRCLKn active edge inverted control RCAE (bit register 007H; shown RCAE RPOSn, RNEGn, RSIGLn, RSYNCn RCVn clocked falling edge LRCLKn. true byte-synchronous mode operation (control bits MODE0 MODE1 01), LRCLKn RSYNCn outputs. RSYNCn output delayed from rising edge LRCLKn when control RCAE LRCLKn shown with RCAE load.
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Figure Intel Microprocessor Read Cycle Timing
DS1MX7 TXC-04201B
ADDR (0-8)
(0-7)
tD(1) tSU(1)
SELI
tSU(2) tPW(1)
READI
tD(2)
RDYO
tPW(2)
Parameter ADDR(0-8) setup time SELI DTB(0-7) valid delay after RDYO DTB(0-7) float time after READI SELI setup time READI READI pulse width SELI hold time after READI RDYO delay after READI RDYO pulse width
Symbol tSU(1) tD(1) tSU(2) tPW(1) tD(2) tPW(2)
Unit
-1/2 cycle PCKI* cycles PCKI*
cycles PCKI*
*Note: PCKI (not shown) Processor Clock Input, MHz, which required device operation.
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Figure Motorola Microprocessor Read Cycle Timing
ADDR (0-8)
DTB(0-7)
tSU(1) tF(1) tPW(1) tSU(2)
SELI
READI/WRI tPW(2) DTACKO tD(2)
tD(1) tF(2)
Parameter DTB(0-7) float time after SELI ADDR(0-8) valid setup time SELI READI/WRI setup time SELI SELI pulse width DTACKO pulse width DTB(0-7) output delay after DTACKO DTACKO float time after SELI DTACKO delay after SELI
Symbol tF(1) tSU(1) tSU(2) tPW(1) tPW(2) tD(1) tF(2) tD(2)
cycles PCKI*
Unit
cycles PCKI* -1/2 cycle PCKI*
*Note: PCKI (not shown) Processor Clock Input, MHz, which required device operation.
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Figure Intel Microprocessor Write Cycle Timing
DS1MX7 TXC-04201B
ADDR (0-8)
tH(1)
DTB(0-7)
tSU(2) tSU(1)
SELI
tSU(3)
tPW(1)
RDYO
tPW(2)
Parameter DTB(0-7) valid setup time DTB(0-7) hold time after ADDR(0-8) setup time SELI SELI setup time pulse width RDYO delay after RDYO pulse width
*Note:
Symbol tSU(1) tH(1) tSU(2) tSU(3) tPW(1) tPW(2)
Unit
cycles PCKI*
PCKI (not shown) Processor Clock Input, MHz, which required device operation. Wait states only occur write cycle immediately follows previous read write cycle (e.g.'read modify write' word-wide write).
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Figure Motorola Microprocessor Write Cycle Timing tH(2)
ADDR (0-8) tH(1) DTB(0-7)
tSU(1) tSU(2)
SELI
tPW(1) tSU(3)
READI/WRI
tPW(2)
DTACKO
Parameter DTB(0-7) valid setup time SELI DTB(0-7) valid hold time after SELI ADDR(0-8) valid setup time SELI ADDR(0-8) valid hold time after SELI READI/WRI setup time SELI SELI pulse width DTACKO pulse width DTACKO float time after SELI DTACKO delay after SELI
*Note:
Symbol tSU(1) tH(1) tSU(2) tH(2) tSU(3) tPW(1) tPW(2)
Unit
cycles PCKI*
PCKI (not shown) Processor Clock Input, MHz, which required device operation. Wait states only occur write cycle immediately follows previous read write cycle (e.g.'read modify write' word-wide write).
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Figure Boundary Scan Timing
DS1MX7 TXC-04201B
tPWL tPWH
(Input)
tH(1) tSU(1)
(Input)
tH(2) tSU(2)
(Input)
(Output)
Parameter clock high time clock time setup time hold time after setup time hold time after delay from
Symbol tPWH tPWL tSU(1) tH(1) tSU(2) tH(2)
Unit
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GENERAL MAPPER APPLICATION OVERVIEW DS1MX7 used wide variety applications (see Figures through that require either asynchronous mapping signal into SONET payload which input clock data replicated output, byte-synchronous mapping signal into SONET payload which only input clock data replicated output, visibility signaling information replicated output. When used asynchronous application side mapper connects line through Line Interface Units (LIUs) that recover 1.544 from data, provide clock data DS1MX7, input clock data from DS1MX7 format line signal transmission. port provided control LIUs from DS1MX7. When used byte-synchronous applications, framers inserted between LIUs DS1MX7 delineate DS0s, extract insert signaling, process alarms, etc. byte-synchronous applications also used direct interface sources DS0s (e.g., time slot interchangers, codecs) data sources like fractional with HDLC protocol channels. DS1MX7 provides complete clock recovery signals through stage digital filter, eliminating need special external de-jitter buffers. DS1MX7 provides complete SONET order path termination origination functions (VT1.5/ TU-11) with alarm mapping from line. system side, that required high order section, line path termination origination function. Telecom provided DS1MX7 allows multiple devices connected seamlessly TranSwitch SOT-1E SOT-3 device, both which supply these high order functions. separate port provided access optional overhead bytes. redundant ring applications ring port provided well special alarm output isolation input. microprocessor port provided configure DS1MX7 well provide interrupts device wide/ Telecom alarms well VT1.5/ TU-11 alarms. second shadow registers provided assist preparation performance monitoring information. IEEE 1149.1 boundary scan function internal PRBS generator/ analyzer provided manufacturing support. LINE INTERFACE SELECTION Each seven DS1MX7 channels individually programmed asynchronous mode, byte-synchronous mode clock master, modified byte-synchronous mode where DS1MX7 channel clock slave which pointer movements generated needed incoming signal SONET/ payload. table below details options present Line Interface. Mode Operation Asynchronous Asynchronous Asynchronous Asynchronous Byte-synchronous LRCLK/RSYNCn Byte-synchronous (Datacom) LRCLK/RSYNCn Modified byte-synchronous LRCLK/RSYNCn Line Code B8ZS
MODE1 MODE0 X+00 LCODE X+00 ENCOD X+00 DATACOM X+00
RNEGn Data Data RCVn RCVn RSIGLn input RGCOn output RSIGLn input
TNEGn
X+00
Data Data High TSIGLn output TGCOn output TSIGLn output
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DS1MX7 TXC-04201B
LCODE X+00 ENCOD X+00 DATACOM X+00
Mode Operation Modified byte-synchronous (Datacom) LRCLK/RSYNCn
Line Code
MODE1
MODE0 X+00
RNEGn RGCOn output
TNEGn
X+00
TGCOn output
Asynchronous Operation with Line Interface Each seven mappers DS1MX7 programmed provide either dual unipolar interface interface. dual unipolar interface selected when written into control ENCOD (bit control register located address X+00H memory map. 040H), where number mapper selected (1-7), explained Memory section. B8ZS line coder/decoder (CODEC) feature selected dual unipolar interface. B8ZS CODEC selected writing control LCODE (bit register X+00H. will select CODEC. B8ZS stands Bipolar with Eight Zero Substitution, which described ANSI Document ANSI T1.102-1993 other Bellcore documents. clock polarity input output line clocks selectable writing sense required global control bits TCAE RCAE (bits register 007H. When mapper configured dual unipolar mode, line signal monitored loss signal (LOS). detected transitions present pulse positions. Recovery occurs when ones density 12.5% more detected pulse positions. status LOSS (bit register X+10H indicates this condition. mask, LOSM, latched value, LOSE, value, LOSPM value, LOSFM available (bit register locations X+08H, X+14H, X+18H X+1CH respectively. Coding violations counted 12-bit performance counter located register locations X+22H X+23H with shadow value registers X+2AH X+2BH. counter overflow CVOS (bit register X+10H provided. mask, CVOM, latched value, CVOE, value, CVOPM value, CVOFM available (bit register locations X+08H, X+14H, X+18H X+1CH respectively. Excessive zeros more B8ZS more AMI) included control ENZC (bit register X+00H indication provided which checks more than 99.9% ones occur millisecond period less than 99.9% ones occur millisecond period. Status DAISS (bit register X+10H indicates condition. mask, DAISM, latched value, DAISE, value, DAISPM value, DAISFM available (bit register locations X+08H, X+14H, X+18H X+1CH respectively. condition also used generate (DS1 payload all-ones will mapped place received signal) control LOS2AIS (bit register X+01H Coder block provides AMI/B8ZS encoder. This block provides generation either from Microprocessor Interface control SDAISL (bit register X+03H when optionally from various system conditions AIS/LOP, Signal Label Mismatch Unequipped) which individually enabled control bits VAIS2AIS (bit X+01H), SLM2AIS (bit X+02H) UNE2AIS (bit X+02H) being high level signal failure input DFAIL will cause seven mappers. 'transmit all-zeros' capability provided conserve power external Line Transceiver when required setting control SDAISL (bit register X+03H when control TBRVAL (bit register X+04H also (Drop slot assigned). connections between DS1MX7 mapper external line interface transceivers shown Figure dual unipolar mode.
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RXTIP RXRING TXTIP TXRING
Line Interface Transceiver channel
SCLK
receive
transmit
RPOSn RNEGn LRCLKn TPOSn TNEGn LTCLKn
DS1MX7
LCSn LAISn LSCLK LSDO LSDI
Other Transceivers Note: channel number
Figure Line Interface Dual Unipolar Mode interface selected when written into control ENCOD (bit register X+00H. clock polarity line input output clocks selectable writing global control bits TCAE RCAE (bits register 007H. Options provided inverting polarity transmit receive data pins. written control TXNRZP (bit global register 007H inverts polarity transmit data signal, TPOSn, while written control RXNRZP (bit same register inverts polarity receive data signal RPOSn. mode, RNEGn used input external indication coding violations (RCVn). External coding violations counted same 12-bit performance counter described above. Coding violations counted when input high rising edges line clock LRCLKn. same detector described above bipolar available mode. detected only externally input LAISn. setting control EXPLOS (bit register X+00H LOSS status plus latched event, mask, functions provided described above. transmit direction, when mode selected, TNEGn becomes spare drive pin. When control ENCOD (bit register X+00H output state TNEGn defined value written LCODE (bit register X+00H (LCODE TNEGn LCODE high TNEGn). typical interface between mapper DS1MX7 external line transceiver shown Figure below mode. TNEGn, example, used select encoding mode LIU.
RXTIP RXRING TXTIP TXRING
Line Interface Transceiver channel
SCLK
receive
transmit
RPOSn RCVn LRCLKn TPOSn TNEGn LTCLKn
DS1MX7
LCSn LAISn LSCLK LSDO LSDI
Other Transceivers Note: channel number
Figure Line Interface Mode
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Byte-synchronous Operation with Line Interface
DS1MX7 TXC-04201B
byte-synchronous operation line interface operates mode with RSIGLn TSIGLn carrying signaling information from/to external framer using negative polarity input output pins. Figure basic byte-synchronous setup. Typical applications shown Figures bytesynchronous applications where signaling used, Datacom option provided connections HDLC controllers other devices that operate over payload only. TGCO RGCO gapped clock outputs clocking data TPOSn RPOSn. clock gapped during frame time every This option available setting control DATACOM (bit register X+00H byte-synchronous applications that require DS1-based performance monitoring (control bits MODE1, register X+00H bits only), CRC-6 generated optionally each superframe data presented RPOSn inserted frame locations following superframe mapped. When control CRC6 (bit register X+01H CRC-6 both inserted checked. After demapping CRC-6 checked. CRC-6 errors share 12-bit line code violation counter shadow register overflow indications support performance monitoring. CRC-6 errors counted 12-bit performance counter located register locations X+22H X+23H with shadow value registers X+2AH X+2BH. Each superframe which calculated CRC-6 value does match received CRC-6 value increments counter one. counter overflow CVOS (bit register X+10H provided. mask, CVOM, latched value, CVOE, value, CVOPM value, CVOFM available (bit register locations X+08H, X+14H, X+18H X+1CH respectively.
RXTIP RXRING TXTIP TXRING
Framer Other Device
receive
RPOSn RSIGLn/RGCOn LRCLKn RSYNCn LTCLKn TPOSn TSIGLn/TGCOn TSYNCn
DS1MX7
transmit
Note: channel number
Figure Byte-synchronous Interface Framer Receive Data Signaling Highway Operation receive highway carries information from framer DS1MX7. highway sub-divided into time division multiplexed buses, data (RPOSn), signaling, frame alarms (RSIGLn). These buses synchronous with signals LRCLKn RSYNCn, 1.544 clock millisecond synchronization signal driven from framer DS1MX7 depending mode bytesynchronous operation. DS1MX7 operates modified byte-synchronous mode, receive clock synchronization inputs DS1MX7; DS1MX7 operates true byte-synchronous mode, receive clock synchronization outputs DS1MX7. data highway single-bit serial organized into 193-bit groups called frames. Each frame consists spare position followed twenty-four 8-bit data samples representing DS0s. frames form multiframe, beginning which identified synchronization pulse, RSYNCn. RSYNCn high pulse occurs time before first frame multiframe every frames after that. signaling highway, RSIGLn, also divided into 193-bit frames. Each frame consists frame followed bits signaling alarm information data channels data highway. frame pattern tracks signaling pattern received from system. alarm
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bits signaling highway follow signaling bits. each frame bits, four signaling bits transmitted followed (Yellow) alarm position. positions coincident with through used alarm bit. Signaling bits through occur frame number one, followed through frame number two, ending with through frame number corresponding mode with 16-state signaling. two-state four-state signaling bits bits replaced bits bits respectively, shown following table. receive framing format signaling format shown Figures signaling information stored Signaling Store block mapping. alarm information (DS1 RAI-Yellow) stored Alarm Control block enabled generate automatically. Control SH2VAIS (bit register X+01H, when causes alarm bits signaling highway activate generation affected channel. When control YEL2RFI (bit register X+01H RAI-Yellow alarm signaling highway causes DS1MX7 mapper channel send byte. status these signaling highway alarm bits available SHDAIS SHYEL (bits register X+20H status only. When control AIS2VAIS (bit register X+01H DS1MX7 will cause generated condition defined above asynchronous mode operation detected. When control DATACOM (bit register X+00H RSIGLn input becomes RGCOn output, which gapped LRCLKn clock with LRCLKn cycle wide occurring frame time RPOSn every microseconds. Signaling positions RSIGLn TSIGLn Frame SF/ESF 16-St. RSIGL; S1-S4
F1/M1 S1/C1 F2/M2 S2/F1 F3/M3 S3/C2 F4/M4 S4/F2 F5/M5 S5/C3 F6/M6 S6/F3 F1/M7 S1/C4 F2/M8 S2/F4 F3/M9 S3/C5 F4/M10 S4/F5 F5/M11 S5/C6 F6/M12 S6/F6 A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, B01, B02, B03, B05, B06, B07, B09, B10, B11, B13, B14, B15, B17, B18, B19, B21, B22, B23, C01, C02, C03, C05, C06, C07, C09, C10, C11, C13, C14, C15, C17, C18, C19, C21, C22, C23, D01, D02, D03, D05, D06, D07, D09, D10, D11, D13, D14, D15, D17, D18, D19, D21, D22, D23,
TSIGL; S1-S4
A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, B01, B02, B03, B05, B06, B07, B09, B10, B11, B13, B14, B15, B17, B18, B19, B21, B22, B23, C01, C02, C03, C05, C06, C07, C09, C10, C11, C13, C14, C15, C17, C18, C19, C21, C22, C23, D01, D02, D03, D05, D06, D07, D09, D10, D11, D13, D14, D15, D17, D18, D19, D21, D22, D23,
4-State; S1-S4
A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, B01, B02, B03, B05, B06, B07, B09, B10, B11, B13, B14, B15, B17, B18, B19, B21, B22, B23, A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, B01, B02, B03, B05, B06, B07, B09, B10, B11, B13, B14, B15, B17, B18, B19, B21, B22, B23,
2-State; S1-S4
A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23,
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DS1MX7 TXC-04201B
RSYNCn frame frame frame frame
frame (193 bits)
LRCLKn
RPOSn
channel
bits channel
channel
channel
channel
RSIGLn
frame bit; AIS; RAI-Yellow alarm; signaling bits; assigned Figure System Interface Receive Framing Format
RSYNCn frame frame frame frame
RPOSn
first bits frame
first bits frame
first bits frame
first bits frame
first bits frame
LRCLKn
RSIGLn
Figure System Interface Receive Signaling Format
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DS1MX7 TXC-04201B
DATA SHEET
Transmit Data Signaling Highway Operation transmit highway carries information from DS1MX7 framer. highway sub-divided into time division multiplexed buses, data (TPOSn) signaling, frame bits alarms (TSIGLn). These buses synchronous with signal LTCLKn, 1.544 clock that driven from DS1MX7. data highway single bit-serial that organized into 193-bit groups called frames. Each frame consists frame followed twenty-four 8-bit data samples. Each 8-bit data samples represents single receive highway. 193-bit frames grouped into 24-frame multiframe. order help locate beginning frame extract signaling information, DS1MX7 sources synchronization signal, TSYNCn. byte synchronous mode only; TSYNCn present standard compliant P1P0 pattern present VT1.5 TU-11 shown Figure TSYNCn high pulse occurs time before first frame multiframe every frames after that. signaling highway, TSIGLn, also divided into 193-bit frames organized identical fashion RSIGLn (see table above signaling assignments). alarm bits signaling highway follow signaling bits. each frame bits, four signaling bits transmitted followed (Yellow) alarm position. positions coincident with through used alarm bit. Signaling bits through occur frame number followed through frame number ending with through frame number corresponding mode with 16-state signaling. two-state four-state signaling bits bits replaced bits bits respectively, shown table above. Yellow alarm sourced DS1MX7 output same positions RSIGLn. These alarm bits used force Yellow automatically QT1F-Plus. Control VAIS2AIS (bit register X+01H, when causes detection VT-LOP bits TSIGLn unless control DATACOM (bit register X+00H Similarly, control bits SLM2AIS (bit UNE2AIS (bit register X+02H either Signal Label Mismatch Unequipped condition exists, bits signaling highway unless control DATACOM Setting control SDAISL (bit register X+03H will also bits TSIGLn unless control DATACOM Control SDAISL control bits VAIS2AIS, SLM2AIS UNE2AIS condition LOP/AIS, Signal Label Mismatch Unequipped occurs will cause all-ones signal generated TPOSn without regard control bits DATACOM MODE1. Likewise, Yellow alarm signaling highway control RFI2YEL (bit register X+01H alarm detected, control SYELL (bit register X+03H when control MODE1 (bit register X+00H indicating byte-synchronous operation DATACOM (bit same register indicating TSIGLn used gapped clock output. frame bits received from VT1.5/ TU-11 available TSIGLn well; they track signaling bits used extraction. When control DATACOM (bit register X+00H TSIGLn output becomes TGCOn output, which gapped LTCLKn clock with LTCLKn cycle wide occurring frame time TPOSn every microseconds. System interface transmit framing format signaling format shown Figures
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DS1MX7 TXC-04201B
TSYNCn frame frame frame frame
frame (193 bits)
LTCLKn
TPOSn
channel
bits channel
channel
channel
channel
TSIGLn
frame bit; AIS; Yellow alarm;
signaling bits;
assigned
Figure System Interface Transmit Framing Format
TSYNCn TPOSn frame frame frame frame
first bits frame
first bits frame
first bits frame
first bits frame
first bits frame
LTCLKn
TSIGLn
Figure System Interface Transmit Signaling Format Signaling Store Alarm Control blocks buffer signaling alarm information sent signaling highway. signaling bits output shown table above well Figure support certain protection schemes, when tied will cause transmit line interface leads (LTCLKn, TNEGn/TSIGLn/TGCOn, TPOSn, TSYNCn) driven logic low.
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Synchronizer, Mapper Overhead Generator Synchronizer/Mapper block operates three different modes, programmable channel basis described above Line Interface Section. Synchronizer/Mapper heart mapping side device. synchronizes 1.544 Mb/s data stream SONET/SDH clock domain, maps data stream virtual tributary (VT1.5/ TU-11) inserts order path overhead performance monitoring administrative purposes. Figure shows result synchronization, mapping overhead insertion functions form VT1.5/ TU-11 asynchronous byte-synchronous mode. synchronization function adjusts approximately bits that they into VT1.5 TU-11 which microseconds long. signal, whether framed formats framed another format, generates bits every microseconds. shown Figure three opportunities provided bits plus bytes) opportunity bits used information), (one used information) bits (both bits used information) VT1.5/ TU-11 asynchronous mode. stuffing control bits repeated twice provided every VT1.5/ TU-11 indicate stuffing opportunity used information stuff; C1C1C1 indicates that used information C1C1C1 indicates that used stuff bit. treated likewise. This mechanism allows majority voting used desynchronizer, providing robust solution high error rates. DS1MX7 input buffer that written line clock read SONET/ clock. stuffing control DS1MX7 uses depth this input buffer value Buffer overflow/ underflow fault condition input caused input frequency being outside stuffing range asynchronous mapping (approximately Hz). This condition will passed Microprocessor Interface alarm (Map Error). Status (bit register X+10H indicates Error status; mask MPM, latched event MPE, performance value MPPM hard fault value MPFM registers X+08H, X+14H, X+18H X+1CH respectively. stuffing mechanism DS1MX7 employs threshold modulation such that desynchronizer will meet GR-253-CORE category jitter requirements. This done using SRCLK vary input clock's phase every sequential VT1.5/ TU-11 such that stuffing pattern varies frequency high enough filtered easily desynchronizer. This prevents clock that different from SONET/SDH derived 1.544 reference clock from generating jitter spikes when desynchronized. This feature turned testing purposes setting global control TMDIS (bit register 03DH Byte-synchronous mapping permits full signaling visibility shown Figure bytes every microseconds DS0s; stuffing mechanism replaced P1/P0 pattern that used identify different frame bits well which signaling bits being sent which what DS0s. Byte-synchronous mapping performs synchronization different ways. When LRCLKn RSYNCn outputs they derived from signal which must sourced from SONET/SDH payload timing (ACLK, ASPE AC1J1V1). such, exactly DS0s, frame four signaling bits mapped every microseconds. RSYNCn output defines start first superframes (the pattern goes from that form multiframe. source different clock than external slip buffer must provided; TranSwitch QT1F-Plus (TXC-03103) provides this function. Since some applications want have added delay frames slip buffering (e.g. TR-496 Objective 3-6), modified version byte-synchronous mapping provided where LRCLKn RSYNCn inputs floating VT1.5/ TU-11 mode. tributary line side operates from input timing block, where data into block. system side operates Telecom SONET/SDH drop timing. line side clock multi-frame synchronization uses buffering supplied this block. input buffer becomes full synchronizer requests pointer decrement generated Termination block which aligns virtual container virtual tributary; this will cause extra byte data read input buffer microsecond period. Figure byte will skipped everything will shift byte. Likewise, input buffer empty synchronizer requests pointer increment causing position repeated less byte data will read input buffer microsecond period. Buffer overflow/underflow fault condition input caused loss frame
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DS1MX7 TXC-04201B
synchronization control LOF2VAIS (bit register X+01H this mode. This condition will passed Microprocessor Interface alarm (Map Error). Status (bit register X+10H indicates Error status; mask MPM, latched event MPE, performance value MPPM hard fault value MPFM registers X+08H, X+14H, X+18H X+1CH respectively. RSYNCn input defines start first superframes (the P1/P0 pattern goes from 00), shown table below. Mapper takes output synchronizer adds overhead bits bytes positions driven with values stored registers X+36H (O-bits), X+37H byte), X+38H (Z6/N2 byte) X+39H (Z7/K4 byte) unless Auxiliary Port used. Auxiliary Port used enable (OBAPEN, J2APEN, Z6APEN Z7APEN, bits register X+0BH) specific byte byte brought from Auxiliary Port inserted into overhead byte position well above register locations. asynchronous operation only, eight O-bits bits included shown Figure byte-synchronous operation mapper also multiplexes into payload data from Signaling Store, which contains both ABCD signaling bits each also frame bits. Since signaling framing bits framed take milliseconds single superframe, 500-microsecond superframes required define P1/P0 bits byte-synchronous mapping coded identify signaling framing bits shown table below. Refer Figure signaling P1/P0 positions. signaling bits shown ESF; with fourstate signaling CnDn bits AnBn bits repeated; two-state signaling AnBnCnDn becomes AnAnAnAn table below. Whether frame bits provided not, DS1MX7 calculate CRC-6 over DS0s only, inserting them positions table below control CRC6 (bit register X+01H TranSwitch QT1F-Plus (TXC-03103) supports insertion specific ABCD signaling codes signaling buffer write capability optionally forces robbed positions support byte-synchronous GR-253-CORE signaling conditional requirements.
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Signaling Frame Assignments Byte-synchronous Modes CRC1 FPS1 CRC2 FPS2 CRC3 FPS3 CRC4 FPS4 CRC5 FPS5 CRC6 FPS5 3.000 2.500 2.000 1.500 1.000 Time (ms) 0.125 0.250 0.375 0.500
Legend: signaling bits 16-state signaling format represent bits robbed from frames 4-state signaling interpreted 2-state signaling interpreted frame alignment bits signaling framing bits FPSn frame alignment bits; CRCn CRC-6 bits ESF; Facility Data Link bits ESF.
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Pointer Generation Telecom Slot Selection
DS1MX7 TXC-04201B
DS1MX7 device only VT1.5/TU-11 termination provided. Termination block accepts data, alarms timing information from Synchronizer/Mapper block completes generation VT1.5/ TU-11 started Synchronizer/Mapper block. Each mapper VT1.5/ TU-11 slots shown Figure Figure below. Control TBTVAL (bit register X+05H must VT1.5/ TU-11 added Telecom Bus. Bits same register determine STS-1, TUG-3 number (one three). Bits this same register determine Group TUG-2 number (one seven) bits determine VT1.5 TU-11 number (one four). asynchronous operation fixed position generated (offset with valid next VT/TU byte after shown Figure above. modified version byte-synchronous operation, synchronous payload envelope virtual container (VT-SPE/ moves accommodate frequency differences described above. Termination block provides pointer generation state machine that follows Bellcore, ANSI rules T1.105, GR-253-CORE G.709 generating more than single movement every four superframes (2.0 ms). Loss frame signal will cause start superframe position when signal recovers; this will force Data Flag (NDF) request Termination block. exiting synchronizer block will re-center buffer request NDF. synchronizer block will also look change expected position RSYNCn indicate request upstream. Valid bytes always generated. used stuff opportunity when pointer decrements done unused. true byte-synchronous operation fixed position results from fact that clock frame synchronization outputs which synchronous with SONET/SDH structure even though pointer generation state machine enabled. four-bit counters (one count increments generated count decrements generated) provided track frequency deviations. These counters located X+25H (bits increment bits decrement) with latched shadow values located same bits X+2DH. overflow either counter occurs, status PGOS (bit register X+10H interrupt generated; second polling/clearing this counter recommended. mask PGOM, latched event PGOE, performance value PGOPM hard fault value PGOFM registers X+08H, X+14H, X+18H X+1CH respectively. byte generated modes. formed from bit-interleaved parity calculation, signal label stored register X+07H bits 2-0, three alarm bits, REI-V, RFI-V RDI-V. that entire virtual container formed, BIP-2 bits calculated inserted byte shown Figure based previous VT-SPE/ chosen make bits every byte VT-SPE even parity second chosen make even bits every byte VT-SPE even. alarm bits mapped based results demapping, Line conditions Ring Port shown table below. When Ring Port enabled, only gets REI-V RDI-V from this port. RFI-V used byte-synchronous modes only comes from microprocessor-forced value result softwarebased failure detection (usually second range) persisting line, section high order path defect signaling highway result Yellow alarm.
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Generation Alarm Sources Controls Alarm BIP-2 Microproc. Force
SBIPE reg. X+03H, ECTL(7-0) reg. 01DH sets number times SFEBE reg. X+03H, ECTL(7-0) reg. 01DH sets number times SRFI reg. X+03H,
Demap Conditions
none
Line Conditions
none
Enable Controls
FEBEIS reg. X+02H, enables microproc. forcing. FEBEIS normal calculation. FEBEIS reg. X+02H, enables microproc. forcing. FEBEIS normal calculation. YEL2RFI reg. X+01H,
Ring
none
Ring Enable
none
REI-V
BIP-2 errors
none
REI-V
RINGEN reg. X+0BH,
RFI-V
Software integrated Yellow signaling failure state from highway; LOS, LOF, AIS-L/P/ Y-bit LOP-P/V, UNEQP/V, PLM-P/V AIS-V, LOP-V UNEQ-V none
none
none
RDI-V
SRDI-VSD reg. X+02H, SRDI-VCD reg. X+02H,
RDIIS RDI-VSD reg. X+02H, enables microproc. RDI-VCD forcing. RDIIS normal insertion from demap
RINGEN reg. X+0BH,
support three-bit RDI, byte also encoded based different demap conditions three-bit values supplied Ring Port. unused bits Z7/K4 supplied from Auxiliary Port internal register X+39H; Figure shows byte usage three-bit RDI. table below defines conditions that generate three-bit RDI. When alarms occur Demap side DS1MX7 supplied internally Ring Port, higher priority code always replaces lower priority code. Three-bit Generation Sources Controls Alarm Microproc. Force Demap Code Conditions bits
Priority
Enable Controls
Ring
Ring Enable
RDI-VSD SRDI-VSD AIS-V, LOP-V reg. X+02H, RDI-VCD SRDI-VCD reg. X+02H, RDI-VPD SRDI-VPD reg. X+02H, none
none UNEQ-V PLM-V defects
RDIIS RDI-VSD RINGEN reg. X+02H, reg. X+0BH, enables microproc. RDI-VCD forcing. RDIIS normal insertion from demap RDI-VPD
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DS1MX7 TXC-04201B
VT/TU Idle Insertion performed this point. Microprocessor Interface controls allow either valid with all-zeros payload generated idle all-zeros unequipped. Control IDLE (bit register X+00H, when powers down channel. Control bits RDIIS, FEBEIS, SBIPE, SFEBE, Transmit Signal Label, SRDI-VPD, SRDI-VSD, SRDI-VCD have effect idle signal sent. table below provides recommended settings idle unassigned (but still monitored) idle unequipped (not monitored). Idle Control DS1MX7 Control
IDLE; reg. X+00H, RDIIS; reg. X+02H, SRDI-VPD; reg. X+02H, SRDI-VSD; reg. X+02H, SRDI-VCD; reg. X+02H, FEBEIS; reg. X+02H, SFEBE; reg. X+03H, SBIPE; reg. X+03H, reg. X+39H, bits RINGEN Ring Port used); reg. X+0BH,
Valid Payload
Payload
Note: Don't Care
Control bits SH2VAIS, LOS2AIS, LOF2VAIS, AIS2VAIS, SDAISS SVTAIS, together with mapping mode control bits (MODE1, MODE0 DATACOM) line decoder controls (ENCOD EXPLOS) determine whether mapped. alarm bits signaling highway, Loss Frame modified byte-synchronous mode, microprocessor command, all-ones detected decoder, condition detected decoder condition signal LAIS used generate (DS1 payload all-ones will mapped place received signal) (payload, overhead plus bytes all-ones). table below details feature.
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VT-AIS Generation Sources Controls Alarm Generated Microproc. Force
SDAISS reg. X+03H,
DS1Line DATACOM MODE1 MODE0 Conditions reg. X+00H, reg. X+00H, reg. X+00H,
All-ones LAIS high
Enable Controls
none (passes through) none EXPLOS reg. X+00H, LOS2AIS reg. X+01H, ENCOD reg. X+00H, LOS2AIS reg. X+01H, none EXPLOS reg. X+00H, LOS2AIS reg. X+01H, SH2VAIS reg. X+01H, AIS2VAIS reg. X+01H, LOF2VAIS reg. X+01H,
detected
SVTAIS reg. X+03H,
LAIS high
TSIGLn A-bits >99.9% ones detected decoder Loss signal RSYNCn
Note: Don't Care
VT/TU Pointer Tracking Telecom Slot Selection DS1MX7 device only VT1.5/TU-11 termination provided. Termination block accepts data, high order alarms timing information from Telecom Interface block, tracks VT1.5/ TUI-11 pointer extracts alarms. Termination block also provides data, alarms control Desynchronizer/Demapper block. operations (pointer interpretation, pointer generation, VT/TU detection, detection, etc.) performed accordance with GR-253-CORE, G.709, G.783. Each mapper drop VT1.5/ TU-11 from slots shown Figure Figure below. Control TBRVAL (bit register X+04H must VT1.5/ TU-11 dropped from Telecom Bus. Bits same register determine STS-1, TUG-3 number (one three). Bits this same register determine Group TUG-2 number (one seven) bits determine VT1.5 TU-11 number (one four). values chosen same different from values. starting location byte determined pulses DC1J1V1 signals. VT/TU pointer assignment bytes shown below. alignment necessary determine starting locations byte other bytes that carrying 1544 kbit/s format.
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Byte Byte
DS1MX7 TXC-04201B
SS-bits
Increment Decrement Data Flag (enabled 1001 0001/1101/1011/1000, normal disabled 0110 1110/0010/0100/0111) Negative Justification: Inverted D-bits accept rule Positive Justification: Inverted I-bits accept rule SS-bits Size) 1544 kbit/s, Pointer Bytes Assignment
pointer value binary number with range 1544 kbit/s format. indicates offset from byte first byte VT1.5 mapping. pointer bytes counted offset calculation. pointer offset arrangement this format shown below. 1544 kbit/s TU-11/VT1.5 79-102 1-24 27-50 53-76 VT/TU Pointer Offset Locations
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Seven independent pointer tracking state machines used DS1MX7. pointer tracking algorithm illustrated Figure pointer tracking state machine based pointer tracking machine found latest ETSI requirements, also valid both Bellcore ANSI. GR-253-CORE G.709 pointer processing rules. Where differences occur GR-253-CORE rules used; particular, state exited state invalid pointers; receipt all-ones pointer considered invalid pointer until consecutive all-ones pointers received (considered AIS); pointers without count toward consecutive pointers even though INC/DEC action taken result pointer mimicking INC/DEC; INC/DEC decision bits. When control (bit register 007H transition from enabled (shown dotted), which required recommendations. Increments decrements forwarded desynchronizer counting pointer leak controls described below.
AIS_ind (Offset Undefined)
inc_ind (Incr. Offset) any_point new_point (Accept Offset)
NDF_enable (Accept Offset) NDF_enable (Accept Offset)
AIS_ind (Offset Undefined)
new_point (Accept Offset) NDF_enable (Accept Offset) new_point (Accept Offset) any_point NDF_enable (Accept Offset) inv_point (Offset Undefined) dec_ind (Decr. Offset) any_point
NORM
new_point (Accept Offset) AIS_ind (Offset Undefined) new_point (Accept Offset)
new_point (Accept Offset)
AIS_ind NDF_enable (Offset Undefined) (Offset Undefined)
inv_point (Offset Undefined) NDF_enable (Accept Offset) AIS_ind (Offset Undefined)
Figure VT/TU Pointer Tracking State Machine
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DS1MX7 TXC-04201B
From Telecom input, extracted means DC1J1V1 DSPE. VT/TU individually made available Microprocessor Interface status bits VAISS LOPS (bits register X+11H. Masks VAISM LOPM, latched events VAISE LOPE, performance values VAISPM LOPPM hard fault values VAISFM LOPFM bits registers X+09H, X+15H, X+19H X+1DH respectively.The logical `OR' these alarms handled demapped described above Transmit Data Signaling Highway section. `SS' bits compared expected value `11' VT1.5/TU-11 interpreted (high level signal failure input DFAIL masks VTAIS, VTLOP Signal Label Mismatch). SS-bits available status only bits RXSS1 RXSS0 (bits register X+20H. Demapper Signal Label received Byte extracted sent Microprocessor Interface. stored bits register X+20H. Additional processing performed detect Signal Label Mismatch (compare with Expected Signal Label) Unequipped Code. Both conditions reported Microprocessor Interface notification Unequipped Signal Label Mismatch Condition (also known Path Label Mismatch PLM-V) handled described herein mapping direction. Status bits UNES SLMS (bits register X+11 indicate current condition. Masks UNEM SLMM, latched events UNEE SLME, performance values UNEPM SLMPM hard fault values UNEFM SLMFM bits registers X+09H, X+15H, X+19H X+1DH respectively. mismatch alarm considered consecutive Signal Labels different condition; consecutive matches will clear alarm. Signal Label `Equipped Nonspecific' (001) received considered mismatch non-zero expected value. Also, Expected Signal Label 'Equipped-Nonspecific' (001) non-zero value received Signal Label will cause alarm. unequipped signal label received, DS1MX7 will generate alarm regardless setting expected signal label (including 000). alarm should masked when both ends connection programmed unequipped path exists. table below shows alarms based received versus expected value, GR-253-CORE. Signal Label Mismatch Unequipped Alarms Expected Signal Label Stored reg. X+07H, bits Received Signal Label
Legend:
UNEQ
match found alarm Path label mismatch alarm, PLM-V UNEQ Unequipped alarm DS1MX7 will generate alarm RX/EXP=000/000)
Z7/K4 Bytes further processed extract BIP-2 Errors, VT/TU (FEBE) Events, VT/TU RDI-V VT/TU Alarms. VT/TU RDI-V de-bounced (default) (selectable) consecutive superframes before alarm declared; (default) (selectable) consecutive RDI-V will clear alarm. De-bounce control through global register RDID10 (bit register 01EH which, when
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causes DS1MX7 de-bounce bits over superframes. de-bounced consecutive superframes before alarm declared; consecutive will clear alarm. byte alarms sent Microprocessor Interface once de-bounced, with status bits RFIS RDI-VS (bits register X+11H. Masks RFIM RDI-VM, latched events RFIE RDI-VE, performance values RFIPM RDI-VPM hard fault values RFIFM RDI-VFM bits registers X+09H, X+15H, X+19H X+1DH respectively. VT/TU Alarm sent signaling highway Yellow byte-synchronous modes only, described Transmit Data Signaling Highway section. BIP-2 Errors VT/TU (FEBE) events accumulated 12-bit overflow indicating counters. Control (bit register 007H, when will cause BIP-2 errors count blocks (count error both BIP-2 bits received different than calculated). When each different counts error. BIP-2 Error counter located location X+26H X+27H with shadow value located X+2EH X+2FH. overflow BIPOS (bit register X+11H overflow occurs. (FEBE) Error counter located location X+28H X+29H with shadow value located X+30H X+31H. overflow FEOS (bit register X+11H overflow occurs. Masks BIPOM FEOM, latched events BIPOE FEOE, performance values BIPOPM FEOPM hard fault values BIPOFM FEOFM bits registers X+09H, X+15H, X+19H X+1DH respectively. DS1MX7 supports three-bit using Z7/K4 byte. Three-bit enhanced Remote Defect Indication that provides three classes defects: Payload Defect (Path Label Mismatch), Server Defects (Loss Pointer AIS) Connect

Mapper 7-Channel TXC-04201B DATA SHEET FEATURES Seven independent

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