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Typical VOLP (Output Ground Bounce) 25°C High-Drive Outputs (-32-mA IO


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SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Typical VOLP (Output Ground Bounce) 25°C High-Drive Outputs (-32-mA IOH, 64-mA IOL) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds JEDEC Standard JESD Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
SN54ABT573 PACKAGE SN74ABT573A PACKAGE (TOP VIEW)
description
These 8-bit latches feature 3-state outputs designed specifically driving highly capacitive relatively low-impedance loads. They particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. eight latches SN54ABT573 SN74ABT573A transparent D-type latches. While latch-enable (LE) input high, outputs follow data inputs. When taken low, outputs latched logic levels inputs.
SN54ABT573 PACKAGE (TOP VIEW)
buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operations latches. data retained data entered while outputs high-impedance state. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. This device fully specified partial-power-down applications using Ioff. Ioff circuitry disables outputs, preventing damaging current backflow through device when powered down.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 2001, Texas Instruments Incorporated
products compliant MIL-PRF-38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
PACKAGE (TOP VIEW)
terminal assignments
ORDERING INFORMATION
PDIP SOIC -40°C 85°C 40°C SSOP TSSOP VFBGA CDIP -55°C 125°C LCCC PACKAGE Tube Tube Tape reel Tape reel Tape reel Tape reel Tube Tube Tube ORDERABLE PART NUMBER SN74ABT573AN SN74ABT573ADW SN74ABT573ADWR SN74ABT573ADBR SN74ABT573APWR SN74ABT573AGQNR SNJ54ABT573J SNJ54ABT573W SNJ54ABT573FK TOP-SIDE MARKING SN74ABT573AN ABT573A AB573A AB573A AB573A SNJ54ABT573J SNJ54ABT573W
SNJ54ABT573FK Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. FUNCTION TABLE (each latch) INPUTS OUTPUT
logic diagram (positive logic)
Seven Other Channels numbers shown packages.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high power-off state, -0.5 Current into output state, SN54ABT573 SN74ABT573A Input clamp current, Output clamp current, Package thermal impedance, (see Note package 70°C/W package 58°C/W package 76°C/W package 69°C/W package 83°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. package thermal impedance calculated accordance with JESD 51-7.
recommended operating conditions (see Note
SN54ABT573 Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate Outputs enabled SN74ABT573A UNIT ns/V
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER Vhys IOZH IOZL Ioff ICEX TEST CONDITIONS Outputs high Outputs high input Other inputs Outputs Outputs disabled -100 ±100 -180 -180 ±100 -180 0.55 0.55* 0.55 0.55 25°C -1.2 SN54ABT573 -1.2 SN74ABT573A -1.2 UNIT
products compliant MIL-PRF-38535, this parameter does apply. typical values This data sheet limit vary among suppliers. more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
SN54ABT573 25°C Pulse duration, high Setup time data before time, Hold time, data after High UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
SN74ABT573A 25°C Pulse duration, high High Setup time, data before time UNIT
Hold time, data after This data sheet limit vary among suppliers.
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
SN54ABT573 PARAMETER FROM (INPUT) (OUTPUT) 25°C tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ UNIT
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
SN74ABT573A PARAMETER FROM (INPUT) (OUTPUT) 25°C tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ UNIT
This data sheet limit vary among suppliers.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
From Output Under Test (see Note
LOAD CIRCUIT Input VOLTAGE WAVEFORMS PULSE DURATION
Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Control tPZL Output Waveform (see Note tPZH Output Waveform Open (see Note tPLZ tPHZ VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
Input tPLH Output tPHL tPHL tPLH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
Output
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such products services might used. TI's publication information regarding third party's products services does constitute TI's approval, license, warranty endorsement thereof. Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations notices. Representation reproduction this information with alteration voids warranties provided associated product service, unfair deceptive business practice, responsible liable such use. Resale TI's products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service, unfair deceptive business practice, responsible liable such use. Also see: Standard Terms Conditions Sale Semiconductor Products. www.ti.com/sc/docs/stdterms.htm
Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated

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