40MX 42MX FPGA Families High Capacity Certification Ceramic
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40MX 42MX FPGA Families
High Capacity
Certification Ceramic Devices Available DSCC
Ease Integration
Single Chip ASIC Alternative 2,000 36,000 Available Logic Gates Kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry User-Programmable Pins Clock-to-Out Performance Dual-Port SRAM Access FIFOs 35-Bit Address Decode
High Performance
HiRel
Commercial, Industrial, Military Temperature Plastic Packages Commercial, Military Temperature MIL-STD-883 Ceramic Packages
Integrator Series Product Profile
Device Capacity A40MX02 A40MX04
Mixed Voltage Operation (5.0V 3.3V I/O). Synthesis-Friendly Architecture Support ASIC Design Methodologies. 95-100% Resource Utilization, Using Automatic Place Route Tools with 100% Fixing. Deterministic, User-Controllable Timing DirectTime Software Tools. Diagnostics Debug Supported Silicon Explorer. Supported Actel Designer Series Development System with Interfaces Popular Design Environments including Cadence, Exemplar, IST, Mentor Graphics, Synopsys, Synplicity, Viewlogic. Power Consumption IEEE standard 1149.1 (JTAG) Boundary Scan Testing 5.0V 3.3V Programmable PCI-Compliant
A42MX09
A42MX16
A42MX24
A42MX36
Gates ASIC-Equivalent Gates SRAM Bits
Logic Modules
2,000 1,200 PL44 PL68 PQ100 VQ80
4,000 2,000 PL44 PL68 PL84 PQ100 VQ80
9,000 4,000 PL84 PQ100 PQ160 TQ176 VQ100
16,000 8,000 PL84 PQ100 PQ160 PQ208 TQ176 VQ100
24,000 14,000 1,410 PL84 PQ160 PQ208 TQ176
36,000 20,000 2,560 1,230 1,184 1,230 1,822 PQ208 PQ240 BG272 CQ208 CQ256
Sequential Combinatorial Decode
Clock-to-Out SRAM Modules (64x4 32x8) Dedicated Flip-Flops Maximum Flip-Flops Clocks User (Maximum) JTAG Packages
March 2000
2000 Actel Corporation
General Description
newest additions Actel's Integrator Series programmable logic devices, 40MX 42MX families, provide system logic designers with high performance, cost-effective ASIC alternative single FPGA. device architecture based Actel's patented antifuse technology implemented 0.45µ triple-metal CMOS process. With capacities ranging from 2,000 36,000 gates, synthesis-friendly devices provide datapaths MHz, live power-up, deliver five times lower stand-by power consumption than other FPGA device. Actel's FPGAs provide I/Os, available wide variety packages speed grades. Actel's 42MX family FPGAs also feature MultiPlex I/O, advanced architectural feature that supports mixed voltage systems, enables programmable PCI, delivers high-performance operation both 5.0V 3.3V, provides low-power mode. MultiPlex supports most common voltage standards today: pure 5.0V operation, pure 3.3V operation, mixed 3.3V operation with 5.0V operation input tolerance maximum performance. Internal array performance retained 3.3V systems using complimentary pass gates that operate fast 3.3V they 5.0V. MultiPlex includes selectable output drives certain 42MX devices, enabling 100% PCI-compliance both 5.0V 3.3V systems. low-power systems, MultiPlex used turn inputs outputs current consumption below 100µA. 42MX FPGA devices also include system-level features such JTAG, dual-port SRAM, fast wide-decode modules. 42MX family offers industry's fastest dual-port SRAM implementing fast FIFOs, LIFOs, temporary data storage. large number storage
elements efficiently address applications requiring wide datapath manipulation, perform transformation functions such telecommunications, networking, DSP. 42MX FPGAs were designed integrate system logic that typically implemented multiple CPLDs, PALs, FPGAs. Compliant devices were specifically designed percent compliant with Local Specification (version 2.1). Combining PCI-compliance with industry's most synthesis friendly architecture provides fastest solution FPGA, regardless whether you're designing interface from scratch using third-party synthesizable "core." A42MX24 A42MX36 devices offer high-performance, PCI-compliant programmable solution. PCI-compliant devices deliver on-chip operation nanosecond clock-to-output performance with capacities spanning from 24,000 36,000 gates. Actel's Compliant devices provide high capacity, synthesis friendly programmable solution applications. section numbers notes denote pertinent section Local Specification version 2.2. devices comply 100% electrical timing specifications detailed specification. However, with programmable logic devices, performance final product depends upon user's design optimization techniques. products 40MX 42MX families available percent tested over Military temperature range. addition, largest member family, A42MX36 available both CQ208 CQ256 packages screened MIL-STD-883 levels. easy prototyping conversion from plastic ceramic CQ208 PQ208 compatible.
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Ordering Information
A42MX16
Application (Temperature Range) Blank Commercial +70°C) Industrial (-40 +85°C) Military (-55 +125°C) MIL-STD-883 Package Lead Count Package Type Plastic Leaded Chip Carrier Plastic Quad Flat Pack Thin (1.4 Quad Flat Pack Very Thin (1.0 Quad Flat Pack Ball Grid Array Ceramic Quad Flat Pack Speed Grade Blank Standard Speed Approximately Faster than Standard Approximately Faster than Standard Approximately Faster than Standard Approximately Slower than Standard Part Number A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 2,000 Gates 4,000 Gates 9,000 Gates 16,000 Gates 24,000 Gates 36,000 Gates
Product Plan
Speed Grade1 A40MX02 Device 44-Pin Plastic Leaded Chip Carrier (PLCC) 68-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 80-Pin Very Thin Plastic Quad Flat Pack (VQFP) A40MX04 Device 44-Pin Plastic Leaded Chip Carrier (PLCC) 68-Pin Plastic Leaded Chip Carrier (PLCC) 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 80-Pin Very Thin Plastic Quad Flat Pack (VQFP) A42MX09 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 160-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) A42MX16 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 160-Pin Plastic Quad Flat Pack (PQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) A42MX24 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 160-Pin Plastic Quad Flat Pack (PQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) A42MX36 Device 208-Pin Plastic Quad Flat Pack (PQFP) 240-Pin Plastic Quad Flat Pack (PQFP) 272-Pin Plastic Ball Grid Array (PBGA) 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) Applications: Commercial Industrial Military MIL-STD-883 Availability: Available Planned Planned Application
Speed Grade: Approx. Faster than Standard Approx. Faster than Standard Approx. Faster than Standard Approx. Slower than Standard Speed Grades only available Commercial temperature. Devices only available Speed Grades.
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Integrator Series devices supported Actel's Designer Series development software, which provides seamless integration into many ASIC design flows. Designer Series development tools offer automatic place route (even with pre-assigned pins), static timing analysis, user programming, debug diagnostic probe capabilities. DirectTime tool provides deterministic controllable timing, allowing designer specify performance requirements individual paths system clocks. Using these specifications, software will automatically optimize placement routing logic meet constraints. Also included with Designer Series tools Actel's ACTgen Macro Builder. ACTgen allows designer quickly build fast, efficient logic functions such counters, adders, FIFOs, RAM. Designer Series tools provide designers with capability move high-level description languages,
Plastic Device Resources
such VHDL Verilog-HDL, schematic design entry with interfaces most tools. Designer Series supported Pentium workstations. software provides interfaces Cadence, Mentor Graphics, Escalade, OrCAD, Viewlogic design environments. Additional development tools supported through Actel's Industry Alliance Program, including Data (ABEL FPGA) MINC. Actel's FPGAs provide high-performance, single-chip solution shortening system design development cycle, they offer cost-effective alternative ASICs. 40MX 42MX devices excellent choices integrating logic that currently implemented multiple PALs, CPLDs, FPGAs. Example applications include high-speed controllers address decoding, peripheral interfaces, DSP, co-processor functions.
User I/Os Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 PLCC 44-Pin PLCC 68-Pin PLCC 84-Pin VQFP 80-Pin VQFP PQFP PQFP PQFP PQFP TQFP 100-Pin 100-Pin 160-Pin 208-Pin 240-Pin 176-Pin 272-Pin
Package Definitions (Consult your local Actel sales representative product availability.) PLCC Plastic Leaded Chip Carrier, PQFP Plastic Quad Flat Pack, TQFP Thin Quad Flat Pack, VQFP Very Thin Quad Flat Pack, PBGA Plastic Ball Grid Array
Ceramic Device Resources
User I/Os Device A42MX36 CQFP CQFP 208-Pin 256-Pin
Package Definitions (Consult your local Actel sales representative product availability.) CQFP Ceramic Quad Flat Pack
Description
CLK, CLKA, CLKB Clock Clock (Input)
QCLKA/B,C,D Quadrant Clock (Input/Output)
Quadrant clock inputs. When used register control signal, these pins function general-purpose I/O.
Serial Data Input (Input)
clock inputs clock distribution networks. clock input buffered prior clocking logic modules. This also used I/O.
DCLK Diagnostic Clock (Input)
Serial data input diagnostic probe device programming. active when MODE HIGH. This functions when MODE LOW.
Test Clock
clock input diagnostic probe device programming. DCLK active when MODE HIGH. This functions when MODE LOW.
Ground (Input)
Clock signal shift JTAG data into device. This functions when JTAG fuse programmed.
Test Data
Input supply voltage.
Input/Output (Input, Output)
Input, output, tri-state, bi-directional buffer. Input output levels compatible with standard CMOS specifications. Unused pins automatically driven Designer Series software.
MODE Mode (Input)
Serial data input JTAG instructions data. Data shifted rising edge TCLK. This functions when JTAG fuse programmed.
Test Data
Serial data output JTAG instructions test data. This functions when JTAG fuse programmed.
Test Mode Select
Controls multifunction pins (DCLK, PRA, PRB, SDI, TDO). provide ActionProbe capability, MODE should held HIGH. facilitate this MODE should terminated through resistor that MODE pulled HIGH when required.
Connection
Serial data input JTAG test mode. Data shifted rising edge TCLK. This functions when JTAG fuse programmed.
Supply Voltage (Input)
Input HIGH supply voltage.
Supply Voltage (Input)
connected circuitry within device.
PRB, Probe (Output)
Input HIGH supply voltage, supplies array core only.
Supply Voltage (Input)
Used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when debugging been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. active when MODE HIGH. This functions when MODE LOW.
PRB, Probe (Output)
Input HIGH supply voltage, supplies cells only.
Power Mode
Controls power mode 42MX devices. This must HIGH switch device power mode. power mode, I/Os tri-stated, input buffers turned OFF, core devices turned OFF. exit power mode, must LOW. This mode enabled nsec after HIGH. Note: TCK, TDI, TDO, available only devices containing JTAG circuitry.
Used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when debugging been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. active when MODE HIGH. This functions when MODE LOW.
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Connecting Devices
40MX
Logic Modules
40MX FPGAs will operate 5.0V only systems 3.3V only systems. 3.3V 5.0V
42MX
40MX logic module eight-input, one-output logic circuit designed implement wide range logic functions with efficient interconnect routing resources (Figure logic module implement four basic logic functions (NAND, AND, NOR) gates two, three, four inputs. Each function have many versions with different combinations active inputs. logic module also implement variety D-latches, exclusivity functions, AND-ORs, OR-ANDs. dedicated hard-wired latches flip-flops required array, since latches flip-flops constructed from logic modules wherever needed application.
Input 3.3V 5.0V
Output 3.3V 5.0V
42MX FPGAs will operate 5.0V only systems, 3.3V only systems, mixed 5.0V/3.3V systems. VCCA 3.3V 5.0V 5.0V VCCI 3.3V 3.3V 5.0V Input 3.3V 3.3V, 5.0V 5.0V Output 3.3V 3.3V 5.0V
Mixed Voltage Power-Up Power-Down
When powering device mixed voltage mode (VCCA 5.0V VCCI 3.3V), VCCA must greater than equal VCCI throughout power-up sequence. VCCI 0.5V greater than VCCA when both above 1.5V, then I/Os input protection junction will forward biased. This causes I/Os draw large amounts current. When VCCA VCCI 2.0V region VCCI greater than VCCA, I/Os would momentarily behave outputs that logical high state rises high levels. power-down sequence with VCCA VCCI implemented.
Architectural Overview
40MX 42MX devices composed fine-grained building blocks that enable fast, efficient logic designs. devices within Integrator Series composed logic modules, routing resources, clock networks, modules, which building blocks designing fast logic designs. addition, subset devices contain embedded dual-port SRAM wide decode modules. dual-port SRAM modules optimized high-speed datapath functions such FIFOs, LIFOs, scratchpad memory. "Integrator Series Product Profile" page lists specific logic resources contained within each device.
Figure 40MX Logic Module
42MX devices contain three types logic modules: combinatorial (C-modules), sequential (S-modules), decode (D-modules). C-module shown Figure implements following function: where S0=A0*B0 S1=A1+B1 S-module shown Figure designed implement high-speed sequential functions within single logic module. S-module implements same combinatorial logic function C-module while adding sequential element. sequential element configured either flip-flop transparent latch. increase flexibility, S-module register bypassed that implements purely combinatorial logic.
Figure C-Module Implementation
GATE
7-Input Function Plus D-Type Flip-Flop with Clear
7-Input Function Plus Latch
GATE
4-Input Function Plus Latch with Clear
8-Input Function Same C-Module)
Figure S-Module Implementation
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Some 42MX devices contain third type logic module, D-modules, which arranged around peripheries devices. D-modules contain wide-decode circuitry, which provides fast, wide-input function similar that found product term architectures (Figure D-module allows 42MX devices perform wide-decode functions speeds comparable CPLDs devices. output D-module programmable inverter active HIGH assertion. D-module output hard-wired output pin, back into array incorporated into other logic.
Dual-Port SRAM Modules
Inputs
Hard-Wire Programmable Inverter
Feedback Array
Several 42MX devices contain dual-port SRAM modules that have been optimized synchronous asynchronous applications. SRAM modules arranged 256-bit blocks that configured 32x8 64x4. (Refer "Integrator Series Product Profile" table, page
Figure D-Module Implementation number SRAM blocks within particular device.) SRAM modules cascaded together form memory spaces user-definable width depth. block diagram 42MX dual-port SRAM block shown Figure
WD[7:0]
Latches [7:0]
[5:0] Write Port Logic SRAM Module (256 Bits) Read Port Logic Latches
RDAD[5:0]
WRAD[5:0] Latches
[5:0]
Read Logic
RCLK
MODE BLKEN WCLK Write Logic RD[7:0]
Routing Tracks
Figure 42MX Dual-Port SRAM Block 42MX SRAM modules true dual-port structures containing independent read write ports. Each SRAM module contains bits read write addressing (RDAD[5:0] WRAD[5:0], respectively) 64x4-bit blocks. When configured byte mode, highest order address bits (RDAD5 WRAD5) used. read write ports SRAM block contain independent clocks (RCLK WCLK) with programmable polarities offering active HIGH implementation. SRAM block contains eight data inputs (WD[7:0]), eight outputs (RD[7:0]) which connected segmented vertical routing tracks. 42MX dual-port SRAM blocks provide optimal solution high-speed buffered applications requiring fast FIFO LIFO queues. Actel's ACTgen Macro Builder provides capability quickly design memory functions, such FIFOs,
LIFOs, arrays. addition, unused SRAM blocks used implement registers other logic within design.
MultiPlex Modules
using C-module register input output signals. achieve 5.0V 3.3V PCI-compliant output drives A42MX24 A42MX36 devices, chip-wide fuse programmed. When fuse programmed, output drive standard. (See bottom portion Figure Actel's Designer Series development tools provide design library macrofunctions that implement configurations supported FPGAs.
Routing Structure
MultiPlex modules provide interface between device pins logic array. Figure block diagram 42MX module. variety user functions, determined library macro selection, implemented module. (Refer Macro Library Guide more information.) 42MX modules contain tri-state buffer, with input output latches that configured input, output, bi-directional operation.
From Array
architecture uses vertical horizontal routing tracks interconnect various logic modules. These routing tracks metal interconnects that either continuous length broken into pieces called segments. Varying segment lengths allows interconnect over design tracks occur with only antifuse connections. Segments joined together ends using antifuses increase their lengths full length track. interconnects accomplished with maximum four antifuses.
Horizontal Routing
G/CLK*
Array
G/CLK*
Configured Latch Flip-Flop (Using C-Module)
Horizontal channels located between rows modules composed several routing tracks. horizontal routing tracks within channel divided into more segments. minimum horizontal segment length width module pair, maximum horizontal segment length full length channel. segment that spans more than one-third length considered long horizontal segment. typical channel shown Figure Non-dedicated horizontal routing tracks used route signal nets; dedicated routing tracks used global clock networks power ground tie-off tracks.
Vertical Routing
Schematic
Signal Output Drive Enable Fuse
Another routing tracks vertically through module. Vertical tracks three types: input, output, long, also divided into more segments. Each segment input track dedicated input particular module; each segment output track dedicated output particular module. Long segments uncommitted assigned during routing. Each output segment spans four channels (two above below), except near bottom array, where edge effects occur. Long vertical tracks contain either segments. example vertical routing tracks segments shown Figure
Antifuse Structures
Figure Module Integrator Series devices contain flexible structures, where each output dedicated output-enable control. module used latch input output data, both, providing fast set-up time. addition, Actel Designer Series software tools build D-type flip-flop
antifuse "normally open" structure opposed normally closed fuse structure used PROMs PALs. antifuses implement programmable logic device results highly-testable structures well efficient programming algorithms. structure highly-testable
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Segmented Horizontal Routing Tracks
Logic Modules
CLKB CLKA From Pads CLKMOD
CLKINB CLKINA Internal Signal CLKO(17)
Antifuses Clock Drivers
CLKO(16) CLKO(15)
Vertical Routing Tracks
Figure Routing Structure because there pre-existing connections; therefore, temporary connections made using pass transistors. These temporary connections isolate individual antifuses programmed individual circuit structures tested, which done before after programming. example, metal tracks tested continuity shorts between adjacent tracks, functionality logic modules verified.
Clock Networks
CLKO(2) CLKO(1)
Clock Tracks
Figure Clock Networks quadrant device. Quadrant clock signals originate from specific pins from internal array used secondary register clock, register clear, output enable.
Test Circuitry
40MX devices have global distribution network. low-skew, high-fanout clock distribution networks provided each 42MX device. These networks referred CLK0 CLK1. Each network clock module (CLKMOD) that selects source clock signal driven follows: Externally from CLKA Externally from CLKB Internally from CLKINA input Internally from CLKINB input clock modules located modules. Clock drivers dedicated horizontal clock track located each horizontal routing channel. user controls clock module selecting clock macros from macro library. macro CLKBUF used connect external clock pins clock network, macro CLKINT used connect internally-generated clock signal clock network. Since both clock networks identical, user does care whether CLK0 CLK1 being used. clock input pads also used normal I/Os, bypassing clock networks. (See Figure 42MX devices that contain SRAM modules have four additional register control resources, called quadrant clock networks (Figure Each quadrant clock provides local, high-fanout resource contiguous logic modules within
Both 40MX 42MX devices provide means test debug design once programmed into device. 40MX 42MX devices contain Actel's test circuitry. Once device been programmed, ActionProbe test circuitry allows designer probe internal node during device operation debugging design. addition, 42MX devices contain IEEE Standard 1149.1 (JTAG) Boundary Scan Test.
JTAG Boundary Scan Testing (BST)
Device spacing decreasing with advent fine-pitch packages such TQFP BGA, manufacturers routinely implementing surface-mount technology with multilayer boards. Joint Test Action Group (JTAG) developed IEEE Standard 1149.1 Boundary Scan Test facilitate board-level testing during manufacturing. IEEE Standard 1149.1 defines four-pin Test Access Port (TAP) interface testing integrated circuits system. 42MX family provides four JTAG pins: Test Data (TDI), Test Data (TDO), Test Clock (TCLK), Test Mode Select (TMS). Devices configured JTAG "chain" where data transmitted serially between devices TDO-to-TDI interconnections. TCLK signals
shared among devices JTAG chain that components operate same state. 42MX family implements subset IEEE Standard 1149.1 instruction addition private instruction, which allows Actel's ActionProbe facility with JTAG BST. Refer IEEE Standard 1149.1 specification detailed information regarding JTAG testing.
JTAG Architecture
42MX JTAG circuitry consist Test Access Port (TAP) controller, JTAG instruction register, JPROBE register, bypass register, boundary scan register. Figure block diagram 42MX JTAG circuitry.
QCLKA Quad Clock Module Quad Clock Module
QCLKC
QCLKB *QCLK1IN
QCLK1
QCLK3
QCLKD *QCLK3IN
Quad Clock Module *QCLK2IN
QCLK2
QCLK4
Quad Clock Module *QCLK4IN
*QCLK1IN, QCLK2IN, QCLK3IN, QCKL4IN internally-generated signals.
Figure Quadrant Clock Network
JPROBE Register Boundary Scan Register Bypass Register Control Logic Output
Controller TCLK Instruction Register
Instruction Decode
Figure JTAG Circuitry
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When device operating JTAG mode, four pins used TDI, TDO, TMS, TCLK signals. active reset (nTRST) supported; however, 42MX contains power-on circuitry that resets JTAG circuitry upon power-up. During normal device operation, JTAG pins should held disable JTAG circuitry. following table summarizes functions JTAG signals.
JTAG Signal Name Test Data Function Serial data input JTAG instructions data. Data shifted rising edge TCLK. Serial data output JTAG instructions test data. Serial data input JTAG test mode. Data shifted rising edge TCLK. Clock signal shift JTAG data into device.
Test Mode EXTEST
Code
Description Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Allows snapshot signals device pins captured examined during device operation. Refer IEEE Standard 1149.1 specification. private instruction allowing user connect Actel's Micro Probe registers JTAG chain. Allows user build application-specific instructions such READ WRITE. Refer IEEE Standard 1149.1 specification. Refer IEEE Standard 1149.1 specification. Enables bypass register between pins. test data passes through selected device adjacent devices JTAG chain.
SAMPLE/ PRELOAD
INTEST JPROBE
Test Data Test Mode Select Test Clock
USER INSTRUCTION
TCLK
HIGH CLAMP BYPASS
JTAG Instructions
JTAG testing within 42MX devices controlled Test Access Port (TAP) state machine. controller drives three-bit instruction register, bypass register, boundary scan data registers within device. controller uses signal control JTAG testing device. JTAG test mode determined bitstream entered pin. table next column describes JTAG instructions supported 42MX.
JTAG Reset
equipped with pull-up resistor. This allows controller remain return Test-Logic-Reset state when there input when logical pin. reset controller, must HIGH least five TCLK cycles.
ActionProbe
device been successfully programmed security fuse been programmed, internal logic module output observed real time using ActionProbe circuitry, and/or pins Actel's Silicon Explorer diagnostic debug tool kit. Refer "Using ActionProbe System-Level Debug" application note further information.
5.0V Operating Conditions Mixed 5.0V/3.3V Operating Conditions Absolute Maximum Ratings1
Free Temperature Range
Recommended Operating Conditions
Parameter Commercial Industrial 4.75 5.25 4.75 5.25 4.75 5.25
Military +125
Units
Symbol Parameter TSTG Supply Voltage Input Voltage Output Voltage Source/Sink Current2 Storage Temperature
Limits -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150
Units
Temperature Range1 Power Supply Tolerance VCCI VCCA VCCI
%VCC
Notes: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Device should operated outside Recommended Operating Conditions. Device inputs normally high impedance draw extremely current. However, when input voltage greater than 0.5V less than 0.5V, internal protection diode will forward-biased draw excessive current.
3.14 3.47
Note: Ambient temperature (TA) used commercial industrial, Case temperature (TC) used military. Operating condition mixed voltage mode.
Electrical Specifications
Commercial Symbol VOH1 Parameter Min. (IOH (IOH (IOH Input Transition Time Capacitance2, Standby Current, ICC4 ICC(D) Dynamic Supply Current Power Mode Standby Current Note
Commercial Min. 3.84 Max.
Industrial Min. Max.
Military Units Min. Max.
Max.
3.84
0.33 -0.3 Note -0.3 0.33 25.0 -0.3 0.40 Note
0.40
(IOL
(IOL
-0.3
"Power Dissipation" page
Notes: Only output tested time. min. tested, information only. Includes worst-case 84-Pin CPGA package capacitance. VOUT MHz. outputs unloaded. inputs GND. limit includes during normal operation. A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 available special request. Contact your local Actel Sales representative additional information. A40MX02 A40MX04 A42MX09, A42MX16, A42MX24, A42MX36 Power Mode, A42MX09 A42MX16, A42MX24, A42MX36 A40MX02 A40MX04 N/A.
40MX 42MX FPGA Families
3.3V Operating Conditions Absolute Maximum Ratings1
Free Temperature Range
Recommended Operating Conditions
Parameter Commerci Industrial Military +125 Units
Symbol TSTG
Parameter Supply Voltage Input Voltage Output Voltage Source Sink Current2 Storage Temperature
Limits -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150
Units Temperature Range1 Power Supply Tolerance VCCI VCCA
Notes: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Device should operated outside Recommended Operating Conditions. Device inputs normally high impedance draw extremely current. However, when input voltage greater than 0.5V less than 0.5V, internal protection diodes will forward-bias draw excessive current.
Note: Ambient temperature (TA) used commercial, industrial, case temperature (TC) used military.
Electrical Specifications
Commercial Parameter Min. VOH1 Input Transition Time Capacitance2,
Industrial Min. Max.
Military Units Min. Max.
Max.
(IOH (IOH -3.2 (IOL
2.15 -0.3 Note
0.48 -0.3 Note "Power Dissipation" page -0.3
0.48
Standby Current,
ICC(D) Dynamic Supply Current Power Mode Standby Current Note
Notes: Only output tested time. min. tested, information only. Includes worst-case 84-Pin PLCC package capacitance. VOUT MHz. outputs unloaded. inputs GND. A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 available special request. Contact your local Actel Sales representative additional information. A40MX02 A40MX04 A42MX09, A42MX16, A42MX24, A42MX36 Power Mode, A42MX09 A42MX16, A42MX24, A42MX36 A40MX02 A40MX04 N/A.
Output Drive Characteristics 5.0V Signaling
device drivers were designed specifically high-performance systems. Figure shows typical output drive characteristics devices. output Table Specification 5.0V Signaling1
drivers compliant Specification.
with
Local
Symbol CCLK LPIN Parameter Supply Voltage Input High Voltage Input Voltage Input High Leakage Current Input Leakage Current Output High Voltage Output Voltage Input Capacitance Capacitance Inductance VIN=0.5 IOUT IOUT 0.55 Condition Minimum 4.75 -0.5 Maximum 5.25 Minimum 4.75 -0.3
Maximum 5.252 Units 0.33
Notes: Local Specification Section 4.2.1.1. Maximum rating -0.5V 7.0V. Dependent upon chosen package. recommends packaging reduce inductance capacitance.
Table Specifications 5.0V Signaling1
Symbol Slew Slew Parameter Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition 0.4V 2.4V load 2.4V 0.4V load Minimum (VIN /0.015 Maximum Minimum Maximum Units V/ns V/ns
Note: Local Specification Section 4.2.1.2.
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Output Drive Characteristics 3.3V Signaling
Table Specification 3.3V Signaling1
Symbol CCLK LPIN Parameter Supply Voltage Input High Voltage Input Voltage Input High Leakage Current Input Leakage Current Output High Voltage Output Voltage Input Capacitance Capacitance Inductance IOUT IOUT Condition Minimum -0.5 Maximum 0.33 Minimum -0.3 Maximum Units
Notes: Local Specification Section 4.2.2.1. Maximum rating -0.5V 7.0V. Dependent upon chosen package. recommends packaging reduce inductance capacitance.
Table Specifications 3.3V Signaling1
Symbol Slew Slew Parameter Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition 0.2V 0.6V load 0.6V 0.2V load Minimum (VIN /0.015 Maximum Minimum Maximum Units V/ns V/ns
Note: Local Specification Section 4.2.2.2.
0.50 0.45 0.40 0.35 0.30 0.25 0.20 Current 0.15 0.10
Maximum
Minimum
0.05 0.00
-0.05 -0.10 -0.15 -0.20
Maximum
Minimum
Voltage
Figure Typical Output Drive Characteristics (Based upon measured data)
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Package Thermal Characteristics
device junction-to-case thermal characteristic junction-to-ambient characteristic thermal characteristics shown with different flow rates.
Maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed PQFP 160-pin package commercial temperature follows:
150°C 70°C Max. junction temp. (°C) Max. commercial temp. 2.5W 32°C/W (°C/W) Plastic Packages Count Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Plastic Quad Flat Pack Ball Grid Array Still 34°C/W 32°C/W 20°C/W 43°C/W 36°C/W 32°C/W 28°C/W 39°C/W 38°C/W 19°C/W 20°C/W 6.7°C/W 6.2°C/W ft/min 31°C/W 24°C/W 17°C/W 31°C/W 25°C/W 22°C/W 21°C/W 33°C/W 32°C/W 16°C/W 14.5°C/W Still 32°C/W 27°C/W Still ft/min Maximum Power Dissipation
Ceramic Packages Ceramic Quad Flat Pack Ceramic Quad Flat Pack
Count
Power Dissipation
General Power Equation
Static Power Component
[ICCstandby ICCactive] IOL* VOL* (VCC VOH) where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH. accurate determination problematic because their values depend family type, design details, system I/O. power divided into components: static active.
Actel FPGAs have small static power components that result power dissipation lower than PALs PLDs. integrating multiple PALs/PLDs into FPGA, even greater reduction board-level power dissipation achieved. power standby current typically small component overall power. Standby power calculated commercial, worst-case conditions: 5.25 Power 10.5
static power dissipation loads depends number outputs driving HIGH LOW, load current. Again, this number typically small. instance, 32-bit sinking 0.33V will generate with outputs driving LOW, with outputs driving HIGH. actual dissipation will average somewhere between, I/Os switch states with time.
Active Power Component
where: CEQI Number logic modules switching frequency Number input buffers switching frequency Number output buffers switching frequency Number clock loads first routed array clock Number clock loads second routed array clock Fixed capacitance first routed array clock Fixed capacitance second routed array clock Equivalent capacitance input buffers
Power dissipation CMOS devices usually dominated active (dynamic) power dissipation. This component frequency-dependent, function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitance board traces load device inputs. additional component active power dissipation totem pole current CMOS transistor pairs. effect associated with equivalent capacitance that combined with frequency voltage represent active power dissipation.
Equivalent Capacitance
CEQM Equivalent capacitance logic modules CEQO Equivalent capacitance output buffers CEQCR Equivalent capacitance routed array clock Output load capacitance Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate
power dissipated CMOS circuit expressed Equation Power (µW) VCC2 where:
equivalent capacitance expressed picofarads (pF). power supply volts (V). switching frequency megahertz (MHz).
Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements have been made over range frequencies fixed value VCC. Equivalent capacitance frequency-independent, results used over wide range operating conditions. Equivalent capacitance values shown below.
Values Actel FPGAs
Fixed Capacitance Values Actel FPGAs (pF)
Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR)
18.2
Device Type A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36
routed_Clk1 41.4 68.6
routed_Clk2
calculate active power dissipated from complete design, switching frequency each part logic must known. Equation shows piece-wise linear summation over components. Power VCC2 CEQM fm)Modules CEQI fn)Inputs (CEQO fp)outputs CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR fq2)routed_Clk2 fq2)routed_Clk2
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Determining Average Switching Frequency
Logic Modules
determine switching frequency design, must have detailed understanding data input values circuit. following guidelines represent worst-case scenarios; these used generally predict upper limits power dissipation. Logic Modules Combinatorial Modules Inputs/4 Outputs/4
Combinatorial Modules F/10
Load Capacitance (CL) Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average First Routed Array Clock Rate (fq1)
Average Output Switching Rate (fp) F/10
Inputs Switching Outputs Switching
First Routed Array Clock Loads (q1) Sequential Modules Second Routed Array Clock Loads (q2) Sequential Modules
Average Second Routed Array Clock Rate (fq2)
40MX Timing Model*
Input Delay Module tINYL 0.62 IRD2 2.59
Internal Delays
Predicted Routing Delays
Output Delay Module
Logic Module tDLH 3.32 tIRD1 2.09 tIRD4 3.64 tIRD8 5.73 1.24 1.24 tRD1 1.28 tRD2 1.80 tRD4 2.33 tRD8 4.93 tENHZ 7.92
Array Clock
tCKH 4.55 FMAX
Values shown 40MX speed' devices 5.0V worst-case commercial conditions.
42MX Timing Model*
Input Delays Module tINYL 1.16 tIRD1 2.24
Internal Delays
Predicted Routing Delays
Output Delays Module
Combinatorial Logic Module 1.55 tRD1 0.80 tRD2 1.00 tRD4 1.50 tRD8 2.50
tDLH 2.70
tINH 0.00 tINSU 0.54 tINGL 1.40 Sequential Logic Module
Combinatorial Logic included tSUD
Module tDLH 2.70
tRD1 0.80
tENHZ 5.40
tOUTH 0.00 tOUTSU 0.30 tGLH 2.90
Array Clocks
tCKH 2.70 FMAX
tSUD 0.36 0.00
1.37
tLCO 5.60 (light loads, pad-to-pad)
*Values shown A42MX09-2 5.0V worst-case commercial conditions
Input module predicted routing delay
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42MX Timing Model (Logic Functions using Quadrant Clocks)*
Input Delays Module tINPY 1.14 IRD1 2.18
Internal Delays
Predicted Routing Delays
Output Delays Module
Combinatorial Module 1.46 tRD1 1.04 tRD2 1.42 tRD4 2.18
tDLH 2.84
tINH 0.00 tINSU 0.53 tINGO 1.55 Decode Module tPDD 1.78 Module tDLH 2.84
tRDD 0.38
Sequential Logic Module
Combinatorial Logic included tSUD
tRD1 1.04
tENHZ 5.80
0.00 tLSU 0.53 tGHL= 3.27
tSUD 0.30 0.00 Quadrant Clocks tCKH 3.03 ns** FMAX
1.43
Preliminary values shown A42MX36-2 5.0V worst-case commercial conditions Load-dependent
42MX Timing Model (SRAM Functions)*
Input Delays Module tINPY 1.14 IRD1 2.18
tINSU 0.53 tINH 0.00 tINGO 1.55
Predicted Routing Delays [7:0] WRAD [5:0] BLKEN WCLK tADSU 1.80 tADH 0.00 tWENSU 2.90 tBENS 2.90 [7:0] RDAD [5:0] tRD1 1.04
Module tDLH 2.84
RCLK tADSU 1.80 tADH 0.00 tRENSU 0.80 tRCO 3.80
tGHL= 5.50 tLSU 0.30 0.00
Array Clocks FMAX
*Values shown A42MX36-2 5.0V worst-case commercial conditions.
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Parameter Measurement
Output Buffer Delays
TRIBUFF test loads (shown below)
1.5V 1.5V
1.5V tENLZ
1.5V tENHZ
tDLH
tDHL
tENZL
tENZH
Test Loads
Load (Used measure propagation delay)
Load (Used measure rising/falling edges)
output under test
output under test
tPLZ/tPZL tPHZ/tPZH
Input Buffer Delays
Module Delays
INBUF
tINYH 1.5V 1.5V tINYL
tPLH tPHL tPLH
tPHL
Sequential Module Timing Characteristics
Flip-Flops Latches
(Positive Edge-Triggered)
tSUD tSUENA tHENA PRE, tWASYN tWCLKI tWCLKA
Note:
represents data functions involving multiplexed flip-flops.
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Sequential Timing Characteristics (continued)
Input Buffer Latches
DATA
IBDL
CLKBUF
DATA tINH tINSU tHEXT tSUEXT
Output Buffer Latches
OBDLHS
tOUTSU tOUTH
Decode Module Timing
A-G, tPHL tPLH
SRAM Timing Characteristics
Write Port WRAD [5:0] BLKEN WCLK [7:0] Array 32x8 64x4 (256 Bits)
Read Port RDAD [5:0] RCLK [7:0]
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Dual-Port SRAM Timing Waveforms
42MX SRAM Write Operation
tRCKHL WCLK tADSU WD[7:0] WRAD[5:0] Valid tWENSU tBENSU BLKEN Valid tBENH tWENH tADH
tRCKHL
Note:
Identical timing falling edge clock.
42MX SRAM Synchronous Read Operation
tCKHL RCLK
tRCKHL
tRENSU tADSU RDAD[5:0] Valid
tRENH
tADH
tRCO tDOH RD[7:0] Data Data
Note:
Identical timing falling edge clock.
42MX SRAM Asynchronous Read Operation-Type
(Read Address Controlled)
tRDADV RDAD[5:0] ADDR1 tDOH RD[7:0] Data ADDR2 tRPD Data
42MX SRAM Asynchronous Read Operation-Type
(Write Address Controlled)
tWENSU
tWENH
WD[7:0] WRAD[5:0] BLKEN
Valid tADSU tADH tRPD tDOH
WCLK
RD[7:0]
Data
Data
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Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends resistive capacitive loading routing tracks, interconnect elements, module inputs being driven. Propagation delay increases length routing tracks, number interconnect elements, number inputs increases. From design perspective, propagation delay statistically correlated modeled fanout (number loads) driven module. Higher fanout usually requires some paths have longer routing tracks. FPGAs deliver tight fanout delay distribution. This tight distribution achieved ways: decreasing delay interconnect elements decreasing number interconnect elements path. Actel's patented PLICE antifuse offers very resistive/capacitive interconnect. antifuses, fabricated 0.45 micron lithography, offer nominal levels ohms resistance femtofarad (fF) capacitance antifuse. Integrator Series fanout distribution also tight number antifuses required each interconnect path. proprietary architecture limits number antifuses path maximum four, with interconnects using antifuses.
Timing Characteristics
determined until after place route user's design complete. Delay values then determined using Designer Series utility performing simulation with post-layout delays.
Critical Nets Typical Nets
Propagation delays this data sheet apply typical nets. abundant routing resources architecture allows deterministic timing using Actel's Designer Series development tools which include DirectTime, timing-driven place-and-route tool. Using DirectTime, designer specify timing-critical nets system clock frequency. Using these timing specifications, place-and-route software optimizes layout design meet user's specifications.
Long Tracks
Some nets design long tracks which special routing resources that span multiple rows, columns, modules. Long tracks employ three sometimes four antifuse connections, which increase capacitance resistance, resulting longer delays macros connected long tracks. Typically, nets fully utilized device require long tracks. Long tracks approximately delay, which represented statistically higher fanout (FO=8) routing delays data sheet specifications section.
Timing Derating
Timing characteristics devices fall into three categories: family-dependent, device-dependent, design-dependent. input output buffer characteristics common Integrator Series members. Internal routing delays device-dependent. Design dependency means actual delays
timing derating factor 0.45 used reflect best-case processing. Note that this factor relative standard speed timing parameters, must multiplied appropriate voltage temperature derating factors given application.
Timing Derating Factor (Tem perature Voltage)
Industrial Min. (Commercial Specification) 0.69 Max. 1.11
Timing Derating Factor Designs Typical Temperature 25°C) Voltage (5.0V)
(Maximum Specification, Worst-Case Condition) 0.85
Note:
This derating factor applies routing propagation delays.
42MX Temperature Voltage Derating Factors (Normalized 25°C)
42MX 4.50 4.75 5.00 5.25 5.50 0.93 0.88 0.85 0.84 0.83 0.95 0.90 0.87 0.86 0.85 1.05 1.00 0.96 0.95 0.94 1.09 1.03 1.00 0.97 0.96 1.25 1.18 1.15 1.12 1.10 1.29 1.22 1.18 1.14 1.13 1.41 1.34 1.29 1.28 1.26
42MX Junction Temperature Voltage Derating Curves (Normalized 25°C)
1.50 1.40 1.30
Derating Factor
1.20 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00
Voltage
-55°C -40°C 25°C 70°C 85°C 125°C 5.25 5.50
Note:
This derating factor applies routing propagation delays.
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40MX Temperature Voltage Derating Factors (Normalized 25°C)
40MX 4.50 4.75 5.00 5.25 5.50 0.89 0.84 0.82 0.80 0.79 0.93 0.88 0.85 0.82 0.82 1.02 0.97 0.94 0.91 0.90 1.09 1.03 1.00 0.97 0.96 1.25 1.18 1.15 1.12 1.10 1.31 1.24 1.20 1.16 1.15 1.45 1.37 1.33 1.29 1.28
40MX Junction Temperature Voltage Derating Curves (Normalized 25°C)
1.50 1.40 1.30
Derating Factor
1.20 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00
Voltage
-55°C -40°C 25°C 70°C 85°C 125°C 5.25 5.50
Note:
This derating factor applies routing propagation delays.
System Timing Specification
Models
Tables list critical timing parameters corresponding timing parameter PCI-compliant devices. Table Clock Specification
Actel provides synthesizable VHDL Verilog-HDL models target interface, Target Target+DMA Master interface. Consult your local Actel sales representative more details.
Symbol TCYC THIGH TLOW Parameter Cycle Time High Time Time Min. Max.
A42MX24 Min. Max.
A42MX36 Min. Max. Units
Table Timing Parameters
Symbol TVAL TVAL(PTP) TOFF TSU(PTP) Parameter Signal Valid-Bused Signals Signal Valid-Point-to-Point Float active Active Float Input Set-Up Time CLK-Bused Signals Input Set-Up Time CLK-Point-to-Point Input Hold Min. Max. A42MX24 Min. Max. 8.31 A42MX36 Min. Max. 8.31 Units
Notes: TOFF system dependent. devices have turn-off time, reflection typically additional
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A40MX02 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
Logic Module Propagation Delays Parameter Description tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1 1.28 1.80 2.33 2.85 4.93 1.48 2.08 2.69 3.29 5.69 1.67 2.35 3.04 3.72 6.45 1.97 2.77 3.58 4.38 7.59 2.76 3.88 5.01 6.13 10.63 `-3' Speed Min. Max. 1.24 2.65 1.24 1.24 1.24 `-2' Speed Min. Max. 1.43 3.06 1.43 1.43 1.43 `-1' Speed Min. Max. 1.63 3.47 1.62 1.62 1.62 `Std' Speed Min. Max. 1.90 4.08 1.90 1.90 1.90 `-F' Speed Min. Max. Units 2.66 5.71 2.66 2.66 2.66
Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Sequential Timing Characteristics tSUD2
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
3.06 0.00 3.06 0.00 3.25 3.25 4.84 180.90
3.53 0.00 3.53 0.00 3.75 3.75 5.59 167.50
4.00 0.00 4.00 0.00 4.25 4.25 6.33 154.10
4.70 0.00 4.70 0.00 5.00 5.00 7.45 134.00
6.58 0.00 6.58 0.00 7.00 7.00 10.43 80.40
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Set-up times assume fanout Further testing information obtained from DirectTime Analyzer utility. hold time DFME1A macro greater than Designer later DirectTime Analyzer check hold time this macro.
A40MX02 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter Description tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays 2.07 2.59 3.12 3.64 5.73 2.39 2.99 3.60 4.20 6.62 2.17 3.39 4.08 4.76 7.50 3.19 3.99 4.80 5.60 8.82 4.47 5.59 6.72 7.84 12.35 `-3' Speed Min. Max. 0.70 0.62 `-2' Speed Min. Max. 0.80 0.71 `-1' Speed Min. Max. 0.91 0.81 `Std' Speed Min. Max. 1.07 0.95 `-F' Speed Min. Max. Units 1.50 1.33
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input High 2.24 2.35 2.24 2.35 0.39 0.53 4.67 4.84 187.60 180.90 5.39 5.59 174.79 167.50 4.55 4.55 4.81 4.81 2.58 2.71 2.58 2.71 0.45 0.62 6.10 6.33 159.85 154.10 5.25 5.25 5.55 5.55 2.92 3.07 2.92 3.07 0.51 0.70 7.18 7.45 139.00 134.00 5.95 5.95 6.29 6.29 3.44 3.61 3.44 3.61 0.60 0.82 10.05 10.43 83.40 80.40 7.00 7.00 7.40 7.40 4.82 5.05 4.82 5.05 0.84 1.15 9.80 9.80 10.36 10.36
Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
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A40MX02 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Module Timing1 3.93 3.39 3.37 4.88 7.92 5.86 0.03 0.02 4.54 3.92 3.89 5.63 9.14 6.77 0.04 0.02 5.14 4.44 4.41 6.38 10.35 7.67 0.04 0.03 6.05 5.22 5.19 7.51 12.18 9.02 0.05 0.03 8.47 7.31 7.27 10.51 17.05 12.63 0.07 0.04 ns/pF ns/pF 3.32 3.98 3.74 4.69 7.92 5.86 0.02 0.03 3.83 4.60 4.31 5.41 9.14 6.77 0.02 0.03 4.34 5.21 4.89 6.13 10.35 7.67 0.03 0.03 5.11 6.13 5.75 7.21 12.18 9.02 0.03 0.04 7.15 8.58 8.05 10.09 17.05 12.63 0.04 0.06 ns/pF ns/pF `-3' Speed Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Notes: Delays based loading.
A40MX02 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
Logic Module Propagation Delays Parameter Description tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1 1.93 2.66 3.39 4.12 7.05 2.23 3.07 3.92 4.76 8.14 2.52 3.47 4.44 5.39 9.22 2.97 4.09 5.22 6.34 10.85 4.16 5.72 7.31 8.88 15.19 `-3' Speed Min. Max. 1.73 3.71 1.73 1.73 1.73 `-2' Speed Min. Max. 2.00 4.28 2.00 2.00 2.00 `-1' Speed Min. Max. 2.26 4.86 2.26 2.26 2.26 `Std' Speed Min. Max. 2.66 5.71 2.66 2.66 2.66 `-F' Speed Min. Max. Units 3.72 8.00 3.72 3.72 3.72
Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics2 4.28 0.00 4.28 0.00 4.55 4.55 6.78
Sequential Timing tSUD
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
4.94 0.00 4.94 0.00 5.25 5.25 7.82 108.54 100.50
5.59 0.00 5.59 0.00 5.95 5.95 8.87 92.46
6.58 0.00 6.58 0.00 7.00 7.00 10.43 80.40
9.21 0.00 9.21 0.00 9.80 9.80 14.60 48.24
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Set-up times assume fanout Further testing information obtained from DirectTime Analyzer utility. hold time DFME1A macro greater than Designer later DirectTime Analyzer check hold time this macro.
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A40MX02 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter Description tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays 2.90 3.63 4.37 5.10 8.03 3.35 4.19 5.04 5.88 9.26 3.80 4.75 5.71 6.66 10.50 4.47 5.59 6.72 7.84 12.35 6.25 7.82 9.41 10.98 17.29 `-3' Speed Min. Max. 0.97 0.86 `-2' Speed Min. Max. 1.12 1.00 `-1' Speed Min. Max. 1.27 1.13 `Std' Speed Min. Max. 1.50 1.33 `-F' Speed Min. Max. Units 2.10 1.86
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 6.53 6.78 112.60 108.54 3.13 3.29 3.13 3.29 0.55 0.75 7.54 7.82 104.88 100.50 6.37 6.37 6.73 6.73 3.61 3.79 3.61 3.79 0.63 0.86 8.54 8.87 95.91 92.46 7.35 7.35 7.77 7.77 4.09 4.30 4.09 4.30 0.71 0.98 10.05 10.43 83.40 80.40 8.33 8.33 8.81 8.81 4.82 5.05 4.82 5.05 0.84 1.15 14.07 14.60 50.04 48.24 9.80 9.80 10.36 10.36 6.74 7.08 6.74 7.08 1.18 1.61 13.72 13.72 14.50 14.50
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
A40MX02 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Module Timing1 5.51 4.75 4.72 6.83 11.08 8.21 0.05 0.03 6.35 5.48 5.45 7.89 12.79 9.47 0.05 0.03 7.20 6.21 6.18 8.94 14.49 10.73 0.06 0.04 8.47 7.31 7.27 10.51 17.05 12.63 0.07 0.04 11.86 10.23 10.17 14.72 23.87 17.68 0.10 0.06 ns/pF ns/pF 4.65 5.58 5.23 6.56 11.08 8.21 0.03 0.04 5.36 6.44 6.04 7.57 12.79 9.47 0.03 0.04 6.08 7.29 6.84 8.58 14.49 10.73 0.04 0.05 7.15 8.58 8.05 10.09 17.05 12.63 0.04 0.06 10.02 12.01 11.27 14.13 23.87 17.68 0.06 0.08 ns/pF ns/pF `-3' Speed Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Notes: Delays based loading.
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A40MX04 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
Logic Module Propagation Delays Parameter Description tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1 1.17 1.90 2.42 2.94 5.04 1.59 2.19 2.80 3.40 5.81 1.80 2.48 3.17 3.85 6.59 2.12 2.92 3.73 4.53 7.75 2.97 4.09 5.22 6.34 10.85 `-3' Speed Min. Max. 1.24 2.25 1.24 1.24 1.24 `-2' Speed Min. Max. 1.43 3.06 1.43 1.43 1.43 `-1' Speed Min. Max. 1.62 3.47 1.62 1.62 1.62 `Std' Speed Min. Max. 1.90 4.08 1.90 1.90 1.90 `-F' Speed Min. Max. Units 2.66 5.71 2.66 2.66 2.66
Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Sequential Timing Characteristics tSUD2
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
3.06 0.00 3.06 0.00 3.25 3.25 4.84 180.90
3.53 0.00 3.53 0.00 3.75 3.75 5.59 167.00
4.00 0.00 4.00 0.00 4.25 4.25 6.33 154.10
4.70 0.00 4.70 0.00 5.00 5.00 7.45 134.00
6.58 0.00 6.58 0.00 7.00 7.00 10.43 80.40
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Set-up times assume fanout Further testing information obtained from DirectTime Analyzer utility. hold time DFME1A macro greater than Designer later DirectTime Analyzer check hold time this macro.
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter Description tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays 2.07 2.59 3.12 3.64 5.73 2.39 2.99 3.60 4.20 6.62 2.17 3.39 4.08 4.76 7.50 3.19 3.99 4.80 5.60 8.82 4.47 5.59 6.72 7.84 12.35 `-3' Speed Min. Max. 0.70 0.62 `-2' Speed Min. Max. 0.80 0.71 `-1' Speed Min. Max. 0.91 0.81 `Std' Speed Min. Max. 1.07 0.95 `-F' Speed Min. Max. Units 1.50 1.33
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH 2.24 2.35 2.24 2.35 0.39 0.53 4.69 4.84 187.68 180.90 5.39 5.59 174.79 167.50 4.58 4.58 4.84 4.84 2.58 2.71 2.58 2.71 0.45 0.62 6.10 6.33 159.85 154.10 5.29 5.29 5.59 5.59 2.92 3.07 2.92 3.07 0.51 0.70 7.18 7.45 139.00 134.00 5.99 5.99 6.33 6.33 3.44 3.61 3.44 3.61 0.60 0.82 10.05 10.43 83.40 80.40 7.05 7.05 7.45 7.45 4.82 5.05 4.82 5.05 0.84 1.15 9.87 9.87 10.43 10.43
Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
Fami
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Module Timing1 3.93 3.39 3.37 4.88 7.92 4.98 0.03 0.02 4.54 3.92 3.89 5.63 9.14 6.77 0.04 0.02 5.14 4.44 4.41 6.38 10.35 7.67 0.04 0.03 6.05 5.22 5.19 7.51 12.18 9.02 0.05 0.03 8.47 7.31 7.27 10.51 17.05 12.63 0.07 0.04 ns/pF ns/pF 3.32 3.98 3.74 4.69 7.92 5.86 0.02 0.02 3.83 4.60 4.31 5.41 9.14 6.77 0.02 0.03 4.34 5.21 4.89 6.13 10.35 7.67 0.03 0.03 5.11 6.13 5.75 7.21 12.18 9.02 0.03 0.04 7.15 8.58 8.05 10.09 17.05 12.63 0.04 0.06 ns/pF ns/pF `-3' Speed Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Notes: Delays based loading.
A40MX04 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
Logic Module Propagation Delays Parameter Description tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1 1.93 2.66 3.39 4.12 7.05 2.23 3.07 3.92 4.76 8.14 2.52 3.47 4.44 5.39 9.22 2.97 4.09 5.22 6.34 10.85 4.16 5.72 7.31 8.88 15.19 `-3' Speed Min. Max. 1.73 3.71 1.73 1.73 1.73 `-2' Speed Min. Max. 2.00 4.28 2.00 2.00 2.00 `-1' Speed Min. Max. 2.26 4.86 2.26 2.26 2.26 `Std' Speed Min. Max. 2.66 5.71 2.66 2.66 2.66 `-F' Speed Min. Max. Units 3.72 8.00 3.72 3.72 3.72
Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics2 4.28 0.00 4.28 0.00 4.55 4.55 6.78
Sequential Timing tSUD
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
4.94 0.00 4.94 0.00 5.25 5.25 7.82 108.54 100.50
5.59 0.00 5.59 0.00 5.95 5.95 8.87 92.46
6.58 0.00 6.58 0.00 7.00 7.00 10.43 80.40
9.21 0.00 9.21 0.00 9.80 9.80 14.60 48.24
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Set-up times assume fanout Further testing information obtained from DirectTime Analyzer utility. hold time DFME1A macro greater than Designer later DirectTime Analyzer check hold time this macro.
Fami
A40MX04 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter Description tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays 2.90 3.63 4.37 5.10 8.03 3.35 4.19 5.04 5.88 9.26 3.80 4.75 5.71 6.66 10.50 4.47 5.59 6.72 7.84 12.35 6.25 7.82 9.41 10.98 17.29 `-3' Speed Min. Max. 0.97 0.86 `-2' Speed Min. Max. 1.12 1.00 `-1' Speed Min. Max. 1.27 1.13 `Std' Speed Min. Max. 1.50 1.33 `-F' Speed Min. Max. Units 2.10 1.86
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 6.53 6.78 112.50 108.54 3.13 3.29 3.13 3.29 0.55 0.75 7.54 7.82 104.88 100.50 6.42 6.42 6.78 6.78 3.61 3.79 3.61 3.79 0.63 0.86 8.54 8.87 95.91 92.46 7.40 7.40 7.82 7.82 4.09 4.30 4.09 4.30 0.71 0.98 10.05 10.43 83.40 80.40 8.39 8.39 8.87 8.87 4.82 5.05 4.82 5.05 0.84 1.15 14.07 14.60 50.04 48.24 9.87 9.87 10.43 10.43 6.74 7.08 6.74 7.08 1.18 1.61 13.82 13.82 14.60 14.60
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
A40MX04 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Module Timing1 5.51 4.75 4.72 6.83 11.08 8.21 0.05 0.03 6.35 5.48 5.45 7.89 12.79 9.47 0.05 0.03 7.20 6.21 6.18 8.94 14.49 10.73 0.06 0.04 8.47 7.31 7.27 10.51 17.05 12.63 0.07 0.04 11.86 10.23 10.17 14.72 23.87 17.68 0.10 0.06 ns/pF ns/pF 4.65 5.58 5.23 6.56 11.08 8.21 0.03 0.04 5.37 6.44 6.04 7.57 12.79 9.47 0.03 0.04 6.08 7.29 6.84 8.58 14.49 10.73 0.04 0.05 7.15 8.58 8.05 10.09 17.05 12.63 0.04 0.06 10.02 12.01 11.27 14.13 23.87 17.68 0.06 0.08 ns/pF ns/pF `-3' Speed Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Notes: Delays based loading.
Fami
A42MX09 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
Logic Module Propagation Delays1 Parameter tPD1 Description Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q `-2' Speed Min. Max. 1.33 1.43 1.37 1.58 `-1' Speed Min. Max. 1.50 1.62 1.55 1.79 `Std' Speed Min. Max. 1.77 1.91 1.82 2.10 `-F' Speed Min. Max. 2.48 2.67 2.55 2.94 Units
Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics3, 0.36 0.00 0.45 0.00 3.77 4.94 3.83 0.00 0.30 0.00 0.30 243.75 0.41 0.00 0.51 0.00 4.27 5.59 4.34 0.00 0.40 0.00 0.40 224.25 0.48 0.00 0.60 0.00 5.02 6.58 5.10 0.00 0.40 0.00 0.40 195.00 0.67 0.00 0.84 0.00 7.03 9.21 7.14 0.00 0.60 0.00 0.60 117.00 0.77 1.02 1.28 1.53 2.60 0.87 1.16 1.45 1.73 2.90 1.02 1.36 1.70 2.04 3.41 1.43 1.90 2.38 2.86 4.77
Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter tINYH tINYL tINGH tINGL Description Pad-to-Y HIGH Pad-to-Y HIGH Delays 2.24 2.51 2.78 3.05 4.13 2.54 2.85 3.15 3.46 4.68 2.99 3.35 3.71 4.07 5.50 4.19 4.69 5.19 5.70 7.70 `-2' Speed Min. Max. 1.16 0.90 1.43 1.43 `-1' Speed Min. Max. 1.32 1.02 1.62 1.62 `Std' Speed Min. Max. 1.55 1.20 1.90 1.90 `-F' Speed Min. Max. 2.17 1.68 2.66 2.66 Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency 0.00 0.00 2.60 2.43 3.72 4.10 268.75 243.75 1.35 1.46 1.35 1.46 0.34 0.34 0.00 0.00 3.00 3.30 4.04 4.46 247.25 224.25 2.70 3.00 3.92 4.30 1.53 1.66 1.53 1.66 0.38 0.38 0.00 0.00 3.50 3.90 4.65 5.13 215.00 195.00 3.04 3.35 4.44 4.87 1.80 1.95 1.80 1.95 0.45 0.45 0.00 0.00 4.90 5.46 7.75 8.55 129.00 117.00 3.62 4.00 5.22 5.73 2.52 2.73 2.52 2.73 0.63 0.63 5.04 5.50 7.31 8.02
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst case performance
Fami
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH Module Timing1 Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH 0.54 0.00 5.78 8.18 0.03 0.04 2.71 3.19 2.93 3.24 5.44 5.93 4.61 4.61 0.61 0.00 6.55 9.27 0.03 0.04 3.07 3.61 3.32 3.67 6.16 6.72 5.22 5.22 0.72 0.00 7.70 10.90 0.04 0.05 3.61 4.25 3.90 4.32 7.25 7.90 6.14 6.14 1.01 0.00 10.78 15.26 0.06 0.07 5.05 5.95 5.46 6.05 10.15 11.06 8.60 8.60 ns/pF ns/pF 0.54 0.00 5.78 8.18 0.03 0.04 2.71 3.19 2.93 3.24 5.44 5.93 2.90 2.90 0.61 0.00 6.55 9.27 0.03 0.04 3.07 3.61 3.32 3.67 6.16 6.72 3.30 3.30 0.72 0.00 7.70 10.90 0.04 0.05 3.61 4.25 3.90 4.32 7.25 7.90 3.78 3.78 1.01 0.00 10.78 15.26 0.06 0.07 5.05 5.95 5.46 6.05 10.15 11.06 5.30 5.30 ns/pF ns/pF
Notes: Delays based loading.
A42MX09 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
Logic Module Propagation Delays1 Parameter tPD1 Description Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q `-2' Speed Min. Max. 1.80 2.00 1.88 2.18 `-1' Speed Min. Max. 2.13 2.30 2.13 2.47 `Std' Speed Min. Max. 2.50 2.70 2.50 2.90 `-F' Speed Min. Max. 3.47 3.76 3.50 4.06 Units
Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics3, 0.50 0.00 0.63 0.00 5.27 6.91 5.60 0.00 0.30 0.00 0.30 146.30 0.57 0.00 0.71 0.00 5.97 7.83 6.20 0.00 0.34 0.00 0.34 134.60 0.67 0.00 0.84 0.00 7.03 9.21 7.10 0.00 0.40 0.00 0.40 117.00 0.94 0.00 1.18 0.00 9.84 12.90 9.94 0.00 0.56 0.00 0.56 70.20 1.10 1.40 1.80 2.10 3.60 1.20 1.60 2.00 2.40 4.10 1.40 1.90 2.40 2.90 4.80 2.00 2.67 3.33 4.00 6.68
Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
Notes:
dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate.
Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
Fami
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter tINYH tINYL tINGH tINGL Description Pad-to-Y HIGH Pad-to-Y HIGH Delays 3.15 3.50 3.90 4.30 5.80 3.57 4.00 4.40 4.85 6.55 4.20 4.70 5.20 5.70 7.70 5.86 6.57 7.27 7.98 10.78 `-2' Speed Min. Max. 1.63 1.30 2.00 2.00 `-1' Speed Min. Max. 1.84 1.40 2.30 2.30 `Std' Speed Min. Max. 2.17 1.70 2.70 2.70 `-F' Speed Min. Max. 3.04 2.40 3.72 3.72 Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency 0.00 0.00 3.70 4.10 6.20 6.80 161.30 146.30 1.89 2.05 1.89 2.05 0.47 0.47 0.00 0.00 4.20 4.60 6.74 7.43 148.40 134.60 4.50 5.00 5.50 6.00 2.14 2.32 2.14 2.32 0.54 0.54 0.00 0.00 4.90 5.50 7.75 8.54 129.00 117.00 5.06 5.63 6.20 6.80 2.52 2.73 2.52 2.73 0.63 0.63 0.00 0.00 6.86 7.64 12.90 14.20 77.40 70.20 6.03 6.70 7.30 8.00 3.53 3.82 3.53 3.82 0.88 0.88 8.40 9.33 10.23 11.23
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst case performance
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH Module Timing1 3.80 4.50 4.10 4.54 7.61 8.30 6.45 6.45 0.76 0.00 9.70 13.50 0.04 0.05 0.86 0.00 10.90 15.40 0.05 0.06 5.45 4.22 4.64 5.14 8.63 9.40 7.31 7.31 1.01 0.00 12.90 18.10 0.06 0.07 6.41 4.97 5.46 6.05 10.15 11.06 8.60 8.60 1.41 0.00 18.03 25.30 0.08 0.10 8.98 6.96 7.64 8.47 14.21 15.48 12.03 12.03 ns/pF ns/pF 0.76 0.00 9.70 13.50 0.00 0.10 3.79 4.46 4.10 4.54 7.61 8.30 6.45 6.45 0.86 0.00 10.90 15.40 0.00 0.10 4.30 5.06 4.64 5.14 8.63 9.40 7.31 7.31 1.01 0.00 12.90 18.10 0.10 0.10 5.05 5.95 5.46 6.05 10.15 11.06 8.60 8.60 1.41 0.00 18.03 25.30 0.008 0.100 7.08 8.33 7.64 8.47 14.21 15.48 12.03 12.03 ns/pF ns/pF
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
Notes: Delays based loading.
Fami
A42MX16 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
Logic Module Propagation Delays1 Parameter tPD1 Description Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q `-2' Speed Min. Max. 1.52 1.60 1.52 1.74 `-1' Speed Min. Max. 1.73 1.81 1.73 1.97 `Std' Speed Min. Max. 2.03 2.13 2.03 2.32 `-F' Speed Min. Max. 2.84 2.98 2.84 3.25 Units
Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics3,4 0.36 0.00 0.75 0.00 3.78 4.95 7.56 0.00 0.54 0.00 0.54 195.00 0.41 0.00 0.85 0.00 4.28 5.61 8.57 0.00 0.61 0.00 0.61 179.40 0.48 0.00 1.00 0.00 5.04 6.60 10.08 0.00 0.72 0.00 0.72 156.00 0.67 0.00 1.40 0.00 7.06 9.24 14.11 0.00 1.01 0.00 1.01 93.60 0.86 1.15 1.43 1.72 2.86 0.98 1.30 1.62 1.95 3.24 1.15 1.53 1.91 2.29 3.81 1.61 2.14 2.67 3.21 5.33
Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD point position whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter tINYH tINYL tINGH tINGL Description Pad-to-Y HIGH Pad-to-Y HIGH `-2' Speed Min. Max. 1.17 0.90 1.56 1.56 `-1' Speed Min. Max. 1.33 1.02 1.77 1.77 `Std' Speed Min. Max. 1.56 1.20 2.08 2.08 `-F' Speed Min. Max. 2.18 1.68 2.91 2.91 Units
Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.03 2.32 2.60 2.89 4.03 2.30 2.63 2.95 3.27 4.56 2.71 3.09 3.47 3.85 5.37 3.79 4.33 4.86 5.39 7.52
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency 0.00 0.00 3.08 3.53 4.65 5.12 215.00 195.00 3.53 4.05 3.53 4.05 0.38 0.38 0.00 0.00 5.49 4.00 5.06 5.57 197.80 179.40 2.90 3.20 4.20 4.95 4.00 4.59 4.00 4.59 0.43 0.43 0.00 0.00 4.10 4.70 5.81 6.41 172.00 156.00 3.27 3.60 4.76 5.61 4.70 5.40 4.70 5.40 0.50 0.50 0.00 0.00 5.74 6.58 9.69 10.68 103.20 93.60 3.90 4.28 5.60 6.60 6.58 7.56 6.58 7.56 0.70 0.70 5.42 5.96 7.84 9.24
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
Fami
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH Module Timing1 Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 3.56 2.73 3.00 3.32 6.02 5.57 5.63 5.63 6.28 8.93 0.03 0.04 4.03 3.09 3.40 3.76 6.82 6.31 6.38 6.38 7.12 10.12 0.03 0.04 4.74 3.64 4.00 4.42 8.02 7.42 7.51 7.51 8.38 11.90 0.04 0.05 6.64 5.10 5.60 6.19 11.23 10.39 10.51 10.51 11.90 16.66 0.06 0.07 ns/pF ns/pF 2.79 3.27 3.00 3.32 6.02 5.57 3.20 3.20 6.28 8.93 0.03 0.04 3.16 3.71 3.40 3.76 6.82 6.31 3.60 3.60 7.12 10.12 0.03 0.04 3.72 4.36 4.00 4.42 8.02 7.42 4.30 4.30 8.38 11.90 0.04 0.05 5.21 6.10 5.60 6.19 11.23 10.39 6.00 6.00 11.90 16.66 0.06 0.07 ns/pF ns/pF
Notes: Delays based loading.
A42MX16 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
Logic Module Propagation Delays1 Parameter tPD1 Description Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q `-2' Speed Min. Max. 2.13 2.24 2.13 2.44 `-1' Speed Min. Max. 2.42 2.53 2.42 2.76 `Std' Speed Min. Max. 2.84 2.98 2.84 3.25 `-F' Speed Min. Max. 3.98 4.17 3.98 4.55 Units
Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics3, 0.50 0.00 1.05 0.00 5.29 6.93 10.58 0.00 0.76 0.00 0.76 117.00 0.57 0.00 1.19 0.00 6.00 7.85 12.00 0.00 0.86 0.00 0.86 107.64 0.67 0.00 1.40 0.00 7.06 9.24 14.11 0.00 1.01 0.00 1.01 93.60 0.94 0.00 1.96 0.00 9.88 12.94 19.76 0.00 1.41 0.00 1.41 56.16 1.21 1.61 2.01 2.40 4.00 1.37 1.82 2.27 2.73 4.53 1.61 2.14 2.67 3.21 5.33 2.25 3.00 3.74 4.49 7.47
Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
Notes: dual-module macros tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
Fami
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter tINYH tINYL tINGH tINGL Description Pad-to-Y HIGH Pad-to-Y HIGH `-2' Speed Min. Max. 1.64 1.26 2.18 2.18 `-1' Speed Min. Max. 1.86 1.43 2.48 2.48 `Std' Speed Min. Max. 2.18 1.68 2.91 2.91 `-F' Speed Min. Max. 3.06 2.35 4.08 4.08 Units
Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.85 3.24 3.64 4.04 5.64 3.22 3.68 4.13 4.58 6.39 3.79 4.33 4.86 5.39 7.52 5.31 6.06 6.80 7.55 10.53
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency 0.00 0.00 4.31 4.94 7.75 8.55 129.00 117.00 6.30 7.35 5.88 6.93 0.53 2.42 0.00 0.00 4.88 5.59 8.43 9.29 118.68 107.64 4.83 5.33 5.88 6.93 7.14 8.33 6.66 7.85 0.60 2.74 0.00 0.00 5.74 6.58 9.71 10.68 103.20 93.60 5.45 6.00 6.66 7.85 8.40 9.80 7.84 9.24 0.70 3.22 0.00 0.00 8.04 9.21 16.15 17.81 61.92 56.16 6.50 7.13 7.84 9.24 11.76 13.72 10.98 12.94 0.98 4.51 9.03 9.93 10.98 12.94
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH Module Timing1 Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 4.98 3.82 4.20 4.64 8.42 7.79 7.89 7.89 8.93 12.50 0.04 0.05 5.64 4.33 4.76 5.26 9.54 8.83 8.94 8.94 10.12 14.16 0.05 0.06 6.64 5.10 5.60 6.19 11.23 10.39 10.51 10.51 11.90 16.66 0.06 0.07 9.29 7.13 7.84 8.66 15.72 14.54 14.72 14.72 16.66 23.32 0.08 0.10 ns/pF ns/pF 3.91 4.58 4.20 4.64 8.42 7.79 5.30 5.30 8.93 4.43 5.19 4.76 5.26 9.54 8.83 6.00 6.00 10.12 14.16 0.05 0.06 5.21 6.10 5.60 6.19 11.23 10.39 7.16 7.16 11.90 16.66 0.06 0.07 7.29 8.55 7.84 8.66 15.72 14.54 10.00 10.00 16.66 23.32 0.08 0.10 ns/pF ns/pF
12.50 0.04 0.05
Notes: Delays based loading.
Fami
A42MX24 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
Preliminary Information Logic Module Propagation Parameter Description Delays1 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Combinatorial Functions tPDD tRD1 tRD2 tRD3 tRD4 tRD5 Internal Array Module Delay Internal Decode Module Delay 1.31 1.59 1.49 1.80 1.75 2.12 2.45 2.97
Predicted Routing Delays2 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics3, 1.43 1.31 0.35 0.00 1.55 0.45 0.00 3.68 4.83 0.51 0.00 4.17 5.47 0.40 0.00 1.76 0.60 0.00 4.91 6.44 1.62 1.49 0.47 0.00 2.07 0.84 0.00 6.87 9.02 1.90 1.75 0.66 0.00 2.90 2.66 2.45 0.89 1.15 1.40 1.66 2.67 1.01 1.30 1.59 1.88 3.03 1.19 1.53 1.87 2.21 3.56 1.67 2.14 2.62 3.09 4.98
Sequential Timing tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Input Module Propagation Delays Parameter tINPY tINGO tINH tINSU tILA Description Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width Delays 2.03 2.29 2.54 2.80 3.81 2.30 2.59 2.88 3.17 4.32 2.71 3.05 3.39 3.73 5.08 3.79 4.27 4.75 5.22 7.11 0.00 0.53 5.18 `-2' Speed Min. Max. 1.14 1.39 0.00 0.60 5.87 `-1' Speed Min. Max. 1.29 1.57 0.00 0.70 6.90 `Std' Speed Min. Max. 1.52 1.85 0.00 0.98 9.66 `-F' Speed Min. Max. 2.13 2.59 Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 0.00 0.00 3.08 3.68 5.23 5.71 191.25 175.00 2.40 2.63 2.40 2.63 0.60 0.60 0.00 0.00 3.49 4.17 5.68 6.21 175.95 161.00 2.90 3.20 4.05 4.73 2.72 2.98 2.72 2.98 0.68 0.68 0.00 0.00 4.10 4.90 6.50 7.14 153.00 140.00 3.27 3.60 4.59 5.36 3.20 3.50 3.20 3.50 0.80 0.80 0.00 0.00 5.74 6.86 10.89 11.90 91.80 84.00 3.90 4.28 5.40 6.30 4.48 4.90 4.48 4.90 1.12 1.12 5.42 5.92 7.56 8.82
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance.
Fami
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Output Module Timing Parameter Description Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH Module Timing1 3.45 2.61 2.82 3.13 5.72 5.33 5.42 5.42 0.53 0.00 6.08 11.78 0.04 0.03 0.60 0.00 6.89 13.35 0.04 0.03 3.91 2.96 3.20 3.54 6.48 6.04 6.15 6.15 0.70 0.00 8.10 15.70 0.05 0.04 4.60 3.48 3.76 4.17 7.62 7.10 7.23 7.23 0.98 0.00 11.34 21.98 0.07 0.06 6.44 4.87 5.26 5.84 10.67 9.94 10.12 10.12 ns/pF ns/pF 0.53 0.00 6.08 11.78 0.04 0.03 2.70 3.15 2.82 3.13 5.72 5.33 3.20 3.20 0.60 0.00 6.89 13.35 0.04 0.03 3.06 3.57 3.20 3.54 6.48 6.04 3.60 3.60 0.70 0.00 8.10 15.70 0.05 0.04 3.60 4.20 3.76 4.17 7.62 7.10 4.30 4.30 0.98 0.00 11.34 21.98 0.07 0.06 5.04 5.88 5.26 5.84 10.67 9.94 6.00 6.00 ns/pF ns/pF
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH
Notes: Delays based loading.
A42MX24 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
Preliminary Information Logic Module Propagation Parameter Description Delays1 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Combinatorial Functions tPDD tRD1 tRD2 tRD3 tRD4 tRD5 Internal Array Module Delay Internal Decode Module Delay 1.84 2.23 2.08 2.52 2.45 2.97 3.43 4.16
Predicted Routing Delays2 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics3, 2.00 1.84 0.49 0.00 2.17 0.63 0.00 5.16 6.76 0.71 0.00 5.84 7.66 0.56 0.00 2.46 0.84 0.00 6.87 9.02 2.26 2.08 0.66 0.00 2.90 1.18 0.00 9.62 12.62 2.66 2.45 0.92 0.00 4.06 3.72 3.43 1.25 1.61 1.96 2.32 3.74 1.42 1.82 2.23 2.63 4.24 1.67 2.14 2.62 3.09 4.98 2.33 3.00 3.67 4.33 6.98
Sequential Timing tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Notes: dual-module macros, tPD1 tRD1 tPDn tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
Fami
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Input Module Propagation Delays Parameter tINPY tINGO tINH tINSU tILA Description Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.00 0.74 7.25 `-2' Speed Min. Max. 1.60 1.94 0.00 0.83 8.21 `-1' Speed Min. Max. 1.81 2.20 0.00 0.98 9.66 `Std' Speed Min. Max. 2.13 2.59 0.00 1.37 13.52 `-F' Speed Min. Max. 2.98 3.63 Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.85 3.20 3.56 3.92 5.33 3.22 3.63 4.03 4.44 6.05 3.79 4.27 4.75 5.22 7.11 5.31 5.98 6.64 7.31 9.96
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 0.00 0.00 4.31 5.15 8.71 9.52 114.75 105.00 3.36 3.68 3.36 3.68 0.84 0.84 0.00 0.00 4.88 5.83 9.47 10.35 105.57 96.60 4.83 5.33 5.67 6.62 3.81 4.17 3.81 4.17 0.95 0.95 0.00 0.00 5.74 6.86 10.80 11.90 91.80 84.00 5.45 6.00 6.43 7.50 4.48 4.90 4.48 4.90 1.12 1.12 0.00 0.00 8.04 9.60 18.15 19.84 55.08 50.40 6.50 7.13 7.56 8.82 6.27 6.86 6.27 6.86 1.57 1.57 9.03 9.93 10.58 12.35
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance.
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Output Module Timing Parameter Description Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH Module Timing1 5.32 3.90 3.95 3.75 8.00 7.46 7.59 7.59 0.74 0.00 8.51 16.49 0.05 0.04 0.83 0.00 9.64 18.68 0.06 0.05 5.47 4.14 4.47 4.96 9.07 8.45 8.60 8.60 0.98 0.00 11.34 21.98 0.07 0.06 6.44 4.87 5.26 5.84 10.67 9.94 10.12 10.12 1.37 0.00 15.88 30.77 0.10 0.08 9.02 6.82 7.37 8.17 14.94 13.92 14.17 14.17 ns/pF ns/pF 0.74 0.00 8.51 16.49 0.05 0.04 3.78 4.41 3.95 4.38 8.00 7.46 5.30 5.30 0.83 0.00 9.64 18.68 0.06 0.05 4.28 5.00 4.47 4.96 9.07 8.45 6.00 6.00 0.98 0.00 11.34 21.98 0.07 0.06 5.04 5.88 5.26 5.84 10.67 9.94 7.16 7.16 1.37 0.00 15.88 30.77 0.10 0.08 7.06 8.23 7.37 8.17 14.94 13.92 10.00 10.00 ns/pF ns/pF
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH
Notes: Delays based loading.
Fami
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
Preliminary Information Logic Module Propagation Delays Parameter Description Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Combinatorial Functions tPDD tRD1 tRD2 tRD3 tRD4 tRD5 tRDD Internal Array Module Delay Internal Decode Module Delay 1.46 1.78 1.66 2.01 1.95 2.37 2.73 3.32
Predicted Module Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay 1.04 1.42 1.79 2.18 3.68 0.38 1.18 1.61 2.03 2.47 4.17 0.43 1.39 1.89 2.39 2.90 4.91 0.50 1.95 2.65 3.35 4.06 6.87 0.70
Sequential Timing Characteristics tSUENA tHENA tWCLKA tWASYN Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.75 0.00 3.68 4.83 0.35 0.00 1.73 0.85 0.00 4.17 5.47 1.43 1.43 0.40 0.00 1.96 1.00 0.00 4.91 6.44 1.62 1.62 0.47 0.00 2.31 1.40 0.00 6.87 9.02 1.90 1.90 0.66 0.00 3.23 2.66 2.66
A42MX36 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Logic Module Timing Parameter Description Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 1.80 0.00 0.68 3.75 3.00 0.00 3.08 0.00 7.50 7.50 3.75 3.75 2.04 0.00 0.77 4.25 3.40 0.00 3.49 0.00 8.50 8.50 4.25 4.25 2.40 0.00 0.90 5.00 4.00 0.00 4.10 0.00 10.00 10.00 5.00 5.00 3.36 0.00 1.26 7.00 5.60 0.00 5.74 0.00 14.00 14.00 7.00 7.00
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Hold Time 9.75 1.80 0.00 0.68 3.75 3.00 0.00 1.35 9.00 11.10 2.04 0.00 0.77 4.25 3.40 0.00 1.53 10.20 13.00 2.40 0.00 0.90 5.00 4.00 0.00 1.80 12.00 18.20 3.36 0.00 1.26 7.00 5.60 0.00 2.52 16.80
Fami
A42MX36 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Advanced Information Input Module Propagation Delays Parameter tINPY tINGO tINH tINSU tILA Description Input Data Pad-to-Y Input Latch Gate-to-Output1 0.00 0.53 5.18 `-2' Speed Min. Max. 1.14 1.55 0.00 0.60 5.87 `-1' Speed Min. Max. 1.29 1.76 0.00 0.70 6.90 `Std' Speed Min. Max. 1.52 2.07 0.00 0.98 9.66 `-F' Speed Min. Max. 2.13 2.90 Units
Input Latch Hold1 Input Latch Set-Up1 Latch Active Pulse Width1
Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.18 2.56 2.93 3.32 4.82 2.47 2.90 3.32 3.76 5.47 2.91 3.41 3.91 4.42 6.43 4.07 4.77 5.47 6.19 9.00
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fHMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.00 0.00 3.15 3.68 6.10 6.61 163.75 151.25 1.95 2.18 1.95 2.18 0.83 0.83 0.00 0.00 3.57 4.17 6.64 7.19 150.65 139.15 3.03 3.33 4.20 5.40 2.21 2.47 2.21 2.47 0.94 0.94 0.00 0.00 4.20 4.90 7.63 8.26 131.00 121.00 3.42 3.76 4.76 6.12 2.60 2.90 2.60 2.90 1.00 1.00 0.00 0.00 5.88 6.86 12.72 13.77 78.60 72.60 4.02 4.43 5.60 7.20 3.64 4.06 3.64 4.06 1.40 1.40 5.63 6.20 7.81 10.08
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance.
A42MX36 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Advanced Information Output Module Timing Parameter Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Description Module Timing1 Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 0.53 0.00 6.30 8.63 0.08 0.08 2.84 3.29 2.95 3.26 5.84 5.45 3.27 3.27 0.60 0.00 7.14 9.78 0.09 0.09 3.21 3.73 3.34 3.69 6.62 6.18 3.70 3.70 0.70 0.00 8.40 11.50 0.10 0.10 3.78 4.39 3.93 4.34 7.79 7.27 4.35 4.35 0.98 0.00 11.76 16.10 0.14 0.14 5.29 6.15 5.50 6.08 10.91 10.18 6.09 6.09 ns/pF ns/pF `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module Timing1 Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 0.53 0.00 6.30 8.63 0.08 0.08 3.92 2.73 2.95 3.26 5.84 5.45 5.59 5.59 0.60 0.00 7.14 9.78 0.09 0.09 4.45 3.09 3.34 3.69 6.62 6.18 6.33 6.33 0.70 0.00 8.40 11.50 0.10 0.10 5.23 3.64 3.93 4.34 7.79 7.27 7.45 7.45 0.98 0.00 11.76 16.10 0.14 0.14 7.32 5.10 5.50 6.08 10.91 10.19 10.43 10.43 ns/pF ns/pF
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance.
Fami
A42MX36 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
Preliminary Information Logic Module Propagation Delays Parameter Description Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Combinatorial Functions tPDD tRD1 tRD2 tRD3 tRD4 tRD5 tRDD Internal Array Module Delay Internal Decode Module Delay 2.05 2.49 2.32 2.82 2.73 3.32 3.82 4.65
Predicted Module Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay 1.46 1.98 2.51 3.05 5.16 0.53 1.65 2.25 2.84 3.45 5.84 0.60 1.95 2.65 3.35 4.06 6.87 0.70 2.72 3.70 4.68 5.68 9.62 0.98
Sequential Timing Characteristics tSUENA tHENA tWCLKA tWASYN Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 1.05 0.00 5.16 6.76 0.49 0.00 2.43 1.19 0.00 5.84 7.66 2.00 2.00 0.56 0.00 2.75 1.40 0.00 6.87 9.02 2.26 2.26 0.66 0.00 3.23 1.96 0.00 9.62 12.62 2.66 2.66 0.92 0.00 4.53 3.72 3.72
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Logic Module Timing Parameter Description Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 2.50 0.00 1.00 5.30 4.20 0.00 4.30 0.00 10.50 10.50 5.30 5.30 2.80 0.00 1.10 6.00 4.80 0.00 4.90 0.00 11.90 11.90 6.00 6.00 3.40 0.00 1.30 7.00 5.60 0.00 5.70 0.00 14.00 14.00 7.00 7.00 4.80 0.00 1.80 9.80 7.80 0.00 8.00 0.00 19.60 19.60 9.80 9.80
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Hold Time 13.70 2.50 0.00 1.00 5.30 4.20 0.00 2.00 12.60 15.50 2.80 0.00 1.10 6.00 4.80 0.00 2.10 14.30 18.20 3.40 0.00 1.30 7.00 5.60 0.00 2.50 16.80 25.50 4.76 0.00 1.80 9.80 7.80 0.00 3.50 23.50
Fami
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Input Module Propagation Delays Parameter tINPY tINGO tINH tINSU tILA Description Input Data Pad-to-Y Input Latch Gate-to-Output1 0.00 0.74 7.25 `-2' Speed Min. Max. 1.60 2.17 0.00 0.83 8.21 `-1' Speed Min. Max. 1.81 2.46 0.00 0.98 9.66 `Std' Speed Min. Max. 2.13 2.90 0.00 1.37 13.52 `-F' Speed Min. Max. 2.98 4.06 Units
Input Latch Hold1 Input Latch Set-Up1 Latch Active Pulse Width1
Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3.06 3.58 4.11 4.64 6.75 3.46 4.06 4.65 5.26 7.65 4.07 4.77 5.47 6.19 9.00 5.70 6.68 7.66 8.66 12.60
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fHMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.00 0.00 4.41 5.15 10.18 11.02 98.25 90.75 2.73 3.05 2.73 3.05 1.16 1.16 0.00 0.00 5.00 5.83 11.06 11.98 90.39 83.49 5.05 5.55 5.88 7.56 3.09 3.45 3.09 3.45 1.31 1.31 0.00 0.00 5.88 6.86 12.70 13.77 78.60 72.60 5.70 6.26 6.66 8.57 3.64 4.06 3.64 4.06 1.54 1.54 0.00 0.00 8.23 9.60 21.20 22.96 47.16 43.56 6.70 7.40 7.84 10.08 5.10 5.68 5.10 5.68 2.16 2.16 9.38 10.33 10.98 14.11
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance.
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Output Module Timing Parameter Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Description Module Timing1 Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 0.74 0.00 8.82 12.08 0.11 0.11 3.97 4.61 4.13 4.56 8.18 7.63 5.45 5.45 0.83 0.00 10.00 13.69 0.12 0.12 4.50 5.22 4.68 5.16 9.27 8.65 6.16 6.16 0.98 0.00 11.76 16.10 0.14 0.14 5.29 6.15 5.50 6.08 10.91 10.18 7.25 7.25 1.37 0.00 16.46 22.54 0.20 0.20 7.41 8.60 7.70 8.51 15.27 14.25 10.15 10.15 ns/pF ns/pF `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module Timing1 Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 0.74 0.00 8.82 12.08 0.11 0.11 5.49 3.82 4.13 4.56 8.18 7.63 7.82 7.82 0.83 0.00 10.00 13.69 0.12 0.12 6.22 4.33 4.68 5.16 9.27 8.65 8.87 8.87 0.98 0.00 11.76 16.10 0.14 0.14 7.32 5.10 5.50 6.08 10.91 10.18 10.43 10.43 1.37 0.00 16.46 22.54 0.20 0.20 10.25 7.13 7.70 8.51 15.27 14.25 14.60 14.60 ns/pF ns/pF
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance.
Fami
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Militar Conditions, 4.5V,
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