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SST28SF040 SST28LF040 SST28VF040 FEATURES: Single Voltage Read Wr
Top Searches for this datasheetMegabit (512K SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 FEATURES: Single Voltage Read Write Operations 5.0V-only SST28SF040 3.0-3.6V SST28LF040 2.7-3.6V SST28VF040 Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Memory Organization: 512K Sector Erase Capability: bytes Sector Power Consumption Active Current: (typical) 5.0V (typical) 3.0-3.6V/2.7-3.6V Standby Current: (typical) Fast Sector Erase/Byte Program Operation Byte Program Time: (typical) Sector Erase Time: (typical) Complete Memory Rewrite: (typical) Fast Read Access Time 5.0V-only operation: 3.0-3.6V operation: 2.7-3.6V operation: Latched Address Data Hardware Software Data Protection 7-Read-Cycle-Sequence Software Data Protection Write Detection Toggle Data# Polling Compatibility JEDEC Standard Flash EEPROM Pinouts Packages Available 32-Pin PDIP 32-Pin PLCC 32-Pin TSOP (8mm 20mm) PRODUCT DESCRIPTION SST28SF040/28LF040/28VF040 512K CMOS sector erase, byte program EEPROMs. SST28SF040/28LF040/28VF040 manufactured using SST's proprietary, high performance CMOS SuperFlash EEPROM Technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternative approaches. SST28SF040/28LF040/28VF040 erase program with single power supply. SST28SF040/28LF040/28VF040 conform JEDEC standard pinouts byte wide memories compatible with existing industry standard EPROM, flash EEPROM pinouts. Featuring high performance programming, SST28SF040/28LF040/28VF040 typically byte program SST28SF040/28LF040/28VF040 typically sector erase Both program erase times optimized using interface features such Toggle Data# Polling indicate completion write cycle. protect against inadvertent write, SST28SF040/28LF040/28VF040 have chip hardware software data protection schemes. Designed, manufactured, tested wide spectrum applications, SST28SF040/28LF040/28VF040 offered with guaranteed sector endurance cycles. Data retention rated greater than years. SST28SF040/28LF040/28VF040 best suited applications that require reprogrammable nonvolatile mass storage program, configuration, data memory. system applications, SST28SF040/ 28LF040/28VF040 significantly improve performance reliability, while lowering power consumption when compared with floppy diskettes EPROM approaches. EEPROM technology makes possible convenient economical updating codes control programs online. SST28SF040/28LF040/28VF040 improve flexibility, while lowering cost program configuration storage application. functional block diagram shows functional blocks SST28SF040/28LF040/28VF040. Figures show assignments TSOP, PDIP, PLCC packages. description operation modes described Tables through Device Operation Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first. Note, during software data protection sequence addresses latched rising edge CE#, whichever occurs first. 1999 Silicon Storage Technology, Inc. logo SuperFlash registered trademarks Silicon Storage Technology, Inc. These specifications subject change without notice. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 Command Definitions Table contains command list brief summary commands. following detailed description operations initiated each command. Sector Erase Operation Sector Erase operation erases bytes within sector initiated setup command execute command. sector contains bytes. This sector erasability enhances flexibility usefulness SST28SF040/28LF040/28VF040, since most applications only need change small number bytes sectors, entire chip. setup command performed writing device. execute command performed writing device. Erase operation begins with rising edge CE#, whichever occurs first terminates automatically using internal timer. Erase determined using either Data# Polling, Toggle Bit, Successive Reads detection methods. Figure timing waveforms. two-step sequence setup command followed execute command ensures that only memory contents within addressed sector erased other sectors inadvertently erased. Sector Erase Flowchart Description Fast reliable erasing memory contents within sector accomplished following sector erase flowchart shown Figure entire procedure consists execution commands. Sector Erase operation will terminate after maximum Reset command executed terminate Sector Erase operation; however, Erase operation terminated prior time-out, sector fully erased. Sector Erase command reissued many times necessary complete erase operation. SST28SF040/28LF040/28VF040 cannot "overerased". Chip Erase Operation Chip Erase operation initiated setup command (30H) execute command (30H). Chip Erase operation allows entire array SST28SF040/28LF040/28VF040 erased operation, opposed 2048 Sector Erase operations. Using Chip Erase operation will minimize time rewrite entire memory array. Chip Erase operation will terminate after maximum Reset command executed terminate Erase operation; however, Chip Erase operation terminated prior time-out, chip completely erased. erase error occurs Chip Erase command reissued many times necessary complete Chip Erase operation. SST28SF040/28LF040/28VF040 cannot "overerased". (See Figure Byte Program Operation Byte Program operation initiated writing setup command (10H). Once program setup performed, programming executed next pulse. Figures timing waveforms. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first, begins Program operation. Program operation terminated automatically internal timer. Figure programming flowchart. two-step sequence setup command followed execute command ensures that only addressed byte programmed other bytes inadvertently programmed. Byte Program Flowchart Description Programming data into SST28SF040/28LF040/ 28VF040 accomplished following Byte Program flowchart shown Figure Byte Program command sets byte programming. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first begins Program operation. program detected using either Data# Polling, Toggle bit, Successive reads. Reset Operation Reset command provided means safely abort Erase Program command sequences. Following either setup commands (Erase Program) with write will safely abort operation. Memory contents will altered. After Reset command, device returns Read mode. Reset command does enable Software Data Protection. Figure timing waveforms. 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 Read Read operation initiated setting CE#, logic setting logic high (See Table Figure Read memory timing waveform. Read operation from host retrieves data from array. device remains enabled Read until another operation mode accessed. During initial power-up, device Read mode Software Data protected. device must unprotected execute Write command. Read operation SST28SF040/28LF040/ 28VF040 controlled logic low. When high, chip deselected only standby power will consumed. output control used gate data from output pins. data high impedance state when high. Read operation Read operation initiated writing single command (90H). read address 0000H will output manufacturer's code (BFH). read address 0001H will output device code (04H). other valid command will terminate this operation. Data Protection order protect integrity nonvolatile data storage, SST28SF040/28LF040/28VF040 provide both hardware software features prevent inadvertent writes device, example, during system powerup power-down. Such provisions described below. Hardware Data Protection SST28SF040/28LF040/28VF040 designed with hardware features prevent inadvertent writes. This done following ways: Write Inhibit Mode: low, CE#, high will inhibit Write operation. Noise/Glitch Protection: pulse width less than will initiate write cycle. Power Up/Down Detection: Write operation inhibited when less than 2.5V. After power-up device Read mode device Software Data Protect state. Software Data Protection (SDP) SST28SF040/28LF040/28VF040 have software methods further prevent inadvertent writes. order perform Erase Program operation, two-step command sequence consisting set-up command followed execute command avoids inadvertent erasing programming device. SST28SF040/28LF040/28VF040 will default Software Data Protection after power sequence seven consecutive reads specific addresses will unprotect device address sequence 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. address latched rising edge CE#, whichever occurs first. similar seven read sequence 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect device. Also refer Figures read cycle sequence Software Data Protection. pins state (i.e., high, low, tristate). Write Operation Status Detection SST28SF040/28LF040/28VF040 provide three means detect completion write cycle, order optimize system write cycle time. write cycle (Erase Program) detected three means: monitoring Data# Polling bit; monitoring Toggle bit; successive reads same data. These three detection mechanisms described below. actual completion nonvolatile Write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with used. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed write cycle, otherwise rejection valid. Data# Polling (DQ7) SST28SF040/28LF040/28VF040 feature Data# Polling indicate Write operation status. During Write operation, attempt read last byte loaded during byte-load cycle will receive complement true data DQ7. Once write cycle completed, will show true data. device then ready next operation. Figure Data# Polling timing waveforms. order Data# Polling function correctly, byte being polled must erased prior programming. 309-02 1/99 1999 Silicon Storage Technology, Inc. This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 Toggle DQ6) alternative means determining Write operation status monitoring Toggle Bit, DQ6. During Write operation, consecutive attempts read data from device will result toggling between logic (low) logic (high). When write cycle completed, toggling will stop. device then ready next operation. Figure Toggle timing waveforms. Successive Reads Alternative means determining write cycle reading same address consecutive data matches. Product Identification Product Identification mode identifies device SST28SF040/28LF040/28VF040 manufacturer SST. This mode accessed hardware software operations. hardware operation typically used external programmer identify correct algorithm SST28SF040/28LF040/28VF040. Users wish software operation identify device (i.e., using device code). details Table hardware operation Figure software operation. manufacturer device codes same both operations. PRODUCT IDENTIFICATION TABLE Manufacturer's Code Device Code Byte 0000 0001 Data FUNCTIONAL BLOCK DIAGRAM SST28SF040/28LF040/28VF040 X-Decoder 4,194,304 EEPROM Cell Array Address Buffer Latches Y-Decoder Control Logic Buffers Data Latches B1.0 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 Standard Pinout View F01.0 FIGURE STANDARD ASSIGNMENT 32-PIN TSOP PACKAGE 32-Pin PDIP View F02.0 32-Lead PLCC View FIGURE ASSIGNMENTS 32-PIN PLASTIC DIP'S 32-PIN PLCC'S TABLE DESCRIPTION Symbol Name A18-A8 Address Inputs A7-A0 Column Address Inputs DQ7-DQ0 Data Input/Output Chip Enable Output Enable Write Enable Power Supply Ground Functions provide memory addresses. addresses define sector. Selects byte within sector. output data during read cycles receive input data during write cycles. Data internally latched during write cycle. outputs tri-state when OE#, high. activate device when low. gate data output buffers. control write operations. provide 5-volt supply 10%) SST28SF040, 3.0-3.6V supply SST28LF040 2.7-3.6V supply SST28VF040 T1.1 Note: This considered input purposes Operation Characteristics Table. 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 TABLE OPERATION MODES SELECTION Mode Read Byte Program Sector Erase Standby Write Inhibit Write Inhibit Software Chip Erase Product Identification Hardware Mode Software Mode Enable Disable Mode Reset DOUT High High DOUT High DOUT Manufacturer Code (BF) Device Code (04) Address AIN, Table AIN, Table Table A18-A1=VIL, A9=VH, A0=V A18-A1=VIL, A9=VH, A0=V Table Table Table T2.0 TABLE SOFTWARE COMMAND SUMMARY Command Summary Sector Erase Byte Program Chip Erase Reset Read Software Data Protect Software Data Unprotect Notes: Required Setup Command Cycle Execute Command Cycle Cycle(s) Type(1) Addr(2,3) Data(4) Type(1) Addr(2,3) Data(4) SDP(5) T3.1 Type definition: Write, Read, don't care Addr (Address) definition: Sector Address sector size bytes; this command. Addr (Address) definition: Program Address Data definition: Program Data, number hex. Software Data Protect mode using Read Cycle Sequence. operation executed with protection enabled operation cannot executed with protection enabled Refer Figure Read Cycle sequence Software Data Protect. Refer Figure Read Cycle sequence Software Data Unprotect. Address 0000H retrieves manufacturer' code address 0001H retrieves device code 04H. TABLE MEMORY ARRAY DETAIL Sector Select Byte Select T4.0 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VCC+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VCC+ 1.0V Voltage Ground Potential -0.5V 14.0V Package Power Dissipation Capability 25°C) 1.0W Through Hole Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1) Note: Outputs shorted more than second. more than output shorted time. SST28SF040 OPERATING RANGE Range Ambient Temp Commercial +70°C Industrial -40°C +85°C CONDITIONS TEST 5V±10% 5V±10% Input Rise/Fall Time Output Load Gate Figures SST28LF040 OPERATING RANGE Range Ambient Temp Commercial +70°C Industrial -40°C +85°C 3.6V 3.6V SST28VF040 OPERATING RANGE Range Ambient Temp Commercial +70°C Industrial -40°C +85°C 3.6V 3.6V 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 TABLE SST28SF040 OPERATING CHARACTERISTICS Limits Symbol Parameter Power Supply Current Read Program Erase ISB1 ISB2 Standby Current (TTL input) Standby Current (CMOS input) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage Supervoltage Supervoltage Current 11.6 12.4 Units Test Conditions =VIL, =VIH, I/Os open Address input VIL/VIH, f=1/TRC Min. =WE# =VIL, =VIH =VCC Max. VIH, VCC=VCC Max. -0.3V, VCC=VCC VCC, Max. VOUT =GND VCC, Max. Min. Max. IOL= Min. -400 Min. CE#=OE#=VIL,WE#=VIH CE#=OE#=VIL,WE#=VIH, Max. T5.1 TABLE SST28LF040/28VF040 OPERATING CHARACTERISTICS Limits Symbol Parameter Units Power Supply Current Read Program Erase ISB1 ISB2 Standby Current (TTL input) Standby Current (CMOS input) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage Supervoltage Supervoltage Current 11.6 12.4 Test Conditions =VIL, =VIH, I/Os open Address input VIL/VIH, f=1/TRC Min. =WE# =VIL, =VIH =VCC Max. VIH, VCC=VCC Max. -0.3V, VCC=VCC VCC, Max. VOUT =GND VCC, Max. Min. Max. IOL= Min. -100 Min. CE#=OE#=VIL,WE#=VIH CE#=OE#=VIL,WE#=VIH, Max. T6.1 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ Power-up Read Operation TPU-WRITE Power-up Write Operation Minimum Units T7.1 T8.0 TABLE CAPACITANCE MHz, other pins open) Parameter Description Test Condition CI/O(1) Capacitance VI/O CIN(1) Input Capacitance Maximum Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter. TABLE RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification NEND Endurance 1,000 10,000(2) TDR(1) Data Retention VZAP_HBM(1) Susceptibility 2000 Human Body Model VZAP_MM Susceptibility Machine Model ILTH(1) Latch Note: Units Cycles Years Volts Volts Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard T9.1 This parameter measured only initial qualification after design process change that could affect this parameter. Ordering Information desired type. 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 CHARACTERISTICS TABLE SST28SF040 READ CYCLE TIMING PARAMETERS IEEE Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX Industry Symbol TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change SST28SF040-120 SST28SF040-150 Units T10.0 TABLE SST28LF040 READ CYCLE TIMING PARAMETERS IEEE Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX Industry Symbol TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) SST28LF040-200 SST28LF040-250 Parameter Units Read Cycle time Address Access Time Chip Enable Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change T11.0 TABLE SST28VF040 READ CYCLE TIMING PARAMETERS IEEE Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX Industry Symbol TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) SST28VF040-250 Parameter Read Cycle time Address Access Time Chip Enable Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change SST28VF040-300 Units T12.0 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 TABLE SST28SF040 ERASE/PROGRAM CYCLE TIMING PARAMETERS IEEE Industry Symbol Symbol Parameter tAVA tWLWH tAVWL tWLAX tELWL tWHEX tGHWL tWGL tWLEH tDVWH tWHDX tWHWL2 tWHWL3 tEHEL tWHWL1 TOES TOEH TRST(1) TSCE TCPH TWPH TPCP(1) TPCH(1) TPAS(1) TPAH(1) Byte Program Cycle Time Write Pulse Width (WE#) Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Write Pulse Width (CE#) Data Setup Time Data Hold Time Sector Erase Cycle Time Reset Command Recovery Time Software Chip Erase Cycle Time High Pulse Width High Pulse Width Protect Chip Enable Pulse Width Protect Chip Enable High Time Protect Address Setup Time Protect Address Hold Time Units T13.1 Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter. 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 TABLE SST28LF040/28VF040 ERASE/PROGRAM CYCLE TIMING PARAMETERS IEEE Industry Symbol Symbol Parameter tAVA tWLWH tAVWL tWLAX tELWL tWHEX tGHWL tWGL tWLEH tDVWH tWHDX tWHWL2 tWHWL3 tEHEL tWHWL1 TOES TOEH TRST(1) TSCE TCPH TWPH TPCP(1) TPCH(1) TPAS(1) TPAH(1) Byte Program Cycle Time Write Pulse Width (WE#) Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Write Pulse Width (CE#) Data Setup Time Data Hold Time Sector Erase Cycle Time Reset Command Recovery Time Software Chip Erase Cycle Time High Pulse Width High Pulse Width Protect Chip Enable Pulse Width Protect Chip Enable High Time Protect Address Setup Time Protect Address Hold Time Units T14.0 Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter. 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 ADDRESS A18-0 TOHZ TCHZ DATA VALID DATA VALID F03.0 TOLZ TCLZ FIGURE READ CYCLE TIMING DIAGRAM ADDRESS A18-0 TOES BYTE PROGRAM SETUP COMMAND F04.0 TOEH TWPH DATA VALID FIGURE CONTROLLED BYTE PROGRAM TIMING DIAGRAM 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 ADDRESS A18-0 TCPH TOEH TOES BYTE PROGRAM SETUP COMMAND DATA VALID F05.0 FIGURE CONTROLLED BYTE PROGRAM TIMING DIAGRAM ADDRESS A18-0 TRST F06.0 FIGURE RESET COMMAND TIMING DIAGRAM 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 ADDRESS A18-0 TSCE SETUP COMMAND EXECUTE COMMAND F07.0 FIGURE CHIP ERASE TIMING DIAGRAM ADDRESS A18-0 SETUP COMMAND EXECUTE COMMAND F08.0 FIGURE SECTOR ERASE TIMING DIAGRAM 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 TPCP TPCH ADDRESS TPAS 1823 1820 TPAH 1822 0418 041B 0419 041A NOTE: ADDRESSES LATCHED INTERNALLY RISING EDGE KEPT TIME. KEPT TIME. FIRST HIGH BOTH TOGGLED. ABOVE ADDRESS VALUES HEX. ADDRESSES "DON'T CARE" F09.1 FIGURE SOFTWARE DATA UNPROTECT TIMING DIAGRAM TPCP TPCH ADDRESS TPAS 1823 1820 TPAH 1822 0418 041B 0419 040A NOTE: ADDRESSES LATCHED INTERNALLY RISING EDGE KEPT TIME. KEPT TIME. FIRST HIGH BOTH TOGGLED. ABOVE ADDRESS VALUES HEX. ADDRESSES "DON'T CARE" F10.0 FIGURE SOFTWARE DATA PROTECT TIMING DIAGRAM 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 ADDRESS A18-0 TOEH TOES NOTE F11.0 NOTE: THIS TIME INTERVAL SIGNAL DEPENDING UPON SELECTED OPERATION MODE. FIGURE DATA# POLLING TIMING DIAGRAM ADDRESS A18-0 TOEH TOES NOTE READ CYCLES WITH SAME OUTPUTS F12.0 NOTE: THIS TIME INTERVAL SIGNAL DEPENDING UPON SELECTED OPERATION MODE. FIGURE TOGGLE TIMING DIAGRAM 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 VIHT INPUT REFERENCE POINTS OUTPUT VILT F13.1 test inputs driven VIHT (2.4 logic VILT (0.4 logic "0". Measurement reference points inputs outputs (2.0 (0.8 Input rise fall times (10% 90%) Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT Test FIGURE INPUT/OUTPUT REFERENCE WAVEFORM TEST LOAD EXAMPLE TESTER HIGH F14.0 FIGURE TEST LOAD EXAMPLE 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 Start Initialize Address Execute Byte Program Setup Command Load Address Data Start Programming Read Write Detection Programming Completed? Data Verifies? Last Address Programming Completed F15.1 Next Address Programming Failure FIGURE BYTE PROGRAM FLOWCHART 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 Internal Timer Program/Erase Initiated Toggle Program/Erase Initiated Data# Polling Program/Erase Initiated Wait Read byte Read Program/Erase Completed Read same byte true data? Program/Erase Completed Does match? Program/Erase Completed F16.2 FIGURE WRITE WAIT OPTIONS 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 Start Initialize Sector Address Execute Step Sector Erase Command Write Detection Erase completed? Read from Selected Byte Address Verify Erase Error Increment Byte Address Last Address? Next Sector Address Sector Erase Completed Last Sector? F17.1 Device Erased FIGURE SECTOR ERASE FLOWCHART 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 Execute Read Command (90H) Enter Read mode Read Address 0000H MFG's Code (BF) Read Address 0001H Device Code 28SF040 (04) Execute Reset Command (FFH) Exit from Read mode F18.2 FIGURE SOFTWARE PRODUCT FLOW 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 PRODUCT ORDERING INFORMATION Device SST28XF040 Speed Suffix1 Suffix2 Package Modifier leads Numeric modifier Package Type PDIP PLCC TSOP (die Unencapsulated Operating Temperature Commercial 70°C Industrial -40° 85°C Minimum Endurance 1000 cycles 10,000 cycles Read Access Speed Voltage 5V-only 3.0-3.6V 2.7-3.6V 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 SST28SF040 Valid combinations SST28SF040-120-4C- SST28SF040-120-4C- SST28SF040-120-4C- SST28SF040-150-4C- SST28SF040-150-4C- SST28SF040-150-4C- SST28SF040-120-3C- SST28SF040-120-3C- SST28SF040-150-3C- SST28SF040-150-3C- SST28SF040-120-4I- SST28SF040-150-4I- SST28SF040-120-3C- SST28SF040-150-3C- SST28SF040-150-4C- SST28SF040-120-4I- SST28SF040-150-4I- SST28LF040 Valid combinations SST28LF040-200-4C- SST28LF040-200-4C- SST28LF040-200-4C- SST28LF040-250-4C- SST28LF040-250-4C- SST28LF040-250-4C- SST28LF040-250-4C- SST28LF040-200-3C- SST28LF040-200-3C- SST28LF040-250-3C- SST28LF040-250-3C- SST28LF040-200-4I- SST28LF040-200-3C- SST28LF040-250-3C- SST28LF040-250-3C- SST28LF040-200-4I- SST28VF040 Valid combinations SST28VF040-250-4C- SST28VF040-250-4C- SST28VF040-250-4C- SST28VF040-300-4C- SST28VF040-300-4C- SST28VF040-300-4C- SST28VF040-300-4C- SST28VF040-250-3C- SST28VF040-250-3C- SST28VF040-300-3C- SST28VF040-300-3C- SST28VF040-250-4I- SST28VF040-250-3C- SST28VF040-300-3C- SST28VF040-300-3C- SST28VF040-250-4I- Example:Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations. 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 PACKAGING DIAGRAMS index .600 .625 .530 .550 .065 .075 1.645 1.655 PLCS. Base Plane Seating Plane .015 .050 .120 .150 .170 .200 .008 .012 .600 .070 .080 .045 .065 .016 .022 .100 32.pdipPH-ILL.1 Note: Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .010 inches. 32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) PACKAGE CODE: VIEW SIDE VIEW BOTTOM VIEW Optional Identifier .485 .495 .447 .453 .042 .048 .106 .112 .020 MAX. .023 .029 .030 .040 .042 .048 .585 .595 .547 .553 .026 .032 .013 .021 .400 .490 .530 .050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032 32.PLCC.NH-ILL.1 Note: Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .008 inches. 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE: 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 IDENTIFIER 1.05 0.95 8.10 7.90 .270 .170 18.50 18.30 0.15 0.05 0.70 0.50 20.20 19.80 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions metric (min/max). Coplanarity: (±.05) 32.TSOP-EH-ILL.2 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE: 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Megabit SuperFlash EEPROM SST28SF040 SST28LF040 SST28VF040 SALES OFFICES Area Offices Customer Service Northwest USA, Rocky Mtns. West Canada Central Southwest East East Canada North America Distribution Asia Pacific East Asia Europe Northern Europe (408) 523-7754 (408) 523-7661 (727) 771-8819 (978) 356-3845 (941) 505-8893 (408) 523-7762 (81) 45-471-1851 (44) 1932-230555 (45) 3833-5000 International Sales Representatives Distributors Australia Belgium Memec Benelux China/Hong Kong Actron Technology Co., Ltd. (HQ) Hong Kong Actron Technology Co., Ltd. Shanghai Actron Technology Co., Ltd. Shenzhen Actron Technology Co., Ltd. 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Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873 1999 Silicon Storage Technology, Inc. 309-02 1/99 This Material Copyrighted Respective Manufacturer Other recent searchesPNZ327 - PNZ327 PNZ327 Datasheet MOC8111X - MOC8111X MOC8111X Datasheet MOC8112X - MOC8112X MOC8112X Datasheet MOC8113X - MOC8113X MOC8113X Datasheet MC10E - MC10E MC10E Datasheet MC100E336 - MC100E336 MC100E336 Datasheet MC100E451 - MC100E451 MC100E451 Datasheet MAX8646 - MAX8646 MAX8646 Datasheet LT1641 - LT1641 LT1641 Datasheet IDT72413 - IDT72413 IDT72413 Datasheet EASY3452 - EASY3452 EASY3452 Datasheet
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