The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

SST27SF256 SST27SF512 SST27SF010 SST27SF020 FEATURES: Organized 1


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



Kbit Kbit Mbit Mbit (x8) Many-Time Programmable Flash
SST27SF256 SST27SF512 SST27SF010 SST27SF020
FEATURES: Organized 128K 256K 5.0V (4.5-5.5V) Read Operation Superior Reliability Endurance: least 1000 Cycles Greater than years Data Retention Power Consumption Active Current: (typical) Standby Current: (typical) Fast Read Access Time Fast Byte-Program Operation Byte-Program Time: (typical) Chip-Program Time: seconds (typical) SST27SF256 seconds (typical) SST27SF512 seconds (typical) SST27SF010 seconds (typical) SST27SF020 PRODUCT DESCRIPTION SST27SF256/512/010/020 128K 256K CMOS, Many-Time Programmable (MTP) cost flash, manufactured with SST's proprietary, high performance SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. These devices electrically erased programmed least 1000 times using external programmer with volt power supply. They have erased prior programming. These devices conform JEDEC standard pinouts byte-wide memories. Featuring high performance Byte-Program, SST27SF256/512/010/020 provide Byte-Program time Designed, manufactured, tested wide spectrum applications, these devices offered with endurance least 1000 cycles. Data retention rated greater than years. SST27SF256/512/010/020 suited applications that require infrequent writes power nonvolatile storage. These devices will improve flexibility, efficiency, performance while matching cost nonvolatile applications that currently UVEPROMs, OTPs, mask ROMs. meet surface mount conventional through hole requirements, SST27SF256/512 offered 28pin PDIP, 32-pin PLCC 32-pin TSOP packages. SST27SF010/020 offered 32-pin PDIP, 32-pin PLCC 32-pin TSOP packages. Figures pinouts. Device Operation SST27SF256/512/010/020 cost flash solution that used replace existing UVEPROM, OTP, mask sockets. These devices functionally (read program) compatible with industry standard EPROM products. addition EPROM functionality, these devices also support electrical erase operation external programmer. They require source erase, therefore packages have window. Read Read operation SST27SF256/512/010/020 controlled OE#. Both have system obtain data from outputs. Once address stable, address access time equal delay from output (TCE). Data available output after delay from falling edge OE#, assuming that been addresses have been stable least TOE. Electrical Erase Using Programmer Does Require Source Chip-Erase Time: (typical) Compatibility JEDEC Standard Byte-wide EPROM Pinouts Power Supply Programming/Erase Packages Available 28-Pin PDIP SST27SF256/512 32-Pin PDIP SST27SF010/020 32-Pin PLCC 32-Pin TSOP (8mm 14mm)
2000 Silicon Storage Technology, Inc.The logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. 502-03 2/00 These specifications subject change without notice.
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet When high, chip deselected typical standby current consumed. output control used gate data from output pins. data high impedance state when either high. Byte-Program Operation SST27SF256/512/010/020 programmed using external programmer. programming mode SST27SF256/010/020 activated asserting (±5%) pin, (±5%), pin, pin. programming mode SST27SF512 activated asserting (±5%) OE#/VPP pin, (±5%), pin. These devices programmed byte-by-byte with desired data desired address using single pulse (CE# SST27SF256/512 PGM# SST27SF010/020) Using programming algorithm, Byte-Programming process continues byte-by-byte until entire chip been programmed. Chip-Erase Operation only change data from electrical erase that changes every device "1". Unlike traditional EPROMs, which light Chip-Erase, SST27SF256/512/010/020 uses electrical Chip-Erase operation. This saves significant amount time (about minutes each Erase operation). entire chip erased single pulse (CE# SST27SF256/512 PGM# SST27SF010/020). order activate Erase mode SST27SF256/010/020, (±5%) applied pins, (±5%), pin, pin. order activate Erase mode SST27SF512, (±5%) applied OE#/VPP pins, (±5%), pin. other address data pins "don't care". falling edge (PGM# SST27SF010/020) will start ChipErase operation. Once chip been erased, bytes must verified Refer Figures flowcharts. Product Identification Mode Product Identification mode identifies devices SST27SF256, SST27SF512, SST27SF010 SST27SF020 manufacturer SST. This mode accessed hardware method. activate this mode SST27SF256/010/020, programming equipment must force (12V±5%) address with (5V±10%) VSS. activate this mode SST27SF512, programming equipment must force (12V±5%) address with OE#/VPP VIL. identifier bytes then sequenced from device outputs toggling address line details, Tables hardware operation. TABLE PRODUCT IDENTIFICATION TABLE Byte Manufacturer's Code 0000 Device Code: SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data
T1.0
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet FUNCTIONAL BLOCK DIAGRAM SST27SF256 262,144 EEPROM Cell Array
X-Decoder
Address Buffer Y-Decoder
B1.0
Control Logic
Buffers
FUNCTIONAL BLOCK DIAGRAM SST27SF512 524,288 EEPROM Cell Array
X-Decoder
Address Buffer Y-Decoder
B2.0
OE#/VPP
Control Logic
Buffers
FUNCTIONAL BLOCK DIAGRAM SST27SF010/020 EEPROM Cell Array
Y-Decoder
X-Decoder
Address Buffer
PGM# Buffers Control Logic
B3.1
SST27SF020, SST27SF010
2000 Silicon Storage Technology, Inc. 502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
SST27SF020 SST27SF010 SST27SF512 SST27SF256
PGM# PGM#
SST27SF256
SST27SF512 SST27SF010 SST27SF020
OE#/VPP
Standard Pinout View
F01.0
FIGURE ASSIGNMENTS 32-PIN TSOP
SST27SF020 SST27SF010
SST27SF512 SST27SF256 SST27SF256
F01a.0
SST27SF010 SST27SF020 32-Pin PDIP View PGM#
F01b.0
SST27SF512 OE#/VPP
28-Pin PDIP View
PGM#
28-PIN PLASTIC DIPS SST27SF256/512 FIGURE ASSIGNMENTS 28-PIN 32-PIN PDIP
32-PIN PLASTIC DIPS SST27SF010/020
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
SST27SF256 SST27SF512 SST27SF010 SST27SF020
PGM#
PGM#
SST27SF256 SST27SF512 SST27SF010 SST27SF020 OE#/VPP
SST27SF020 SST27SF010 SST27SF512 SST27SF256
32-Pin PLCC View
SST27SF020 SST27SF010 SST27SF512 SST27SF256
F02c.1
FIGURE ASSIGNMENTS 32-PIN PLCC
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE DESCRIPTION Symbol Name Address Inputs AMS-A0 DQ7-DQ0 Data Input/Output OE#/VPP PGM#
Note:
Chip Enable Output Enable Output Enable/VPP Program/Erase Power Supply Program Erase Power Supply Ground Connection
Functions provide memory addresses output data during Read cycles receive input data during Program cycle, outputs tri-state when high activate device when SST27SF256/010/020, gate data output buffers during Read operation SST27SF512, gate data output buffers during Read operation high voltage during Chip-Erase programming operation SST27SF010/020, used Program Erase (PGM# pulse during Program Erase) SST27SF256/010/020, high voltage during Chip-Erase programming operation 12-volt (±5%) provide 5-volt supply (±10%) Unconnected pins
T2.2
Most significant address SST27SF256, SST27SF512, SST27SF010 SST27SF020
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE OPERATION MODES SELECTION SST27SF256 Mode Read Output Disable Byte-Program VPPH Standby Chip-Erase VPPH Program/Erase VPPH Inhibit Product Identification
Note: VPPH 12V±5%, 12V±5%
DOUT High High High High Manufacturer Code (BF) Device Code (A3)
Address
A14-A1 VIL, A14-A1 VIL,
T3.0
TABLE OPERATION MODES SELECTION SST27SF512 Mode OE#/VPP Read Output Disable Program VPPH Standby Chip-Erase VPPH Program/Erase Inhibit VPPH Product Identification
DOUT High High High High Manufacturer Code (BF) Device Code (A4)
Address VIL, VIL,
T4.0
Note:
VPPH 12V±5%, 12V±5%
TABLE OPERATION MODES SELECTION SST27SF010/020 Mode PGM# Read Output Disable Program VPPH Standby Chip-Erase VPPH Program/Erase VPPH Inhibit Product Identification
Note: VPPH 12V±5%, 12V±5% Device Code SST27SF010, SST27SF020 Most significant address SST27SF010 SST27SF020
DOUT High High High High Manufacturer Code (BF) Device Code
Address AMS(2)-A1 VIL, AMS(2)-A1 VIL,
T5.0
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VCC+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VCC+ 1.0V Voltage Ground Potential -0.5V 14.0V Package Power Dissipation Capability 25°C) 1.0W Through Hole Lead Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1)
Note: Outputs shorted more than second. more than output shorted time.
OPERATING RANGE Range Ambient Temp Commercial +70°C Industrial -40°C +85°C
CONDITIONS TEST 5V±10% 5V±10% 12V±5% 12V±5% Input Rise/Fall Time Output Load Output Load Figures
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE READ MODE OPERATING CHARACTERISTICS SST27SF256/512/010/020 V±10%, VSS, 70°C (Commercial) -40°C +85°C (Industrial) Limits Symbol Parameter Units Test Conditions Read Current I/Os open, Address Input VIL/VIH 1/TRC Min, Read Current VIL, I/Os open, IPPR Address Input VIL/VIH 1/TRC Min, Max, ISB1 ISB2 Standby Current (TTL input) Standby Current (CMOS input) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage Supervoltage Current Vcc+0.5 VIH, CE#=VCC -0.3V Max. VCC, VOUT VCC, -400µA, VIL, Max.
T6.0
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE PROGRAM/ERASE OPERATING CHARACTERISTICS SST27SF256 V±10%, VPPH,TA 25°C±5°C Limits Symbol Parameter Units Test Conditions Erase Program VIL, VIH, 12V±5%, Current Erase Program VIL, VIH, 12V±5%, Current VPPH Input Leakage Current Output Leakage Current Supervoltage Supervoltage Current High Voltage 11.4 12.6 12.6
T7.0
VCC, VOUT VCC, VIL,
11.4
TABLE PROGRAM/ERASE OPERATING CHARACTERISTICS SST27SF512 V±10%, VPPH,TA 25°C±5°C Limits Symbol Parameter Units Test Conditions Erase Program Current Erase Program Current Input Leakage Current Output Leakage Current Supervoltage Supervoltage Current High Voltage OE#/VPP 11.4 11.4 VIL, OE#/VPP 12V±5%, VIL, OE#/VPP 12V±5%, VCC, VOUT VCC, OE#/VPP OE#/VPP VIL,
VPPH
12.6 12.6
T8.1
TABLE PROGRAM/ERASE OPERATING CHARACTERISTICS SST27SF010/020 V±10%, VPPH,TA 25°C±5°C Limits Symbol Parameter Units Test Conditions Erase Program PGM# VIL, VIH, Current 12V±5%, Erase Program PGM# VIL, VIH, Current 12V±5%, VPPH Input Leakage Current Output Leakage Current Supervoltage Supervoltage Current High Voltage 11.4 12.6 12.6
T9.0 2000 Silicon Storage Technology, Inc. 502-03 2/00
VCC, VOUT VCC, VIL,
11.4
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ Power-up Read Operation TPU-WRITE Power-up Write Operation
Minimum
Units
T10.0
T11.0
TABLE CAPACITANCE MHz, other pins open) Parameter Description Test Condition CI/O Capacitance VI/O Input Capacitance CIN(1)
Note:
(1)This
Maximum
parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance Data Retention VZAP_HBM(1) Susceptibility Human Body Model VZAP_MM(1) Susceptibility Machine Model ILTH Latch
Note:
Minimum Specification 1000 1000
Units Cycles Years Volts Volts
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T12.0
This parameter measured only initial qualification after design process change that could affect this parameter.
CHARACTERISTICS TABLE READ CYCLE TIMING PARAMETERS ±10%, 70°C (Commercial) SST27SF256-70 SST27SF256-90 SST27SF512-70 SST27SF512-90 SST27SF010-70 SST27SF010-90 SST27SF020-70 SST27SF020-90 Symbol Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time TCLZ Active Output TOLZ Active Output TCHZ High High-Z Output TOHZ High High-Z Output Output Hold from Address Change
Note: 90ns,
Units
T13.0
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS SST27SF256 Symbol Parameter Address Setup Time Address Hold Time TPRT Pulse Rise Time TVPS Setup Time Hold Time TVPH Program Pulse Width Erase Pulse Width Data Setup Time Data Hold Time Recovery Time Rise Time during Erase TART TA9S Setup Time during Erase TA9H Hold Time during Erase TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS SST27SF512 Symbol Parameter Address Setup Time Address Hold Time TPRT OE#/VPP Pulse Rise Time TVPS OE#/VPP Setup Time TVPH OE#/VPP Hold Time Program Pulse Width Erase Pulse Width Data Setup Time Data Hold Time OE#/VPP Recovery Time TART Rise Time during Erase Setup Time during Erase TA9S TA9H Hold Time during Erase TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS SST27SF010/020 Symbol Parameter TCES Setup Time TCEH Hold Time Address Setup Time Address Hold Time TPRT Pulse Rise Time TVPS Setup Time TVPH Hold Time PGM# Program Pulse Width PGM# Erase Pulse Width Data Setup Time Data Hold Time Recovery Time Erase TART Rise Time during Erase TA9S Setup Time during Erase TA9H Hold Time during Erase
2000 Silicon Storage Technology, Inc.
Units
T14.0
Units
T15.0
Units
T16.0 502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
ADDRESS
TOHZ DATA VALID TCHZ DATA VALID
TOLZ
F03.0
DQ7-0
HIGH-Z TCLZ
FIGURE READ CYCLE TIMING DIAGRAM SST27SF256/512/010/020
ADDRESS (EXCEPT
DQ7-0 VPPH VPPH TART TA9S TPRT
TVPS TVPH
F04a.0
TA9H
FIGURE CHIP-ERASE TIMING DIAGRAM SST27SF256
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
ADDRESS (EXCEPT
DQ7-0
VPPH OE#/VPP VPPH TART TPRT
TVPS TVPH
TA9S
TA9H
F04b.0
FIGURE CHIP-ERASE TIMING DIAGRAM SST27SF512
ADDRESS (EXCEPT
TCEH
DQ7-0 VPPH VPPH TART TA9H PGM# TCES
F04c.0
TVPS TVPH TPRT TA9S
FIGURE CHIP-ERASE TIMING DIAGRAM SST27SF010/020
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
ADDRESS
ADDRESS VALID
DATA VALID
TVPS
DQ7-0
HIGH-Z VPPH
TPRT
TVPH
F05a.0
FIGURE BYTE-PROGRAM TIMING DIAGRAM SST27SF256
ADDRESS
ADDRESS VALID
DQ7-0
HIGH-Z
DATA VALID
VPPH OE#/VPP
TPRT
TVPS
TVPH
F05b.1
FIGURE BYTE-PROGRAM TIMING DIAGRAM SST27SF512
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
ADDRESS
ADDRESS VALID
TCEH
DQ7-0
HIGH-Z VPPH
DATA VALID
TVPS
PGM#
TPRT
TVPH
TCES
F05c.0
FIGURE BYTE-PROGRAM TIMING DIAGRAM SST27SF010/020
VIHT
INPUT REFERENCE POINTS
OUTPUT
VILT
F06.0
test inputs driven VIHT (2.4 logic VILT (0.4 logic "0". Measurement reference points inputs outputs (2.0 (0.8 Inputs rise fall times (10% 90%)
Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
TESTER HIGH
F07.0
FIGURE TEST LOAD EXAMPLE
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
VPPH,
Erase 100ms pulse (CE# VIL)
Wait Recovery Time
Read Device (CE# VIL)
Compare bytes
Device Passed
Device Failed
F08a.0
FIGURE CHIP-ERASE ALGORITHM SST27SF256
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
OE#/VPP VPPH
Erase 100ms pulse (CE# VIL)
OE#/VPP
Wait OE#/VPP Recovery Time Read Device (CE# VIL)
Compare bytes
Device Passed
Device Failed
F08b.0
FIGURE CHIP-ERASE ALGORITHM SST27SF512
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
VPPH
VIL, Erase 100ms pulse (PGM# VIL)
PGM#
Wait Recovery Time
Read Device
Compare bytes
Device Passed
Device Failed
F08c.0
FIGURE CHIP-ERASE ALGORITHM SST27SF010/020
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
Figure
Erase
VPPH
Address First Location
Program 20µs pulse (CE# VIL)
Increment Address
Last Address?
Wait RecoveryTime Read Device (CE# VIL)
Compare bytes original data
Device Passed
Device Failed
F09a.1
FIGURE BYTE-PROGRAM ALGORITHM SST27SF256
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
Erase
Figure
OE#/VPP VPPH
Address First Location
Program 20µs pulse (CE# VIL)
Increment Address
Last Address?
OE#/VPP
Wait OE#/VPP RecoveryTime Read Device (CE# VIL)
Compare bytes original data
Device Passed
Device Failed
F09b.0
FIGURE BYTE-PROGRAM ALGORITHM SST27SF512
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
Figure
Erase
VPPH
Address First Location
VIL,
Program 20µs pulse (PGM# VIL)
Increment Address
Last Address?
Read Device
Compare bytes original data
Device Passed
Device Failed
F09c.0
FIGURE BYTE-PROGRAM ALGORITHM SST27SF010/020
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet PRODUCT ORDERING INFORMATION
Device SST27SFxxx
Speed
Suffix1
Suffix2 Package Modifier pins pins Numeric modifier Package Type PDIP PLCC TSOP (die (8mm 14mm) Operating Temperature Commercial 70°C Industrial -40° 85°C Minimum Endurance 1000 cycles Read Access Speed Device Density Kilobit Kilobit Megabit Megabit
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet Valid combinations SST27SF256 SST27SF256- 70-3C-WH SST27SF256- 70-3C-NH SST27SF256- 90-3C-WH SST27SF256- 90-3C-NH SST27SF256- 70-3I-WH SST27SF256- 90-3I-WH SST27SF256- 70-3I-NH SST27SF256- 90-3I-NH SST27SF256- 70-3C-PG SST27SF256- 90-3C-PG
Valid combinations SST27SF512 SST27SF512- 70-3C-WH SST27SF512- 70-3C-NH SST27SF512- 90-3C-WH SST27SF512- 90-3C-NH SST27SF512- 70-3I-WH SST27SF512- 90-3I-WH SST27SF512- 70-3I-NH SST27SF512- 90-3I-NH
SST27SF512- 70-3C-PG SST27SF512- 90-3C-PG
Valid combinations SST27SF010 SST27SF010- 70-3C-WH SST27SF010- 70-3C-NH SST27SF010- 90-3C-WH SST27SF010- 90-3C-NH SST27SF010- 70-3I-WH SST27SF010- 90-3I-WH SST27SF010- 70-3I-NH SST27SF010- 90-3I-NH
SST27SF010- 70-3C-PH SST27SF010- 90-3C-PH
Valid combinations SST27SF020 SST27SF020- 70-3C-WH SST27SF020- 70-3C-NH SST27SF020- 90-3C-WH SST27SF020- 90-3C-NH SST27SF020- 70-3I-WH SST27SF020- 90-3I-WH SST27SF020- 70-3I-NH SST27SF020- 90-3I-NH
SST27SF020- 70-3C-PH SST27SF020- 90-3C-PH
Example:Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet PACKAGING DIAGRAMS
IDENTIFIER 1.05 0.95
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (min/max). Coplanarity: (±.05)
32.TSOP-WH-ILL.3
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
index
.600 .625 .530 .550
.065 .075
1.445 1.455
PLCS.
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600
.070 .080
.045 .065
.016 .022
.100
Note:
Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .010 inches.
28.pdipPG-ILL.1
28-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) PACKAGE CODE:
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
index
.600 .625 .530 .550
.065 .075
1.645 1.655
PLCS.
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600
.070 .080
.045 .065
.016 .022
.100
Note:
Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .010 inches.
32.pdipPH-ILL.1
32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) PACKAGE CODE:
SIDE VIEW BOTTOM VIEW
VIEW
Optional Identifier
.485 .495 .447 .453 .042 .048
.106 .112 .020 MAX. .023 .029 .030 .040
.490 .530
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
32.PLCC.NH-ILL.1
Note:
Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .008 inches.
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
2000 Silicon Storage Technology, Inc.
502-03 2/00
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
2000 Silicon Storage Technology, Inc.
502-03 2/00

Other recent searches


UT54ACS54 - UT54ACS54   UT54ACS54 Datasheet
UT54ACTS54 - UT54ACTS54   UT54ACTS54 Datasheet
RFD16N05L - RFD16N05L   RFD16N05L Datasheet
RFD16N05LSM - RFD16N05LSM   RFD16N05LSM Datasheet
MHW7185C - MHW7185C   MHW7185C Datasheet
LT3682 - LT3682   LT3682 Datasheet
LT3682 - LT3682   LT3682 Datasheet
LT3682EDE - LT3682EDE   LT3682EDE Datasheet
LT3682IDE - LT3682IDE   LT3682IDE Datasheet
EM641FP16 - EM641FP16   EM641FP16 Datasheet
DC-2 - DC-2   DC-2 Datasheet
CR-13 - CR-13   CR-13 Datasheet
BSR15 - BSR15   BSR15 Datasheet
BSR16 - BSR16   BSR16 Datasheet
AT45DB321 - AT45DB321   AT45DB321 Datasheet
ADG1604 - ADG1604   ADG1604 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive