BCM5228 10/100BASE-TX/FX Octal-Transceiver GENERAL DESCRIPTION BC
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FINAL DATA SHEET
BCM5228 10/100BASE-TX/FX Octal-Transceiver
GENERAL DESCRIPTION BCM5228 octal 10/100BASE-TX/FX transceiver targeted Fast Ethernet switches. device contains eight full-duplex 10BASE-T/100BASE-TX/FX Fast Ethernet transceivers, each which perform physical layer interface functions 10BASE-T Ethernet Category unshielded twisted pair (UTP) cable 100BASE-TX Fast Ethernet Category cable. 100BASE-FX supported each port through external fiber optic transmit receive devices. BCM5228 highly integrated solution combining digital adaptive equalizers, ADCs, phase locked loops, line drivers, encoders, decoders, required support circuitry into single monolithic CMOS chip. BCM5228 complies with IEEE 802.3 specification, including auto negotiation subsections. effective digital technology BCM5228 design results robust performance over broad range operating scenarios. Problems inherent mixed-signal implementations, such analog offset on-chip noise, eliminated employing field-proven digital adaptive equalization digital clock recovery techniques. FEATURES 10BASE-T/100BASE-TX/FX IEEE 802.3u compliant Single-chip octal physical interface-RMII magnetics Reduced Media Independent Interface (RMII) Option Serial Media Independent Interface (SMII) Option Source Synchronous SMII (S3MII) Fully integrated digital adaptive equalizers 125-MHz clock generator timing recovery On-chip multimode transmit waveshaping Edge-rate control eliminates external filters Integrated baseline wander correction Auto-MDIX Cable Length Indication Cable Noise Level Indication IEEE 802.3u-compliant auto negotiation Shared management interface Mbps Serial status pins Programmable parallel pins Interrupt output capability Loopback mode diagnostics IEEE 1149.1 (JTAG) NAND chain support Low-power dual-supply 2.5V/3.3V CMOS technology Compatible with 3.3V PQFP FPBGA packages APPLICATIONS Fast Ethernet switches
TXD[1:0] {1:8} {1:8}
Multimode
10BASE-T
TX_EN {1:8} TX_ER/LED1 {1:8}
Baseline Wander Correction
100BASE-X
Digital Adaptive Equalizer
CRS_DV {1:8} RX_ER {1:8} RXD[1:0] {1:8}
{1:8}
{1:8} REF_CLK
CRS/Link Detection
Auto Negotiation /Link Integrity Drivers Clock Recovery
SLED_DO/INTR
TXER/LED1 {1:8}
Clock Generator Bias Generator JTAG Test Logic
LED2 {1:8}
LED3 {1:8)
MODES MDIO
VREF RDAC JTAG
Registers
Mgmt Control
Figure
Functional Block Diagram
5228-DS05-R
16215 Alton Parkway P.O. 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
10/24/01
REVISION HISTORY
Revision
5228-DS01-R 5228-DS02-R 5228-DS03-R
Date
11/24/99 12/15/99 09/01/00
Change Description
Initial Release Added MDIX info page Minor editorial changes. Correct several signal name inconsistencies. Changed from PLLVDDP OVDD Table Figure Figure Figure Table Changed AGND from Table page Modified description "100BASE-FX Mode" page Changed "LED_CLK" "SLED_CLK" "Low-Cost Serial Mode" page Changed address Table page from Enable Reserved. Deleted Enable description Table page Added TX_ER parameter Table page Added CRS_DV, RX_ER, note Table page Changed SRD_Delay SRX_Delay Figure page Deleted reference IVDD Table page Added following list FEATURES Cover: Option Source synchronous SMII (S3MII) Auto-MDIX Cable Length Indication Cable Noise Level Indication. Following Table page deleted from Interrupt Enable description "Bits this register mutually exclusive. Only time." Table page inserted values parameters after TXEN Assert Steady State Delay. Table page added values parameter CRS_DV Assert after RD±, CRS_DV Deassert after RD±; CRS_DV Deassert after RD±, Valid EOP. Deleted last (parameter CRS_DV Steady State Delay). Table page added values Total Supply Current AVDD, DVDD OVDD pins. Added Section "Packaging Thermal Characteristics" page Corrected specification register 19h, from "jabber detect" "fullduplex indication." Added ordering information; added minor table information updates.
5228-DS04-R
03/15/01
5228-DS05-R 10/24/01
Final Data Sheet
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BCM5228
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Document 5228-DS05-R Page
Broadcom Corporation P.O. 57013 16215 Alton Parkway Irvine, California 92619-7013 2001 Broadcom Corporation rights reserved Printed U.S.A.
Broadcom® pulse logo® registered trademarks Broadcom Corporation and/or subsidiaries United States certain other countries. other trademarks property their respective owners.
Final Data Sheet
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BCM5228
TABLE CONTENTS
Section Functional Description.
Overview Encoder/Decoder Link Monitor Carrier Sense Auto Negotiation Digital Adaptive Equalizer Digital Clock Recovery/Generator Baseline Wander Correction Multimode Transmit Stream Cipher. Far-End Fault Reduced Media Independent Interface (RMII). Management Serial Media Independent Interface (SMII) Interrupt Mode
Section Hardware Signal Definition Table. Section Pinout Diagrams Section Operational Description
Resetting BCM5228 Isolate Mode Loopback Mode Full-duplex Mode. 100BASE-FX Mode 10BASE-T Mode Address
Section Modes
Description Serial mode.
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Low-Cost Serial Mode Parallel Mode
Section Register Summary
Management Interface: Register Programming.31 Register Summary.33 Control Register.36 Status Register Identifier Registers.39 Auto Negotiation Advertisement Register Auto Negotiation Link Partner (LP) Ability Register Auto Negotiation Expansion Register Auto Negotiation Next Page Register Auto Negotiation Link Partner (LP) Next Page Transmit Register.44 100BASE-X Auxiliary Control Register.45 100BASE-X Auxiliary Status Register.47 100BASE-X Receive Error Counter 100BASE-X False Carrier Sense Counter.48 100BASE-X Disconnect Counter Auxiliary Control/Status Register Auxiliary Status Summary Register.51 Interrupt Register.52 Auxiliary Mode Register.53 10BASE-T Auxiliary Error General Status Register Auxiliary Mode Register.55 Auxiliary Multiple Register Broadcom Test Register Auxiliary Mode (PHY Register (Shadow Register) Auxiliary Mode (PHY Register (Shadow Register) Auxiliary Mode (PHY Register (Shadow Register) Auxiliary Status Register (Shadow Register).60 Auxiliary Status Register (Shadow Register).60 Auxiliary Mode Register (Shadow Register) Auxiliary Status Register (Shadow Register).62
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BCM5228
Section Timing Characteristics Section Electrical Characteristics. Section Mechanical Information. Section Packaging Thermal Characteristics. Section Application Examples Section Ordering Information.
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LIST FIGURES
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Functional Block Diagram. BCM5228F Pinout Diagram.16 BCM5228U Pinout Diagram Pinout (Top View) Clock Reset Timing RMII Transmit Packet Timing RMII Receive Packet Timing RMII Receive Packet with False Carrier SMII/S3MII Timing Management Interface Timing.68
Figure Management Interface Timing (with Preamble Suppression Figure 208-Pin PQFP Figure Fine Pitch (FPBGA) Package Figure SMII Application.75 Figure SMII Application using Source Synchronous Signals Figure Switch Application
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BCM5228
LIST TABLES
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 4B5B Encoding Definitions Ballout Signal Name Serial Mode Framing. Low-Cost Serial Mode Bank Selection. Low-Cost Serial Mode Bank Selection. Low-Cost Serial Mode Bank Selection. Low-Cost Serial Mode Bank Selection. Low-Cost Serial Mode Bank Selection. Low-Cost Serial Mode Bank Selection. Parallel Mode LED1 Selection Parallel Mode LED2 Selection Parallel Mode LED3 Selection Management Frame Format Register Summary Shadow Register Summary (MII Register 1Fh, bit7 Control Register (Address 00d, 00h). Status Register (Address 01d, 01h) Identifier Registers (Addresses 03d, 03h) Auto Negotiation Advertisement Register (Address 04d, 04h). Auto Negotiation Link Partner Ability Register (Address 05d, 05h). Auto Negotiation Expansion Register (Address 06d, 06h). Next Page Transmit Register (Address 07d, 07h) Next Page Transmit Register (Address 08d, 08h) 100-BASE-X Auxiliary Control Register (Address 16d, 10h). 100BASE-X Auxiliary Status Register (Address 17d, 11h) 100BASE-X Receive Error Counter (Address 18d, 12h). 100BASE-X False Carrier Sense Counter (Address 19d, 13h). 100BASE-X Disconnect Counter Auxiliary Control/Status Register (Address 24d, 18h). Auxiliary Status Summary Register (Address 25d, 19h) Interrupt Register (Address 26d, 1Ah)
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Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Auxiliary Mode Register (Address 27d, 1Bh).53 10BASE-T Auxiliary Error General Status Register (Address 28d, 1Ch) Auxiliary Mode Register (Address 29d, 1Dh) Auxiliary Multiple Register (Address 30d, 1Eh) Broadcom Test (Address 31d, 1Fh) Auxiliary Mode (PHY Register (Shadow Register 26d, 1Ah).58 Auxiliary Mode (PHY Register (Shadow Register 26d, 1Ah).58 Auxiliary Mode (PHY Register (Shadow Register 26d, 1Ah).59 Auxiliary Status Register (Shadow Register 27d, 1Bh) Cable Length Auxiliary Status Register (Shadow Register 28d, 1Ch) Auxiliary Mode Register (Shadow Register 29d, 1Dh) Current Receive FIFO Size Auxiliary Status Register (Shadow Register 30d, 1Eh) Clock Timing.63 Reset Timing RMII Transmit Timing RMII Receive Timing SMII/S3MII Timing Auto Negotiation Timing Timing.67 Management Data Interface Timing Recommended Operating Conditions Electrical Characteristics Theta-JA Airflow BCM5228B (256 FPBGA) Package.73 Theta-JA Airflow BCM5228F (208 PQFP) Package Theta-JA Airflow BCM5228U (208 PQFP) Package.73
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BCM5228
OVERVIEW
BCM5228 single-chip device containing eight independent Fast Ethernet transceivers. Each transceiver performs physical layer interface functions 100BASE-TX full-duplex half-duplex Ethernet Category unshielded twisted pair (UTP) cable 10BASE-T full-duplex half-duplex Ethernet Category cable. Each port also configured 100BASE-FX full-duplex half-duplex transmission over fiber optic cabling when paired with external fiber optic line driver receiver. chip performs 4B5B, MLT3, NRZI, Manchester encoding decoding, clock data recovery, stream cipher scrambling/descrambling, digital adaptive equalization, line transmission, carrier sense link integrity monitor, auto negotiation, RMII SMII management functions. BCM5228 connected through RMII SMII side connected directly network media other side through isolation transformers modes, through fiber optic transmitter/receiver components mode. BCM5228 compliant with IEEE 802.3 standard.
ENCODER/DECODER
100BASE-TX 100BASE-FX modes, BCM5228 transmits receives continuous data stream twisted pair fiber optic cable. When RMII Transmit Enable asserted, data from transmit data pins encoded into 5-bit code groups inserted into transmit data stream. 4B5B encoding shown Table page transmit packet encapsulated replacing first nibbles preamble with start stream delimiter (J/K codes) appending stream delimiter (T/R codes) packet. transmitter repeatedly sends idle code group between packets. mode, encoded data stream scrambled stream cipher block then serialized encoded into MLT3 signal levels. multimode transmit used drive MLT3 data onto twisted pair cable. mode, scrambling function bypassed data NRZI encoded. multimode transmit drives differential positive (PECL) levels external fiber optic transmitter. Following baseline wander correction, adaptive equalization, clock recovery mode, receive data stream converted from MLT3 serial NRZI data. NRZI data descrambled stream cipher block then deserialized aligned into 5-bit code groups. mode, receive data stream differential PECL levels sampled from fiber optic receiver. Baseline wander correction, adaptive equalization, stream cipher descrambling functions bypassed, NRZI decoding used instead MLT3. 5-bit code groups decoded into 4-bit data nibbles, shown Table page start-of-stream delimiter replaced with preamble nibbles end-of-stream delimiter idle codes replaced with zeros. decoded data driven onto RMII/SMII receive data pins. When invalid code group detected data stream, BCM5228 asserts RMII/SMII RXER signal. chip also asserts RXER several other error conditions that improperly terminate data stream. While RXER asserted, receive data pins driven with invalid data reception false carrier. 10BASE-T mode, Manchester encoding decoding performed data stream. multimode transmit performs pre-equalization meters Category cable.
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LINK MONITOR
100BASE-TX mode, receive signal energy detected monitoring receive pair transitions signal level. Signal levels qualified using squelch detect circuits. When signal certain invalid signals detected receive pair, link monitor enters remains Link Fail state where only idle codes transmitted. When valid signal detected receive pair minimum period time, link monitor enters Link Pass state transmit receive functions enabled. 100BASE-FX mode, external fiber optic receiver performs signal energy detection function communicates this information directly BCM5228 through differential pins. 10BASE-T mode, link-pulse detection circuit constantly monitors pins presence valid link pulses.
CARRIER SENSE
mode, carrier sense receive data valid signals multiplexed same pin. carrier sense asserted asynchronously CRS_DV soon valid activity detected receive data stream. Loss carrier results deassertion CRS_DV synchronous cycle REF_CLK that presents first di-bit nibble onto RXD. additional bits presented following initial deassertion CRS_DV, asserts CRS_DV cycles REF_CLK that present second di-bit each nibble, deasserts CRS_DV cycles REF_CLK that present first di-bit each nibble. carrier sense asserted valid detected immediately, RXER asserted. value hex) driven receive data pins indicate false carrier sense. 10BASE-T mode, carrier sense asserted asynchronously when valid preamble activity detected input pins.
AUTO NEGOTIATION
BCM5228 contains ability negotiate mode operation over twisted pair link using auto negotiation mechanism defined IEEE 802.3u specification. Auto negotiation enabled disabled hardware software control. When auto negotiation function enabled, BCM5228 automatically chooses mode operation advertising abilities comparing them with those received from link partner. BCM5228 configured advertise 100BASE-TX full-duplex and/or half-duplex 10BASE-T full-duplex and/or half-duplex. Each transceiver negotiates independently with link partner chooses highest level operation available link.
DIGITAL ADAPTIVE EQUALIZER
digital adaptive equalizer removes interzonal interference created transmission channel media. equalizer accepts sampled unequalized data from each channel produces equalized data. BCM5228 achieves optimum signal noise ratio using combination feed-forward equalization decision-feedback equalization. This powerful technique achieves 100BASE-TX less than 10-12 transmission meters Category twisted pair cable, even harsh noise environments. digital adaptive equalizers BCM5228 achieve performance close theoretical limits. all-digital nature design makes performance very tolerant on-chip noise. filter coefficients self adapting quality cable cable length. Because transmit pre-equalization 10BASE-T mode complete lack 100BASE-FX mode, adaptive equalizer bypassed this mode operation.
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BCM5228
Each receive channel 125-MHz analog digital converter (ADC). samples incoming data receive channel produces digital output. output digital adaptive equalizer. Advanced analog circuit techniques achieve offset, high power supply noise rejection, fast settling time, error rate (BER).
DIGITAL CLOCK RECOVERY/GENERATOR
all-digital clock recovery generator block creates internal transmit receive clocks. transmit clocks locked 50-MHz clock input, while receive clocks locked incoming data streams. Clock recovery circuits optimized MLT3, NRZI, Manchester encoding schemes included with each three different operating modes. input data streams sampled recovered clock from each port synchronously respective digital adaptive equalizer.
BASELINE WANDER CORRECTION
100BASE-TX data stream always balanced. Because receive signal must pass through transformer, offset differential receive input wander. This effect, known baseline wander, greatly reduce noise immunity receiver. BCM5228 automatically compensates baseline wander removing offset from input signal, thereby significantly reducing chance receive symbol error. baseline wander correction circuit required, therefore bypassed, 10BASE-T 100BASE-FX operating modes
Table 4B5B Encoding Name
Code
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Code
11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101
Meaning
Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
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Table 4B5B Encoding (Cont.) Name
Code
0000* 0101* 0101* 0000* 0000* 1000 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111
Code
11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001
Meaning
Idle Start-of-stream delimiter, part Start-of-stream delimiter, part End-of-stream delimiter, part End-of-stream delimiter, part Transmit error (used force signalling errors) Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid Code Invalid Code Invalid Code
Treated invalid code (mapped 0111) when received data field.
MULTIMODE TRANSMIT
multimode transmit digital analog converter (DAC) transmits MLT3-coded symbols 100BASE-TX mode, NRZIcoded symbols 100BASE-FX mode Manchester-coded symbols 10BASE-T mode. performs programmable edgerate control mode, which decreases unwanted high frequency signal components thus reducing EMI. High-frequency pre-emphasis performed 10BASE-T mode; filtering performed 100BASE-FX mode. transmit utilizes current drive output which well balanced produces very noise transmit signals. PECL voltage levels produced with resistive terminations 100BASE-FX mode.
STREAM CIPHER
100BASE-TX mode, transmit data stream scrambled order reduce radiated emissions twisted pair cable. data scrambled exclusive ORing NRZI signal with output 11-bit wide linear feedback shift register (LFSR), which produces 2047-bit non-repeating sequence. scrambler reduces peak emissions randomly spreading signal energy over transmit frequency range, eliminating peaks certain frequencies. Signal energy spread further using unique seeds generate different non-repeating sequence each eight ports. receiver descrambles incoming data stream exclusive ORing with same sequence generated transmitter. descrambler detects state transmit LFSR looking sequence representing consecutive idle codes. descrambler will "lock" scrambler state after detecting sufficient number consecutive idle code-groups. receiver will attempt decode data stream unless descrambler locked. Once locked, descrambler continuously monitors data stream make sure that lost synchronization. receive data stream expected
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BCM5228
contain inter-packet idle periods. descrambler does detect enough idle codes within microseconds, becomes "unlocked", receive decoder disabled. receiver into Token Ring mode (see reg. 1Bh), descrambler monitors receiver 5792 microseconds before unlocking. descrambler always forced into unlocked state when link failure condition detected. Stream cipher scrambling/descrambling used 100BASE-FX 10BASE-T modes.
FAR-END FAULT
Auto negotiation provides Remote Fault capability detection asymmetric link failures. Because auto negotiation available 100BASE-FX, BCM5228 implements IEEE 802.3 standard Far-End Fault mechanism indication detection remote error conditions. Far-End Fault mechanism enabled, transceiver transmits Far-End Fault indication whenever receive channel failure detected (signal detect deasserted). Each transceiver also continuously monitors receive channel when valid signal present (signal detect asserted). When link partner indicating remote error, transceiver forces link monitor into link fail state Remote Fault RMII status register. Far-End Fault mechanism default 100BASE-FX mode default 100BASE-TX 10BASE-T modes, controlled software after reset.
REDUCED MEDIA INDEPENDENT INTERFACE (RMII)
interface BCM5228 based count (Reduced) Media Independent Interface (RMII) developed RMII Consortium. copy specification found consortium site http://www.rmii-consort.com. purpose this interface provide low-cost alternative IEEE 802.3u[2] Media Independent Interface (MII). RMII capable supporting megabit megabit data rates with single clock, using independent 2-bit wide transmit receive paths. single 50-MHz synchronous reference clock used timing reference transmitters receivers. doubling clock frequency relative MII, four pins saved data path, which uses lines into each transmitter lines each receiver, compared four lines used each direction MII. Since start-of-packet end-ofpacket timing information preserved across interface, able derive signal from receive transmit data delimiters, saving another pin. Transmit receive clocks have been eliminated well. data transfers synchronous with REF_CLK. This poses less challenge transmitter than does receiver, which required buffer output data FIFO until edge REF_CLK suitably aligned. received data bits RX_DV signal passed through FIFO; CRS_DV not. asserted time wire receiving frame. remote transmitter idle, data need passed from receiver, status information made available setting Register 10h. Out-of-band signaling consists di-bit pairs immediately following last di-bit pair received packet. di-bit pairs consist "full-duplex, Link Speed msb, lsb" "RXER, FIFO Error msb, lsb."
MANAGEMENT
Management each transceiver within BCM5228 remains same under specification. Each contains independent management registers. They share single MDC/MDIO serial interface. Each transceiver unique address must accessed individually. common base address group eight individual transceivers defined configuring five external PHYAD address input pins.
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SERIAL MEDIA INDEPENDENT INTERFACE (SMII)
SMII alternative both RMII. objective reduce number pins required interconnect PHY. This accomplished clocking data control signals each pair pins rate MHz. SMII mode selected pulling SMII_EN high during power-on reset. Data control signals passing from serial transmit (STX) line; data control signals passing from serial receive (SRX) line. transfers synchronous with clock (SCLK) MHz; frame synchronization provided fourth line (SYNC), asserted beginning each frame, which occurs every cycles SCLK. Each provided with pair. Pins TXD0{x} RXD0{x}, where number specific PHY, used perform functions. BCM5228 chip single SCLK SYNC input that common PHYs. Pins REF_CLK SSYNC used these functions. Receive data control information passed from frames. Mbps mode, each frame represents byte data. Mbps mode, each byte data repeated times; sample every frames. Since timing data coming from remote transmitter synchronized with local SCLK SYNC lines contain errors frequency, FIFO capable storing bits provided each receive path. received data bits RX_DV signal passed through FIFO; not. asserted time wire receiving frame. remote transmitter idle data need passed from receiver, status information becomes available. Transmit data control information passed from frames, receive path. Mbps mode, each frame represents byte data. Mbps mode, each byte data repeated times; transmit every frames.
INTERRUPT MODE
BCM5228 programmed provide interrupt output consisting eight interrupts, from each PHY. interrupt feature disabled default. interrupt capability enabled setting register 1Ah, SLED_DO becomes INTR# pin, when SERIAL_EN pulled during power-up reset. serial mode required, hardware interrupt obtained wire ORing LED2{1:8} open drain outputs programming LED2 output interrupt setting TXER/LED1{5:3} pins during power-on reset. status each interrupt source also reflected Register 1Ah, bits sources interrupt change link, speed full-duplex status. type interrupt occurs, Interrupt Status bit, Register 1Ah, set. addition, each transceiver register controlling interrupt function. interrupt enable status bits sets, interrupts generated. interrupt enable following conditions apply: mask status bits interrupt mask status bits interrupts generated. mask status bits interrupt mask status bits interrupts available. mask status bits interrupt mask status bits interrupts available.
Changes from active inactive vice versa causes interrupt. Setting Register 1Ah, high masks interrupts, regardless settings individual mask bits.
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BCM5228
Hardwa
Table Definitions BCM5228B BCM5228F BCM5228U Label Description
Media Connections A12,B12 A11,B11 A08,B08 A07,B07 T06,R06 T07,R07 T10,R10 T11,R11 A13,B13 A10,B10 A09,B09 A06,B06 T05,R05 T08,R08 T09,R09 T12,R12 D12,E12 D11,E11 D08,E08 E07,D07 N09,M09 N10,M10 N11,M11 N12,M12 166,167 178,177 184,185 196,195 64,65 76,75 82,83 94,93 164,165 180,179 182,183 198,197 62,63 78,77 80,81 96,95 171,170 173,174 189,188 191,192 69,68 71,72 87,86 89,90 165,166 173,172 179,180 198,197 62,63 81,80 87,88 95,94 163,164 175,174 177,178 200,199 60,61 83,82 85,86 97,96 RD+{1}, RD-{1} RD+{2}, RD-{2} RD+{3}, RD-{3} RD+{4}, RD-{4} RD+{5}, RD-{5} RD+{6}, RD-{6} RD+{7}, RD-{7} RD+{8}, RD-{8} TD+{1}, TD-{1} TD+{2}, TD-{2} TD+{3}, TD-{3} TD+{4}, TD-{4} TD+{5}, TD-{5} TD+{6}, TD-{6} TD+{7}, TD-{7} TD+{8}, TD-{8} SD+{1}, SD-{1} SD+{2}, SD-{2} SD+{3}, SD-{3} SD+{4}, SD-{4} SD+{5}, SD-{5} SD+{6}, SD-{6} SD+{7}, SD-{7} SD+{8}, SD-{8}
Receive Pair. Differential data from media received signal pair.
Transmit Pair. Differential data transmitted media signal pair.
100BASE-FX Signal Detect. Indicates signal quality status fiber-optic link 100BASEFX mode. When signal quality good, should driven high relative pin. 100BASE-FX mode disabled when both pins simultaneously pulled left unconnected.
Reduced Media Independent Interface (RMII) Reference Clock Input. This must driven with continuous 50-MHz clock RMII application SMII application. provides timing CRS_DV, RXD1, RXD0, TX_EN, TXD1,TXD0, RX_ER. Accuracy shall ppm, with duty cycle between inclusive.
REF_CLK
active low, digital input, digital output, bidirectional, analog input, analog output, digital input internal pull-up, digital input internal pull-down, open-drain output, three-state output, I/OPD bidirectional internal pull-down, bias. naming convention: label followed {Port
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Table Definitions (Cont.) BCM5228B
BCM5228F
BCM5228U
Label
Description
Transmit Enable. RMII mode,active high indicates that presenting di-bits TXD1,TXD0 transmission. TX_EN asserted synchronously with first nibble preamble remains asserted while di-bits transmitted presented RMII. TX_EN transitions synchronously with respect REF_CLK.
TX_EN{1:8}
TXD1{1} TXD0{1} TXD1{2} TXD0{2} TXD1{3} TXD0{3} TXD1{4} TXD0{4} TXD1{5} TXD0{5} TXD1{6} TXD0{6} TXD1{7} TXD0{7} TXD1{8} TXD0{8}
Transmit Data Input. RMII mode, TXD1,TXD0 dibit wide data input these pins transmission PHY. data synchronous with REF_CLK. TXD1 most significant bit. Values other than TXD1,TXD0 while TX_EN deasserted ignored PHY. SMII mode, TXD0{1:8} form STXD pins each PHY.
CRS_DV{1:8}
Carrier Sense/Receive Data Valid. RMII mode, CRS_DV shall asserted when medium non-idle. data RXD1,RXD0 considered valid once CRS_DV asserted. During false carrier event, CRS_DV shall remain asserted duration carrier activity. CRS_DV synchronized with respect REF_CLK.
active low, digital input, digital output, bidirectional, analog input, analog output, digital input internal pull-up, digital input internal pull-down, open-drain output, three-state output, I/OPD bidirectional internal pull-down, bias. naming convention: label followed {Port
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BCM5228
Table Definitions (Cont.) BCM5228B
BCM5228F
BCM5228U
Label
RXD1{1} RXD0{1} RXD1{2} RXD0{2} RXD1{3} RXD0{3} RXD1{4} RXD0{4} RXD1{5} RXD0{5} RXD1{6} RXD0{6} RXD1{7} RXD0{7} RXD1{8} RXD0{8}
Description
Receive Data Outputs. RMII mode, RXD1,RXD0 data output synchronous with REF_CLK. each clock period which CRS_DV asserted, RXD1,RXD0 transfers bits data from PHY. RXD1 most significant bit. SMII mode, RXD0{1:8} form SRXD pins each PHY.
RX_ER{1:8}
Receive Error Detected. RMII mode, RX_ER asserted high more REF_CLK periods indicate that error detected somewhere frame presently being transferred from PHY. RX_ER transitions synchronously with respect REF_CLK.
Serial Media Independent Interface (SMII) SMII Enable. Active high. active high being left unconnected during power-on reset selects SMII mode, while active selects RMII mode. Serial clock. After power-on reset, Serial Low-Cost Serial mode enabled, this sources clock serial data SLED_DO. Refer Section "LED Modes" details. SMII SYNC. SMII mode, this must connected free running sync pulse occurring every clock cycles. RMII mode, this Connect). SSYNC Data controls transferred through TXD0 RXD0 between respective default SMII mode. source synchronous enable, SSMII_EN, high, then SSYNC provides sync TXD0 only SMII_RSYNC from BCM5228 provides sync RXD0.
SMII_EN/ SLED_CLK
I/OPU
active low, digital input, digital output, bidirectional, analog input, analog output, digital input internal pull-up, digital input internal pull-down, open-drain output, three-state output, I/OPD bidirectional internal pull-down, bias. naming convention: label followed {Port
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Table Definitions (Cont.) BCM5228B BCM5228F BCM5228U Label Description
SMII Source Synchronous (S3MII) Enable. Active high. When S3MII enabled, BCM5228 provides source synchronous receive clock (SMII_RXC) sync (SMII_RSYNC) use. BCM5228 uses SMII_TXC along with SSYNC receive data from MAC. Signals CRS_DV, TXER, TXEN, RXER used when Source Synchronous mode enabled. SMII Source Synchronous Receive Clock. Optional 125-MHz clock SMII mode clock RXD0. SMII Source Synchronous SYNC. S3MII mode, this provides source synchronous SYNC pulse RXD0 Source Synchronous enabled. SMII Source Synchronous Transmit Clock. 125-MHz clock SMII mode BCM5228 clock TXD0 Source Synchronous enabled.
SSMII_EN
SMII_RXC
SMII_RSYNC
SMII_TXC
Management Data I/OPU Management Data I/O. This serial input/output used read from write RMII registers. data value MDIO valid latched rising edge MDC. Management Data Clock. clock input must provided allow RMII management functions. Clock frequencies supported. ADdress Selects. These inputs base address management addresses. Also serve test control inputs along with TESTEN select NAND-chain test mode. Master Address Mode. Active high. This forces address global write address PHYs within BCM5228. active high during power-on reset selects master address mode, while active being left unconnected selects normal address mode. Serial Frame. After power-on reset, this sources serial frame output signal serial mode enabled. Mode
MDIO
PHYAD{4:0}
MASTERPHY/ SFRAME
I/OPD
active low, digital input, digital output, bidirectional, analog input, analog output, digital input internal pull-up, digital input internal pull-down, open-drain output, three-state output, I/OPD bidirectional internal pull-down, bias. naming convention: label followed {Port
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Page Section Hardware Signal Definition Table Document 5228-DS05-R
Final Data Sheet
10/24/01
BCM5228
Table Definitions (Cont.) BCM5228B
BCM5228F
BCM5228U
Label
RESET#
Description
Reset. Active Low. Resets BCM5228. included NAND chain. 10/100 Mode Select. When high ANEN low, transceivers forced 100BASE-X operation. When ANEN low, transceivers forced 10BASE-T operation. When ANEN high, F100 effect operation. Auto Negotiation Enable. Active high. When pulled high, auto negotiation begins immediately after reset. When low, auto negotiation disabled after reset. Auto negotiation enabled under software control (Register auto negotiation enabled through hardware. Full-Duplex Mode Enable. FDXEN logically ORed with control generate internal full-duplex enable signal. When FDXEN high, BCM5228 operate full-duplex mode determined auto negotiation. When FDXEN low, internal control (Register determines fullduplex operating mode. Initial value internal control zero. TXER Enable. Active high. When pulled high during power-on reset, TXER[1:8]/LED1[1:8] pins become TXER[1:8] input. Otherwise they become LED1[1:8] output. Auto-MDIX Disable. Active high. When pulled high during reset, automatic cable swap detection function BCM5228 disabled. Leave this unconnected normal operation. Test Enable. Active high test control input used along with PHYAD[4:0] select NAND-chain test mode. This test mode latched when TESTEN pulsed high, then low, with PHYAD[4:0]=10111. This included NAND chain must pulled left unconnected during normal operation.
F100
ANEN
FDXEN
TXER_EN
I/OPU
MDIX_DIS
I/OPD
TESTEN
active low, digital input, digital output, bidirectional, analog input, analog output, digital input internal pull-up, digital input internal pull-down, open-drain output, three-state output, I/OPD bidirectional internal pull-down, bias. naming convention: label followed {Port
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Document 5228-DS05-R Section Hardware Signal Definition Table Page
BCM5228
Final Data Sheet
10/24/01
Table Definitions (Cont.) BCM5228B
Serial Enable. Active high. Serial mode enabled this high LC-SER_EN during power-on reset. Serial mode Low-Cost Serial mode cannot active same time. Refer Section "LED Modes" page details. Low-Cost Serial Enable. Active high. LowCost Serial mode enabled this high SER_EN high during power-on reset. Low-Cost Serial mode Serial mode active same time. Section "LED Modes" page details. Serial Data. Active serial data. This becomes serial data output SER_EN high during power-on reset. Section "LED Modes" page details. Interrupt. Active output. This becomes interrupt output SER_EN during power-on reset. TXER[1:8]. Active high input. This becomes TXER input TXER_EN high during poweron reset. TXER function typically used HSTR application transmitting halt codes. TXER[1:8] pins sampled during power-on reset default output LED1, LED2 LED3. Section "LED Modes" page details. LED1[1:8]. Active output. This becomes LED1 output TXER_EN during power-on reset. LED1 configured output LINK, SPEED, ACTIVITY, FULLDUPLEX, TRANSMIT, RECEIVE, INTERRUPT COLLISION status. Section "LED Modes" page details.
BCM5228F
BCM5228U
Label
Description
SERIAL_EN
I/OPD
LC_SER_EN
I/OPU
SLED_DO INTR#
TX_ER{1:8} LED1{1:8}
I/OPD
LED2{1:8}
LED2. Active low. This configured output SPEED, ACTIVITY, FULLDUPLEX, TRANSMIT, RECEIVE, INTERRUPT, COLLISION, LINK status. Section "LED Modes" page details.
active low, digital input, digital output, bidirectional, analog input, analog output, digital input internal pull-up, digital input internal pull-down, open-drain output, three-state output, I/OPD bidirectional internal pull-down, bias. naming convention: label followed {Port
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Page Section Hardware Signal Definition Table Document 5228-DS05-R
Final Data Sheet
10/24/01
BCM5228
Table Definitions (Cont.) BCM5228B
Bias Bias Resistor. Adjusts current level each transmit DAC's. resistor 1.24 must connected between RDAC AGND. Voltage Reference. Low-impedance bias driven internal band-gap voltage reference. This must left unconnected during normal operation.
BCM5228F
BCM5228U
Label
Description
LED3{1:8}
LED3. Active low. function this signal configured output ACTIVITY, FULL-DUPLEX, LINK SPEED status. Refer Section "LED Modes" page details.
RDAC
VREF
JTAG Test Mode Select. Serial data input JTAG controller. Sampled rising edge TCK. unused, left unconnected. Test Data Input. Single control input JTAG controller used traverse test-logic state machine. Sampled rising edge TCK. unused, left unconnected. Test Clock. Clock input used synchronize JTAG control data transfers. unused, left unconnected. Test Data Output. Serial data output from JTAG Controller. Updated falling edge TCK. Actively driven both high when enabled; high impedance otherwise. Test Reset. Asynchronous active-low reset input JTAG Controller. Must held during power-up insure Controller initializes test-logic-reset state. pulled continuously when JTAG functions used. Must held normal operation.
TRST#
Power PLLVDDC PLLGND BIASVDD 2.5V, Phase Locked Loop Core (VDDC) Phase Locked Loop 2.5V, Bias
active low, digital input, digital output, bidirectional, analog input, analog output, digital input internal pull-up, digital input internal pull-down, open-drain output, three-state output, I/OPD bidirectional internal pull-down, bias. naming convention: label followed {Port
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Document 5228-DS05-R Section Hardware Signal Definition Table Page
BCM5228
Final Data Sheet
10/24/01
Table Definitions (Cont.) BCM5228B
BCM5228F
BCM5228U
Label
BIASGND
Description
Bias
AVDD
2.5V, Analog
AGND
Analog
DVDD
2.5V, Digital Core
DGND
Digital Core
active low, digital input, digital output, bidirectional, analog input, analog output, digital input internal pull-up, digital input internal pull-down, open-drain output, three-state output, I/OPD bidirectional internal pull-down, bias. naming convention: label followed {Port
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Page Section Hardware Signal Definition Table Document 5228-DS05-R
Final Data Sheet
10/24/01
BCM5228
Table Definitions (Cont.) BCM5228B
BCM5228F
BCM5228U
Label
Description
OVDD
3.3V, Digital Periphery (Output Buffer)
OGND
Digital Periphery (Output Buffer)
active low, digital input, digital output, bidirectional, analog input, analog output, digital input internal pull-up, digital input internal pull-down, open-drain output, three-state output, I/OPD bidirectional internal pull-down, bias. naming convention: label followed {Port
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Document 5228-DS05-R Section Hardware Signal Definition Table Page
BCM5228
Final Data Sheet
10/24/01
Figure provides pinout diagram BCM5228F Support).
TXEN{3} TXEN{4} CRS_DV{1} CRS_DV{2} CRS_DV{3} CRS_DV{4} OGND AGND TD+{4} TD-{4} RD+{4} RD-{4} AGND AVDD SD-{4} SD+{4} AGND SD+{3} SD-{3} AVDD AGND RD-{3} RD+{3} TD-{3} TD+{3} AGND TD+{2} TD-{2} RD+{2} RD-{2} AGND AVDD SD-{2} SD+{2} AGND SD+{1} SD-{1} AVDD AGND RD-{1} RD+{1} TD-{1} TD+{1} BIASGND VREF RDAC BIASVDD RESET#
DGND DVDD TXEN{2} TXEN{1} RXER{4} RXER{3} RXER{2} RXER{1} TXER{4} TXER{3} TXER{2} TXER{1} OVDD DGND DVDD OVDD TESTEN LC_SER_EN TXER_EN MDIX_DIS SER_EN MASTERPHY SMII_EN PHYAD4 PHYAD3 PHYAD2 PHYAD1 PHYAD0 SLED_DO MDIO TRST# OGND OVDD RXER{8} RXER{7} RXER{6} RXER{5} TXER{8} TXER{7} TXER{6} TXER{5} DVDD DGND TXEN{8} TXEN{7} TXEN{6}
BCM5228F (Top View)
FDXEN DGND DVDD OGND RXD0{1} RXD1{1} TXD0{1} TXD1{1} RXD0{2} RXD1{2} TXD0{2} TXD1{2} OVDD OVDD RXD0{3} RXD1{3} TXD0{3} TXD1{3} RXD0{4} RXD1{4} TXD0{4} TXD1{4} OGND DGND DVDD OGND RXD0{5} RXD1{5} TXD0{5} TXD1{5} RXD0{6} RXD1{6} TXD0{6} TXD1{6} OVDD OVDD RXD0{7} RXD1{7} TXD0{7} TXD1{7} RXD0{8} RXD1{8} TXD0{8} TXD1{8} OGND DVDD DGND F100 ANEN SMII_RSYNC SMII_RXC SSYNC
Page Section Pinout Diagrams
TXEN{5} CRS_DV{8} CRS_DV{7} CRS_DV{6} CRS_DV{5} OGND AGND TD+{5} TD-{5} RD+{5} RD-{5} AGND AVDD SD-{5} SD+{5} AGND SD+{6} SD-{6} AVDD AGND RD-{6} RD+{6} TD-{6} TD+{6} AGND TD+{7} TD-{7} RD+{7} RD-{7} AGND AVDD SD-{7} SD+{7} AGND SD+{8} SD-{8} AVDD AGND RD-{8} RD+{8} TD-{8} TD+{8} AGND PLLGND REF_CLK OVDD PLLVDDC SSMII_EN SMII_TXC
Figure
BCM5228F Pinout Diagram
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Final Data Sheet
10/24/01
BCM5228
Figure provides pinout diagram BCM5228U (UTP Support).
TXEN{3} TXEN{4} CRS_DV{1} CRS_DV{2} CRS_DV{3} CRS_DV{4} OGND AGND TD+{4} TD-{4} RD+{4} RD-{4} AGND AVDD AGND OGND LED3#{4} LED3#{3} LED3#{2} LED3#{1} LED2#{4} LED2#{3} LED2#{2} LED2#{1} OVDD AGND AVDD AGND RD-{3} RD+{3} TD-{3} TD+{3} AGND TD+{2} TD-{2} RD+{2} RD-{2} AGND AVDD AGND AVDD AGND RD-{1} RD+{1} TD-{1} TD+{1} BIASGND VREF RDAC BIASVDD RESET#
DGND DVDD TXEN{2} TXEN{1} RXER{4} RXER{3} RXER{2} RXER{1} TXER{4} TXER{3} TXER{2} TXER{1} OVDD DGND DVDD OVDD TESTEN
LC_SER_EN
TXER_EN MDIX_DIS SER_EN MASTERPHY SMII_EN PHYAD4 PHYAD3 PHYAD2 PHYAD1 PHYAD0 SLED_DO MDIO TRST# OGND OVDD RXER{8} RXER{7} RXER{6} RXER{5} TXER{8} TXER{7} TXER{6} TXER{5} DVDD DGND TXEN{8} TXEN{7} TXEN{6}
BCM5228U (Top View)
FDXEN DGND DVDD OGND RXD0{1} RXD1{1} TXD0{1} TXD1{1} RXD0{2} RXD1{2} TXD0{2} TXD1{2} OVDD OVDD RXD0{3} RXD1{3} TXD0{3} TXD1{3} RXD0{4} RXD1{4} TXD0{4} TXD1{4} OGND DGND DVDD OGND RXD0{5} RXD1{5} TXD0{5} TXD1{5} RXD0{6} RXD1{6} TXD0{6} TXD1{6} OVDD OVDD RXD0{7} RXD1{7} TXD0{7} TXD1{7} RXD0{8} RXD1{8} TXD0{8} TXD1{8} OGND DVDD DGND F100 ANEN SMII_RSYNC SMII_RXC SSYNC
Document
5228-DS05-R
TXEN{5} CRS_DV{8} CRS_DV{7} CRS_DV{6} CRS_DV{5} OGND AGND TD+{5} TD-{5} RD+{5} RD-{5} AGND AVDD AGND OVDD LED2#{5} LED2#{6} LED2#{7} LED2#{8} LED3#{5} LED3#{6} LED3#{7} LED3#{8} OGND AGND AVDD AGND RD-{6} RD+{6} TD-{6} TD+{6} AGND TD+{7} TD-{7} RD+{7} RD-{7} AGND AVDD AGND AVDD AGND RD-{8} RD+{8} TD-{8} TD+{8} AGND PLLGND REF_CLK OVDD PLLVDDC SSMII_EN SMII_TXC
Figure
BCM5228U Pinout Diagram
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Section Pinout Diagrams Page
BCM5228
Final Data Sheet
10/24/01
CRS_DV
CRS_DV
CRS_DV
TXEN{4}
AVDD
TD+{4}
RD+{4}
RD+{3}
TD+{3}
TD+{2}
RD+{2}
RD+{1}
TD+{1}
VREF
RDAC
BIASVDD
TXEN{3}
TXEN{2}
LED3{2}
CRS_DV
AGND
TD-{4}
RD-{4}
RD-{3}
TD-{3}
TD-{2}
RD-{2}
RD-{1}
TD-{1}
AGND
AGND
BIASGND
RXER{4}
RXER{3}
TXEN{1}
LED2{1}
LED2{4}
AGND
AVDD
AGND
AGND
AVDD
AGND
AGND
AVDD
DGND
FDXEN
RESET#
RXER{2}
RXER{1}
LED3{1}
LED3{4}
LED2{3}
OVDD
SD-{4}
SD+{3}
AGND
AGND
SD+{2}
SD+{1}
OGND
RXD1{1}
RXD0{1}
TXD1{1}
TX_ER{3}/ TX_ER{4}/ LED1{3} LED1{4}
OVDD
DVDD
LED3{3}
LED2{2}
SD+{4}
SD-{3}
AGND
SD-{2}
SD-{1}
DVDD
RXD1{2}
RXD0{2}
TXD0{1}
TX_ER{1}/ TX_ER{2}/ LED1{1} LED1{2}
DGND
TESTEN
MDIX_DIS
OGND
OGND
TGND
TGND
TGND
TGND
RXD1{3}
RXD0{3}
OVDD
TXD1{2}
TXD0{2}
TXER_EN
LC_SER_ SERIAL_EN
DVDD
PHYAD4
DGND
TGND
TGND
TGND
TGND
TGND
RXD1{4}
OVDD
RXD0{4}
TXD1{3}
TXD0{3}
SMII_EN/ MASTERP SLED_CL SFRAME
OVDD
PHYAD2
PHYAD3
TGND
TGND
TGND
TGND
TGND
OGND
RXD1{5}
RXD0{5}
OGND
TXD1{4}
TXD0{4}
MDIO
PHYAD0
OGND
PHYAD1
TGND
TGND
TGND
TGND
TGND
TGND
RXD1{6}
DGND
RXD0{6}
TXD1{5}
TXD0{5}
SLED_DO/ INTR#
OVDD
TRST#
TGND
TGND
TGND
TGND
TGND
TGND
RXD1{7}
RXD0{7}
DVDD
TXD1{6}
TXD0{6}
RXER{8}
DVDD
OGND
OGND
TGND
TGND
TGND
TGND
RXD1{8}
OVDD
RXD0{8}
TXD1{7}
TXD0{7}
RXER{6}
RXER{7}
DGND
LED3{8}
LED3{5}
LED2{7}
LED2{5}
SD-{5}
SD-{6}
SD-{7}
SD-{8}
ANEN
OVDD
TXD1{8}
TXD0{8}
TX_ER{8}/ TX_ER{7}/ LED1{8} LED1{7}
RXER{5}
LED3{6}
LED3{7}
LED2{8}
LED2{6}
OVDD
SD+{5}
SD+{6}
SD+{7}
SD+{8}
DVDD
DGND
F100
OGND
TX_ER{5}/ TX_ER{6}/ LED1{5} LED1{6}
TXEN{8}
TXEN{7}
AGND
AGND
AVDD
AGND
AGND
AGND
AVDD
AGND
AGND
OVDD
SSYNC
SMII_ RSYNC
TXEN{6}
CRS_DV
CRS_DV
AGND
TD-{5}
RD-{5}
RD-{6}
TD-{6}
TD-{7}
RD-{7}
RD-{8}
TD-{8}
AGND
PLLGND
SSMII_EN
SMII_
TXEN{5}
CRS_DV
CRS_DV
AVDD
TD+{5}
RD+{5}
RD+{6}
TD+{6}
TD+{7}
RD+{7}
RD+{8}
TD+{8}
AVDD
PLLVDDC REF_CLK
SMII_
Note: TGND balls thermal grounds
Figure Pinout (Top View)
Table Ballout Signal Name Signal Name
AGND AGND AGND AGND
Ball
Signal Name
CRS_DV{5} CRS_DV{6} CRS_DV{7} CRS_DV{8}
Ball
Signal Name
MASTERPHY/SFRAME MDIO MDIX_DIS
Ball
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Page Section Pinout Diagrams Document 5228-DS05-R
Final Data Sheet
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BCM5228
Table Ballout Signal Name (Cont.) Signal Name
AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND ANEN AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD BIASGND BIASVDD CRS_DV{1} CRS_DV{2} CRS_DV{3} CRS_DV{4} RD-{3} RD-{4} RD-{5} RD-{6} RD-{7}
Ball
Signal Name
DGND DGND DGND DGND DGND DGND DVDD DVDD DVDD DVDD DVDD DVDD F100 FDXEN LC_SER_EN LED2{1} LED2{2} LED2{3} LED2{4} LED2{5} LED2{6} LED2{7} LED2{8} LED3{1} LED3{2} LED3{3} LED3{4} LED3{5} LED3{6} LED3{7} LED3{8} RXER{4} RXER{5} RXER{6} RXER{7} RXER{8}
Ball
Signal Name
OGND OGND OGND OGND OGND OGND OGND OGND OGND OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD PHYAD0 PHYAD1 PHYAD2 PHYAD3 PHYAD4 PLLGND PLLVDDC RD-{1} RD-{2} TD-{7} TD-{8} TD+{1} TD+{2} TD+{3}
Ball
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Document 5228-DS05-R Section Pinout Diagrams Page
BCM5228
Final Data Sheet
10/24/01
Table Ballout Signal Name (Cont.) Signal Name
RD-{8} RD+{1} RD+{2} RD+{3} RD+{4} RD+{5} RD+{6} RD+{7} RD+{8} RDAC REF_CLK RESET# RXD0{1} RXD0{2} RXD0{3} RXD0{4} RXD0{5} RXD0{6} RXD0{7} RXD0{8} RXD1{1} RXD1{2} RXD1{3} RXD1{4} RXD1{5} RXD1{6} RXD1{7} RXD1{8} RXER{1} RXER{2} RXER{3} TGND TGND TGND TGND TGND
Ball
Signal Name
SD-{1} SD-{2} SD-{3} SD-{4} SD-{5} SD-{6} SD-{7} SD-{8} SD+{1} SD+{2} SD+{3} SD+{4} SD+{5} SD+{6} SD+{7} SD+{8} SERIAL_EN SLED_DO/INTR# SMII_RSYNC SMII_RXC SMII_TXC SMII_EN/SLED_CLK SSMII_EN SSYNC TD-{1} TD-{2} TD-{3} TD-{4} TD-{5} TD-{6} TXD0{7} TXD0{8} TXD1{1} TXD1{2} TXD1{3}
Ball
Signal Name
TD+{4} TD+{5} TD+{6} TD+{7} TD+{8} TESTEN TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TGND TXEN{6} TXEN{7} TXEN{8} TXER_EN TX_ER{1}/LED1{1}
Ball
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Page Section Pinout Diagrams Document 5228-DS05-R
Final Data Sheet
10/24/01
BCM5228
Table Ballout Signal Name (Cont.) Signal Name
TGND TGND TRST# TXD0{1} TXD0{2} TXD0{3} TXD0{4} TXD0{5} TXD0{6}
Ball
Signal Name
TXD1{4} TXD1{5} TXD1{6} TXD1{7} TXD1{8} TXEN{1} TXEN{2} TXEN{3} TXEN{4} TXEN{5}
Ball
Signal Name
TX_ER{2}/LED1{2} TX_ER{3}/LED1{3} TX_ER{4}/LED1{4} TX_ER{5}/LED1{5} TX_ER{6}/LED1{6} TX_ER{7}/LED1{7} TX_ER{8}/LED1{8} VREF
Ball
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BCM5228
Final Data Sheet
10/24/01
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Final Data Sheet
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BCM5228
RESETTING BCM5228
There ways reset each transceiver BCM5228. hardware reset been provided which resets internal nodes inside chip known state. reset pulse must asserted least microseconds. Hardware reset should always applied BCM5228 after power-up. Each transceiver BCM5228 also individual software reset capability. perform software reset, must written transceiver's Control Register (see Register Definitions). This self-clearing, meaning that second write operation necessary reset. There effect written Control Register reset bit.
ISOLATE MODE
Each transceiver BCM5228 isolated from RMII. When transceiver into isolate mode, RMII inputs (TXD1,TXD0, TXEN, TXER) ignored, RMII outputs (CRS_DV, RXER, RXD1,RXD0) high impedance. Only management pins (MDC, MDIO) operate normally. Upon resetting chip, isolate mode off. Writing Control Register puts transceiver into isolate mode. Writing same removes from isolate mode.
LOOPBACK MODE
loopback mode allows in-circuit testing BCM5228 chip. packets sent through pins looped-back internally pins, sent cable. Incoming packets cable ignored. loopback mode entered writing Control Register writing shadow register 1Dh. order resume normal operation bits must Several function bypass modes also supported which provide number different combinations feedback paths during loopback testing. These bypass modes include: bypass scrambler, bypass MLT3 encoder bypass 4B5B encoder.
FULL-DUPLEX MODE
BCM5228 supports full-duplex operation. While full-duplex mode, transceiver simultaneously transmit receive packets cable. default, each transceiver BCM5228 powers half-duplex mode. When auto negotiation disabled, full-duplex operation enabled either (FDXEN) register (Register When auto negotiation enabled mode, full-duplex capability advertised default overridden write auto negotiation Advertisement Register (04h).
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BCM5228
Final Data Sheet
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100BASE-FX MODE
BCM5228F transceivers interface with external 100BASE-FX fiber optic driver receiver instead magnetics module used with twisted-pair cable. differential transmit receive data pairs will operate PECL voltage levels instead those required twisted-pair transmission, termination scheme recommended application note used. data encoded using two-level NRZI instead three-level MLT3. data stream scrambled fiberoptic transmission. stream cipher function bypassed when 100BASE-FX mode selected. external fiber optic receiver detects signal status communicate BCM5228B BCM5228F through pins. this mode, internal signal detect function bypassed. 100BASE-FX mode automatically selected whenever valid differential signal detected input pins. Pulling both simultaneously disables 100BASE-FX mode.
10BASE-T MODE
same magnetics module used interface twisted-pair cable 10BASE-T mode 100BASE-TX mode. data two-level Manchester coded instead three-level MLT3 scrambling/descrambling 4B5B coding performed. Data clock rates decreased factor with RMII interface operating MHz.
ADDRESS
Each transceiver BCM5228 unique address management. address determined using base address, which input PHYAD[4:0] pins. following shows addressing eight PHYs. PHY0 PHYAD PHY1 PHYAD PHY7 PHYAD Every time write read operation executed, transceiver compares address with address definition. operation executed only when addresses match.
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Page Section Operational Description Document 5228-DS05-R
Final Data Sheet
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BCM5228
DESCRIPTION
BCM5228 offers rich display outputs through serial parallel modes. There serial modes available, Serial mode Low-Cost Serial mode. serial mode provides compatibility with other Broadcom PHYs. Serial modes selected hardware only during power-on reset. When serial mode enabled global hardware interrupt feature available. However, interrupt serial Low-Cost Serial mode desired simultaneously, then parallel programmed provide interrupt output port eight such interrupt ORed obtain global interrupt.
SERIAL MODE
Serial mode enabled only having SER_EN high LC_SER_EN during power-on reset. serial mode enabled then Low-Cost Serial mode hardware global interrupt disabled. serial mode BCM5228 sources serial data stream, associated clock, framing signal follows: Serial data stream, SLED_DO which active stream containing bits frame. Serial data clock, SLED_CLK which runs approximately used clock SLED_DO falling edge this clock. SLED-DO valid rising edge this clock. Framing pulse, SFRAME which logic high pulse occurring once every SLED_DO times. SFRAME goes high coincident with port BCM5228 provides different serial stream depending register 1Ah. When serial mode enabled hardware, further action taken, Normal (default) stream selected SLED_DO. Interrupt enable register then Interrupt stream selected SLED_DO. Table below details.
Table Serial Mode Framing Option
Normal Interrup
Serial
Serial
Global interrupt
Serial
Speed100 Speed100
Serial
Link Link
Serial
Transmit Port interrupt
Serial
Receive Activity
Note global interrupt indicates interrupt from eight PHYs they were ORed together.
port interrupt provided per-PHY basis.
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Document 5228-DS05-R Section Modes Page
BCM5228
Final Data Sheet
10/24/01
LOW-COST SERIAL MODE
Low-Cost Serial mode enabled pulling both LC_SER_EN SER_EN high during power-on reset. When enabled, serial data stream, SLED_DO, shifted falling edge SLED_CLK. SLED_DO valid rising edge this clock. data shifted such manner that update LEDs using simple shift register that drive display LEDs will cause noticeable flicker normal operation. There banks, bank through bank associated with outputs. Each bank register bits that select signal output from that bank. Selected signal from each bank shifted LED_DO following order: Bank port through port Bank port through port 8,., Bank port through total outputs. Low-Cost Serial mode programmable banks located shadow register port port Table Table Table Table Table Table programming details. default outputs SPEED, LINK, FULL-DUPLEX, ACTIVITY, SPEED, LINK bank through bank respectively.
Table Low-Cost Serial Mode Bank Selection Shadow Register 1Ah, Bits [2:0] Value
SERIAL BANK SELECT BITS[2:0]
Selection
Speed Activity Full-duplex Transmit Receive Interrupt Collision Link
Note: Shadow Register accessed setting Register
Table Low-Cost Serial Mode Bank Selection Shadow Register 1Ah, Bits [5:3] Value
SERIAL BANK SELECT BITS[2:0]
Selection
Link Speed Activity Full-duplex Transmit Receive Interrupt Collision
Note: Shadow Register accessed setting Register
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BCM5228
Table Low-Cost Serial Mode Bank Selection Shadow Register 1Ah, Bits [8:6] Value
Serial Bank Select Bits[2:0]
Selection
Full-duplex Transmit Receive Interrupt Collision Link Speed Activity
Note: Shadow Register accessed setting Register
Table Low-Cost Serial Mode Bank Selection Shadow Register 1Ah, Bits [2:0] Value
Serial Bank Select Bits[2:0]
Selection
Activity Full-duplex Transmit Receive Interrupt Collision Link Speed
Note: Shadow Register accessed setting Register
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Table Low-Cost Serial Mode Bank Selection Shadow Register 1Ah, Bits [5:3] Value
SERIAL BANK SELECT BITS[2:0]
Selection
Speed Activity Full-duplex Transmit Receive Interrupt Collision Link
Note: Shadow Register accessed setting Register
Table Low-Cost Serial Mode Bank Selection Shadow Register 1Ah, Bits [8:6] Value
SERIAL BANK SELECT BITS[2:0]
Selection
Link Speed Activity Full-duplex Transmit Receive Interrupt Collision
Note: Shadow Register accessed setting Register
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BCM5228
PARALLEL MODE
BCM5228U offers parallel mode that active time. There pins, LED1, LED2, LED3 each port each which individually configured output many signals. Configuration accomplished either hardware programming register bits. LED1 pins shared with TXER. These pins configured output LED1 TXER_EN pulled during power-on reset. unmanaged system design using BCM5228U, parallel pins each port programmed through hardware during power-on reset pull-down pull-up combinations TXER/LED1 [1:8] pins. Pull-up pull-down these pins should done using series 4.7-K resistor OVDD OGND respectively drive polarity should such that active output LED1 lights LED. LED2 LED3 configured output Link, Speed, Activity, Full-duplex, Transmit, Receive, Interrupt Collision while LED3 configured Activity, Full-duplex, Link Speed. Software configuration LED1, LED2 LED3 accomplished through shadow register 1Ah, bits [7:0]. Table Table Table details. Because LED2{1:8} pins open drain, they wire 0Red together configured hardware during power-on reset through software setting bits shadow register) provide global hardware interrupt when required.
Table Parallel Mode LED1 Selection TXER[3:1] Shadow Register 1Ah, Bits [2:0] Value
POWER-ON LED1 SELECT BITS[2:0] LED1 Select[2:0] Note: Shadow Register accessed setting Register
LED1 Selection
Link Speed Activity Full-duplex Transmit Receive Interrupt Collision
Table Parallel Mode LED2 Selection TXER [6:4] Shadow Register 1Ah, Bits [5:3] Value
POWER-ON RESET LED2 SELECT[2:0] LED2 Select[2:0] Note: Shadow Register accessed setting Register
LED2 Selection
Speed Activity Full-duplex Transmit Receive Interrupt Collision Link
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Final Data Sheet
10/24/01
Table Parallel Mode LED3 Selection TXER [8:7] Shadow Register 1Ah, Bits [7:6] Value
POWER-ON RESET LED3 SELECT[1:0] LED3 SELECT[1:0] Note: shadow register accessed setting Register
LED3 Selection
Activity Full-duplex Link Speed
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BCM5228
Regis Summa
MANAGEMENT INTERFACE: REGISTER PROGRAMMING
BCM5228 fully complies with IEEE 802.3u Media Independent Interface (MII) specification. management interface registers each port serially written-to read from using common MDIO pins. single clock waveform must provided BCM5228 rate 0-25 through pin. serial data communicated MDIO pin. Every MDIO must have same period clock. MDIO bits latched rising edge clock. Every read write instruction frame contains following fields:
Table Management Frame Format Operation
Read
PHYAD
AAAAA
REGAD
RRRRR
Data
Idle
Direction
Driven BCM5228 Driven BCM5228 Driven BCM5228
Write
AAAAA
RRRRR
Preamble (PRE). Thirty-two consecutive bits must sent through MDIO BCM5228 signal beginning RMII instruction. Fewer than bits causes remainder instruction ignored. Start Frame (ST). pattern indicates that start instruction follows. Operation Code (OP). Read instruction indicated while Write instruction indicated Address (PHYAD). 5-bit address follows next, with transmitted first. address allows single MDIO access multiple chips. BCM5228 supports complete address space with PHYAD[4:0] input-pins used base address selecting eight transceivers. Register Address (REGAD). 5-bit Register Address follows, with transmitted first. register BCM5228, containing register addresses definitions, provided following pages. Turnaround (TA). next times used avoid contention MDIO when Read operation performed. Write operation, must sent BCM5228 chip during these times. Read operation, MDIO must placed into High-Impedance during these times. chip drives MDIO during second time. Data. last bits frame actual data bits. Write operation, these bits sent BCM5228, whereas, Read operation, these bits driven BCM5228. either case, transmitted first. When writing BCM5228, data field bits must stable nanoseconds before rising edge MDC, must held valid nanoseconds after rising edge MDC. When reading from BCM5228, data field bits valid after rising-edge until next rising edge MDC. Idle. high impedance state MDIO line. tri-state drivers disabled PHY's pull-up resistor pulls MDIO line logic Note that least more idle states required between frames. Following examples write read instructions.
transceiver with address 00001 into Loopback mode, following write instruction must issued 1111 1111 1111 1111 1111 1111 1111 1111 0101 00001 00000 0100 0000 0000 0000
determine link pass state, following read instruction must issued 1111 1111 1111 1111 1111 1111 1111 1111 0110 00001 00001 ZZZZ ZZZZ ZZZZ ZZZZ
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read operation, BCM5228 drives MDIO line during Data fields (the last times). final 65th clock pulse must sent close transaction cause write operation take place.
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REGISTER SUMMARY
Table contains register summary each port BCM5228. register addresses specified form, name register bits have been abbreviated. When writing reserved bits, always write value, when reading from these bits, ignore output value. Never write value undefined register address. reset value registers shown Init column.
Table Register Summary
Loopback Force100 Isolate Reserved Power Down Full Duplex Auto Enable Restart Auto Collision Test pream supp-ress Model Auto comp Remote Fault Capable Reserved Pause Reserved Tech 10BT Capable
Addr
Name
Init
3000h
Control
Soft Reset
Reserved Acknow -ledge Fault Reserved Tech Pause Remote Fault
Status
Capable
Capable
Capable
Auto Capable
Link Status Revision Advertised Selector Field[4:0] Link Partner Selector Field [4:0]
Jabber Detect
Extd Capable
7809h 0040h 61D0h 01E1h
PhyID High
PhyID
Auto Advertise
Next Page
Link Partner Ability
Next Page
0000h
Reserved Acknowledge2 Acknowledge2 Toggle Toggle Reserved Message Page Message Page
Auto Expansion
Reserved
Fault Message/Unformatted Code Field Message/Unformatted Code Field
Next Able
Next Able
Page Recvd
Auto Able
0004h
Next Page
Next Page
2001h 0000h
Next Page
Trans Disable Reserved Bypass 4B5B Enc/ Bypass Scram/ Descram
Next Page
100BASE-X Control
Reserved
Bypass NRZI Enc/
Bypass Align
Base-line Wander Disable
Enable
Reserved
Extended RMII FIFOs
RMII Band
Reserved
0000h
100BASE-X Status
Reserved
R/SMII Over Under
Mode
Locked
Current Link Status
Current Remote Fault
Reserved
False Carrier Detected
Detected
Error Detected
Error Detected
Lock Error Detected
MLT3 Error Detected
0000h
100BASE-X Error Counter
Receive Error Counter[15:0]
0000h
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BCM5228 Final Data Sheet
10/24/01
Table Register Summary (Cont.)
False Carrier Sense Counter[7:0]
Addr
Name
Init
0000h
100BASE-X False Carrier Counter
RMII/ SMII Slowrxd Reserved
RMII/SMII Over-run/Under-run Counter[7:0]
100BASE-X Disconnect Counter
RMII/ SMII Fastrxd
0200h 0300h 0000h 0000h
Reserved
Reserved
Reserved
Reserved
PTest
Reserved
Reserved
Auxiliary Control/ Status
Force Link TXDAC Power Mode
Jabber Disable
Edge Rate[1:0]
Auto Enable Indicator
Force Indicator
SP100 Indicator
Indicator
003xh
Auxiliary Status Summary
AutoNeg Detect Auto Pause Auto Remote Fault INTR Enable Reserved Mask Mask Link Mask INTR Mask Reserved
Auto Complete Auto Ability Detect Auto Pardet Fault
Auto Complete
Page Rcvd
Auto Able
SP100 Indicator
Link Status
Internal Auto Enabled
FullDuplex Indication
0000h
Interrupt
Reserved
Global Interrupt Status
Change
Change
Link Change
INTR Status
8F0xh
Auxiliary Mode2
Reserved
Reserved
10BT Dribble Correct
Token Ring Mode
HSTR FIFO Enable
Block 10BT Echo Mode
Traffic Meter Mode
Activity Force
Serial Enable
Disable
Activity/ Link Enable
Qual Parallel Detect Mode
Reserved
008Ah
10BASE-T Aux. Error General Status
MDIX Status (BT) MDIX Manual Swap Manchstr Code (BT) AutoMDIX Disable Reserved
Reserved
Reserved
Reserved
Auto Enable Indicator
Force Indicator
SP100 Indicator
Indicator
002xh
Auxiliary Mode
Reserved
Activity Force Inactive
Link Force Inactive
Reserved
Block TXEN Mode
Reserved
x000h
Auxiliary Multi-PHY
10BT
10BT
Reserved
Restart Auto
Auto Complete Shadow Register Enable
Reserved
Detect
Ability Detect
Super Isolate
Reserved
RXER Code Mode
0000h
Broadcom Test
Reserved
Reserved
000Bh
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Section Register Summary
Final Data Sheet
BCM5228
10/24/01
Table Shadow Register Summary (MII Register 1Fh, bit7 Init
003Ah
Addr Name
Reserved
Reserved
Parallel LED2 Select[2:0]
Auxiliary Mode (PHY
Parallel LED3 Select[1:0]
Reserved
Select enable Serial Bank Select[2:0] Serial Bank Select[2:0]
Parallel LED1 Select[2:0]
3000h
Auxiliary Mode (PHY
Serial Bank Select[2:0]
Reserved
Serial Bank Select[2:0]
3000h
Auxiliary Mode (PHY
Cable Length 100x[2:0] Peak Amplitude[5:0] Reserved
Reserved
Serial Bank Select[2:0]
Serial Bank Select[2:0]
3000h
Auxiliary Status
MLT3 Detect
0000h
Auxiliary Status
Detect
Noise[7:0] (Root Mean Square error)
Detect
Link Break Timer Expire
Link Fail Timer Expire
FIFO Consumption[3:0]
0000h
Auxiliary Mode
Reserved
FIFO Size Select[3:0]
0C04h
Auxiliary Status4
Packet Length Counter[15:0]
0000h
Broadco
Section Register Summary Page
Document 5228-DS05-R
BCM5228
Final Data Sheet
10/24/01
CONTROL REGISTER
Table Control Register (Address 00d, 00h)
Name
Soft Reset Loopback Forced Speed Selection Auto Negotiation Enable Power Down Isolate Restart Auto Negotiation Duplex Mode Reserved Reserved
(SC) (SC)
Description
reset Normal operation loopback mode Normal operation megabits/second megabits/second Auto negotiation enable Auto negotiation disable Normal operation Electrically isolate from RMII Normal operation Restart auto negotiation process Normal operation Full-duplex Half-duplex Ignore when read Ignore when read
Default
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Soft Reset. reset BCM5228 software control, must written Control Register using write operation. clears itself after reset process complete, need cleared using second write. Writes other Control Register bits will have effect until reset process completed, which requires approximately microsecond. Writing this effect. Since this self-clearing, after cycles from write operation, returns when read. Loopback. BCM5228 placed into loopback mode writing Control Register. loopback mode cleared writing control register, resetting chip. When this read, returns when chip software-controlled loopback mode, otherwise returns Forced Speed Selection. auto negotiation enabled, this effect speed selection. However, auto negotiation disabled software control, operating speed BCM5228 forced writing appropriate value Control Register. Writing this forces 100BASE-X operation, while writing forces 10BASET operation. When this read, returns value software-controlled forced speed selection only. order read overall state forced speed selection, including both hardware software control, Auxiliary Error General Status Register, 1Ch. Auto Negotiation Enable. Auto negotiation disabled methods: hardware software control. ANEN input driven logic auto negotiation disabled hardware control. Control Register written with value auto negotiation disabled software control. When auto negotiation disabled this manner, writing same Control Register resetting chip re-enables auto negotiation. Writing this effect when auto negotiation been disabled hardware control. When read, this returns value most recently written this location, been written since last chip reset.
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Power Down. BCM5228 does implement power mode. Isolate. Each individual isolated from Media Independent Interface writing Control Register. RMII outputs tri-stated RMII inputs ignored. Because management interface still active, isolate mode cleared writing control register, resetting chip. When this read, returns when chip isolate mode, otherwise, returns Restart Auto Negotiation. Control Register self-clearing that allows auto negotiation process restarted, regardless current status auto negotiation state machine. order this have effect, auto negotiation must enabled. Writing this restarts auto negotiation, while writing this effect. Since self-clearing after only cycles, always returns when read. operation this identical Auxiliary Multiple Register. Duplex Mode. default, BCM5228 powers half-duplex mode. chip forced into full-duplex mode writing Control Register while auto negotiation disabled. Half-duplex mode resumed writing Control Register, resetting chip. Reserved Bits. reserved Register bits must written times. Ignore BCM5228 output when these bits read.
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STATUS REGISTER
Table Status Register (Address 01d, 01h)
10:7
Name
100BASE-T4 Capability 100BASE-TX Capability 100BASE-TX Capability 10BASE-T Capability 10BASE-T Capability Reserved Preamble Suppression Auto Negotiation Complete Remote Fault Auto Negotiation Capability Link Status Jabber Detect Extended Capability
Description
100BASE-T4 capable 100BASE-TX full-duplex capable 100BASE-TX half-duplex capable 10BASE-T full-duplex capable 10BASE-T half-duplex capable Ignore when read Preamble suppressed Preamble always required Auto negotiation process completed Auto negotiation process completed Far-End Fault condition detected Far-End Fault condition detected Auto negotiation capable auto negotiation capable Link (Link Pass state) Link down (Link Fail state) Jabber condition detected Jabber condition detected Extended register capable
Default
0000
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
100BASE-T4 Capability. BCM5228 capable 100BASE-T4 operation, returns when status register read. 100BASE-X Full-Duplex Capability. BCM5228 capable 100BASE-X full-duplex operation, returns when Status Register read. 100BASE-X Half-Duplex Capability. BCM5228 capable 100BASE-X half-duplex operation, returns when Status Register read. 10BASE-T Full-Duplex Capability. BCM5228 capable 10BASE-T full-duplex operation, returns when Status Register read. 10BASE-T Half-Duplex Capability. BCM5228 capable 10BASE-T half-duplex operation, returns when Status Register read. Reserved Bits. Ignore BCM5228 output when these bits read. Preamble Suppression. This only writable Status Register. Setting this allows subsequent management frames accepted with without standard preamble pattern. When preamble suppression enabled, only preamble bits required between successive management commands, instead normal
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Auto Negotiation Complete. Status Register returns auto negotiation process been completed contents registers valid. Remote Fault. returns Status Register when link partner signalled far-end fault condition. When far-end fault occurs, latched remains until register read remote fault condition been cleared; this only applies mode operation. Auto Negotiation Capability. BCM5228 capable performing IEEE auto negotiation, returns when Status Register read, regardless whether auto negotiation function been disabled. Link Status. BCM5228 returns Status Register when link state machine Link Pass, indicating that valid link been established. Otherwise, returns When link failure occurs after Link Pass state been entered, Link Status latched remains until read. After read, becomes Link Pass state been entered again. Jabber Detect. 10BASE-T operation only. BCM5228 returns Status Register jabber condition been detected. After read, chip reset, reverts Extended Capability. BCM5228 supports extended capability registers, returns when Status Register read. Several extended registers have been implemented BCM5228, their functions defined later this section.
IDENTIFIER REGISTERS
Table Identifier Registers (Addresses 03d, 03h)
15:0 15:0
Name
Address 00010 Address 00011
Description
PHYID high PHYID
Value
0040h XXXXh
Broadcom Corporation been issued Organizationally Unique Identifier (OUI) IEEE. 24-bit number, 00-10-18, expressed values. That number, along with Broadcom Model Number BCM5228 part, 1Ch, Broadcom Revision number, 00h, placed into Registers. translation from OUI, Model Number Revision Number Identifier Register occurs follows: PHYID High[15:0] OUI[21:6] PHYID Low[15:0] OUI[5:0] Model[5:0] Rev[3:0]
Note most significant bits represented (OUI[23:22]).
Figure page shows result concatenating these values form Identifier Registers PHYID HIGH PHYID LOW.
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Final Data Sheet
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AUTO NEGOTIATION ADVERTISEMENT REGISTER
Table Auto Negotiation Advertisement Register (Address 04d, 04h)
12:11
Name
Next Page Reserved Remote Fault Reserved Technologies Pause Advertise 100BASE-T4 Advertise 100BASE-X Advertise 100BASE-X Advertise 10BASE-T Advertise 10BASE-T Advertise Selector Field
Description
Next Page ability enabled Next Page ability disabled Ignore when read Transmit Remote Fault Ignore when read Pause operation full-duplex Advertise capability advertise capability Advertise 100BASE-X full-duplex advertise 100BASE-X full-duplex Advertise 100BASE-X Advertise 10BASE-T full-duplex advertise 10BASE-T full-duplex Advertise 10BASE-T Indicates 802.3
Default
00001
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Next Page. BCM5228 supports Next Page function. Reserved Bits. Ignore output when read. Remote Fault. Writing Advertisement Register causes Remote Fault indicator sent Link Partner during auto negotiation. Writing this resetting chip clears Remote Fault transmission bit. This returns value last written else write been completed since last chip reset. Reserved Technologies Bits. Ignore output when read. Pause. Pause operation full-duplex links. this independent negotiated data rate, medium, link technology. setting this indicates availability additional capability when full-duplex operation use. This used communicate pause capability Link Partner effect operation. Advertisement Bits. Bits Advertisement Register allow user customize ability information transmitted Link Partner. default value each reflects abilities BCM5228. writing bits, corresponding ability transmitted Link Partner. Writing causes corresponding ability suppressed from transmission. Resetting chip restores default values. Reading register returns values last written corresponding bits, else default values write been completed since last chip reset. Selector Field. Bits Advertisement Register contain value 00001, indicating that chip belongs 802.3 class transceivers.
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AUTO NEGOTIATION LINK PARTNER (LP) ABILITY REGISTER
Table Auto Negotiation Link Partner Ability Register (Address 05d, 05h)
12:11
Name
Next Page Acknowledge Remote Fault Reserved Technologies Advertise Pause Advertise 100BASE-T4 Advertise 100BASE-X Advertise 100BASE-X Advertise 10BASE-T Advertise 10BASE-T Link Partner Selector Field
Description
Link Partner next page Link Partner acknowledge Link Partner remote fault indicator Ignore when read Link Partner Pause capability Link Partner 100BASE-T4 capability Link Partner 100BASE-X capability Link Partner 100BASE-X capability Link Partner 10BASE-T capability Link Partner 10BASE-T capability Link Partner selector field
Default
00000
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Note that values contained auto negotiation Link Partner Ability Register only guaranteed valid once auto negotiation successfully completed, indicated Status Register.
Next Page. Link Partner Ability Register returns value when Link Partner implements Next Page function Next Page information that wants transmit. BCM5228 does implement Next Page function, thus ignores Next Page bit, except copy this register. Acknowledge. Link Partner Ability Register used auto negotiation indicate that device successfully received Link Partner's link code word. Remote Fault. Link Partner Ability Register returns value when Link Partner signals that remote fault occurred. BCM5228 simply copies value this register does upon Reserved Bits. Ignore when read. Advertise Pause. Indicates that Link Partner Pause set. Advertise Bits. Bits Link Partner Ability Register reflect abilities Link Partner. these bits indicates that Link Partner capable performing corresponding mode operation. Bits cleared time auto negotiation restarted BCM5228 reset. Selector Field. Bits Link Partner Ability Register reflect value Link Partner's selector field. These bits cleared time auto negotiation restarted chip reset.
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AUTO NEGOTIATION EXPANSION REGISTER
Table Auto Negotiation Expansion Register (Address 06d, 06h)
15:5
Name
Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Link Partner Auto Negotiation Able
Description
Ignore when read Parallel Detection Fault. Parallel Detection Fault Link Partner Next Page capability Link Partner does have Next Page Next Page able page been received page been received Link Partner auto negotiation capability Link Partner does have auto negotiation
Default
000h
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Reserved Bits. Ignore when read. Parallel Detection Fault. auto negotiation Expansion Register read-only that gets latched high when parallel detection fault occurs auto negotiation state machine. further details, consult IEEE standard. reset after register read, when chip reset. Link Partner Next Page Able. auto negotiation Expansion Register returns when Link Partner Next Page capabilities. same value Link Partner Ability Register. Next Page Able. BCM5228 Returns when auto negotiation Expansion Register read indicating that Next Page capabilities. Page Received. auto negotiation Expansion Register latched high when link code word received from Link Partner, checked, acknowledged. remains high until register read, until chip reset. Link Partner Auto Negotiation Able. auto negotiation Expansion Register returns when Link Partner known have auto negotiation capability. Before auto negotiation information exchanged, Link Partner does comply with IEEE auto negotiation, returns value
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AUTO NEGOTIATION NEXT PAGE REGISTER
Table Next Page Transmit Register (Address 07d, 07h)
Name
Next Page Reserved Message Page Acknowledge
Description
Additional Next Page(s) follows Last page Ignore when read Message page Unformatted page Will comply with message Cannot comply with message Previous value transmitted link code word equalled logic zero Previous value transmitted Link Code Word equalled logic
Default
Toggle
10:0
Message/Unformatted Code Field
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Next Page. Indicates whether this last Next Page transmitted. Message Page. Differentiates Message Page from unformatted page. Acknowledge Indicates that device ability comply with message. Toggle. Used arbitration function ensure synchronization with Link Partner during Next Page exchange. Message Code Field. eleven-bit wide field, encoding 2048 possible messages. Unformatted Code Field. eleven-bit wide field, which contain arbitrary value.
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AUTO NEGOTIATION LINK PARTNER (LP) NEXT PAGE TRANSMIT REGISTER
Table Next Page Transmit Register (Address 08d, 08h)
Name
Next Page Reserved Message Page Acknowledge
Description
Additional Next Page(s) follows Last page Ignore when read Message page Unformatted page Will comply with message Cannot comply with message Previous value transmitted Link Code Word equalled logic zero Previous value transmitted Link Code Word equalled logic
Default
Toggle
10:0
Message/Unformatted Code Field
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Next Page. Indicates whether this last Next Page. Message Page. Differentiates Message Page from unformatted page. Acknowledge Indicates that Link Partner ability comply with message. Toggle. Used Arbitration function ensure synchronization with Link Partner during Next Page exchange. Message Code Field. eleven-bit wide field, encoding 2048 possible messages. Unformatted Code Field. eleven-bit wide field, which contain arbitrary value.
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100BASE-X AUXILIARY CONTROL REGISTER
Table 100-BASE-X Auxiliary Control Register (Address 16d, 10h)
15:14
Name
Reserved Transmit Disable Reserved Reserved Bypass 4B5B Encoder/Decoder
Description
Write ignore read
Default
Transmitter disabled Normal operation Write ignore when read Write ignore when read
Transmit receive codes over RMII pins Normal RMII Scrambler descrambler disabled Scrambler descrambler enabled NRZI encoder decoder disabled NRZI encoder decoder enabled receive symbols aligned Receive symbols aligned boundaries Baseline wander correction disabled Baseline wander correction enabled Far-End Fault enabled. Far-End Fault disabled. Write ignore when read Extended FIFO mode, Normal FIFO mode Enabled Disabled Write ignore when read
Bypass Scrambler/Descrambler Bypass NRZI Encoder/Decoder Bypass Receive Symbol Alignment Baseline Wander Correction Disable Enable Reserved Extended FIFO Enable RMII Out-of-Band Enable Reserved
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Transmit Disable. transmitter disabled writing Register 10h. transmitter output (TD±) forced into high impedance state. Bypass 4B5B Encoder/Decoder. 4B5B encoder decoder bypassed writing Register 10h. transmitter sends codes from TXER TXD1,TXD0 pins directly scrambler. TXEN must active, frame encapsulation (insertion codes) performed. receiver places descrambled aligned codes onto RXER, RXD1 RXD0 pins. asserted when valid frame received. Bypass Scrambler/Descrambler. Stream Cipher function disabled writing Register 10h. Stream Cipher function re-enabled writing this bit. Bypass NRZI Encoder/Decoder. NRZI encoder decoder bypassed writing Register 10h, causing 3-level NRZI data transmitted received cable. Normal operation (3-level NRZI encoding decoding) re-enabled writing this bit.
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Bypass Receive Symbol Alignment. Receive Symbol Alignment bypassed writing Register 10h. When used conjunction with bypass 4B5B encoder/decoder bit, unaligned codes placed directly RXER RXD1, RXD0 pins. Baseline Wander Correction Disable. Baseline Wander Correction circuit disabled writing Register 10h. BCM5228 corrects baseline wander receive data signal when this cleared. Enable. Controls Far-End Fault mechanism associated with 100BASE-FX operation. enables function, disables Extended RMII/SMII FIFO Enable. Controls Extended RMII/SMII FIFO mechanism. RMII Out-of-Band Enable. Controls RMII Out-of-Band mechanism within RMII receive logic. Reserved Bits. Reserved bits 100BASE-X Auxiliary Control Register must written times. Ignore BCM5228 outputs when these bits read.
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100BASE-X AUXILIARY STATUS REGISTER
Table 100BASE-X Auxiliary Status Register (Address 17d, 11h)
15:12
Name
Reserved R/SMII Overrun/Underrun Detected Mode Locked Current 100BASE-X Link Status Remote Fault Reserved False Carrier Detected Detected Receive Error Detected Transmit Error Detected Lock Error Detected MLT3 Code Error Detected
Description
Ignore when read Error detected error 100BASE-FX mode 100BASE-TX 10BASE-T mode Descrambler locked Descrambler unlocked Link pass Link fail Remote Fault detected Remote Fault detected Ignore when read False Carrier detected since last read False Carrier since last read error detected since last read error since last read Receive error detected since last read receive error since last read Transmit Error code received since last read Transmit Error code received since last read Lock Error detected since last read Lock Error since last read MLT3 Code Error detected since last read MLT3 Code Error since last read
Default
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
R/SMII Overrun/Underrun Error. returns when RMII receive FIFO encounters overrun underrun condition. Mode. Returns value derived from input pins. Returns when driven with valid differential signal level. Returns when both simultaneously driven low. Locked. returns when descrambler locked incoming data stream. Otherwise, returns Current 100BASE-X Link Status. returns when 100BASE-X Link Status good. Otherwise, returns Remote Fault. returns while link partner signalling far-end fault condition. Otherwise, returns False Carrier Detected. returns extended status register false carrier been detected since last time this register read. Otherwise, returns
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Document 5228-DS05-R Section Register Summary Page
BCM5228
Final Data Sheet
10/24/01
Detected. returns end-of-stream delimiter error been detected since last time this register read. Otherwise, returns Receive Error Detected. returns packet received with invalid code since last time this register read. Otherwise, returns Transmit Error Detected. returns packet received with Transmit Error code since last time this register read. Otherwise, returns Lock Error Detected. returns descrambler lost lock since last time this register read. Otherwise, returns MLT3 Code Error Detected. returns MLT3 coding error been detected receive data stream since last time this register read. Otherwise returns
100BASE-X RECEIVE ERROR COUNTER
Table 100BASE-X Receive Error Counter (Address 18d, 12h)
15:0
Name
Receive Error Counter [15:0]
Description
Number Non-Collision packets with Receive Errors since last read
Default
0000h
Receive Error Counter [15:0]. This counter increments each time BCM5228 receives non-collision packet containing least receive error. counter automatically clears itself when read. When counter reaches maximum value, FFh, stops counting receive errors until cleared
100BASE-X FALSE CARRIER SENSE COUNTER
Table 100BASE-X False Carrier Sense Counter (Address 19d, 13h)
15:8
Name
RMII/SMII Overrun/Underrun Counter [7:0] False Carrier Sense Counter [7:0]
Description
Number RMII Overruns/Underruns since last read Number False Carrier Sense events since last read
Default
RMII/SMII Overrun/Underrun Counter [7:0]. RMII/SMII Overrun/Underrun Counter increments each time BCM5228 detects overrun underrun RMII/SMII FIFOs. counter automatically clears itself when read. When counter reaches maximum value, FFh, stops counting overrun/underrun errors until cleared. False Carrier Sense Counter [7:0]. This counter increments each time BCM5228 detects false carrier receive input. This counter automatically clears itself when read. When counter reaches maximum value, FFh, stops counting false carrier sense errors until cleared.
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Page Section Register Summary Document 5228-DS05-R
Final Data Sheet
10/24/01
BCM5228
100BASE-X DISCONNECT COUNTER
Table 100BASE-X Disconnect Counter
13:8
Name
RMII/SMII Fast RMII/SMII Slow Reserved Reserved
Description
extended FIFO mode, detect fast receive data Normal Normal extended FIFO mode, detect slow receive data Write 000010, ignore when read Write 00h, ignore when read
Default
000010
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
RMII/SMII Fast RXD. Extended FIFO operation only. Disconnect Counter Register indicates FIFO state machine detected fast receive data relative REF_CLK input. RMII/SMII Slow RXD. Extended FIFO operation only. Disconnect Counter Register indicates FIFO state machine detected slow receive data relative REF_CLK input.
AUXILIARY CONTROL/STATUS REGISTER
Table Auxiliary Control/Status Register (Address 24d, 18h)
13:8
Name
Jabber Disable Link Disable Reserved
Description
Jabber function disabled Jabber function enabled Link Integrity test disabled Link Integrity test enabled Ignore when read These bits define squelch mode 10BASE-T carrier sense mechanism: normal squelch squelch high squelch allowed nanosecond nanoseconds nanoseconds nanoseconds
Default
000000
Edge Rate [1:0]
Auto Negotiation Indicator
Auto negotiation activated Speed forced manually
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
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Document 5228-DS05-R Section Register Summary Page
BCM5228
Final Data Sheet
10/24/01
Table Auxiliary Control/Status Register (Address 24d, 18h) (Cont.)
Name
Force 100/10 Indication Speed Indication Full-duplex Indication
Description
Speed forced 100BASE-X Speed forced 10BASE-T 100BASE-X 10BASE-T Full-Duplex active Full-Duplex active
Default
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Jabber Disable. 10BASE-T operation only. Auxiliary Control Register allows user disable Jabber Detect function, defined IEEE standard. This function shuts transmitter when transmission request exceeded maximum time limit. writing Auxiliary Control Register, Jabber Detect function disabled. Writing this resetting chip restores normal operation. Reading this returns value Jabber Detect disable. Link Disable. Writing Auxiliary Control Register allows user disable Link Integrity state machines, place BCM5228 into forced Link Pass status. Writing this resetting chip restores Link Integrity functions. Reading this returns value Link Integrity Disable. LSQ. Extend decrease squelch levels detection incoming 10BASE-T data packets. default squelch levels implemented those defined IEEE standard. high- low-squelch levels useful situations where IEEE-prescribed levels inadequate. squelch levels used CRS/LINK block filter noise recognize only valid packet preambles link integrity pulses. Extending squelch levels allows BCM5228 operate properly over longer cable lengths. Decreasing squelch levels useful situations where there high level noise present cables. Reading these bits returns value squelch levels. Edge Rate [1:0]. Control bits used program transmit output Edge Rate 100BASE-TX mode. These bits logically ANDed with [1:0] input pins produce internal edge-rate controls (Edge_Rate [1], Edge_Rate [0]). Auto Negotiation Indicator. read-only that indicates whether auto negotiation been enabled disabled BCM5228. combination Control Register logic ANEN input required enable auto negotiation. When auto negotiation disabled, Auxiliary Control Register returns other times, returns Force100/10 Indication. read-only that returns value when following cases true:
ANEN F100 low, Control Register been written Control Register been written
When Auxiliary Control Register speed chip 10BASE-T. other cases, either speed forced (auto negotiation enabled), speed forced 100BASE-X.
Speed Indication. Auxiliary Control Register read-only that shows true current operation speed BCM5228. indicates 100BASE-X operation, while indicates 10BASE-T. Note that while auto negotiation exchange performed, BCM5228 always operating 10BASE-T speed. Full-Duplex Indication. Auxiliary Control Register read-only that returns when BCM5228 fullduplex mode. other modes, returns
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Final Data Sheet
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BCM5228
AUXILIARY STATUS SUMMARY REGISTER
Auxiliary Status Summary Register contains copies redundant status bits found elsewhere within register space.
Table Auxiliary Status Summary Register (Address 25d, 19h)
Name
Auto Negotiation Complete Auto Negotiation Complete Acknowledge Auto Negotiation Acknowledge Detected Auto Negotiation Ability Detect Auto Negotiation Pause
Description
Auto negotiation process completed Auto negotiation completed acknowledge state Auto negotiation acknowledge detected Auto negotiation Link Partner ability BCM5228 Link Partner Pause operation highest common denominator 10BASE-T 10BASE-T full-duplex 100BASE-TX 100BASE-T4 100BASE-TX full-duplex undefined Parallel detection fault Link Partner signalled far-end fault condition mode Page been received Link Partner auto negotiation capable megabits/second megabits/second Link (link pass state) Auto negotiation enabled Full-Duplex active Full-Duplex active
Default
10:8
Auto Negotiation
Auto Negotiation Parallel Detection Fault Link Partner Remote Fault Link Partner Page Received Link Partner Auto Negotiation Able Speed Indicator Link Status Auto Negotiation Enabled Full-Duplex Indication
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Descriptions each these individual bits found associated with their primary register descriptions.
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BCM5228
Final Data Sheet
10/24/01
INTERRUPT REGISTER
Table Interrupt Register (Address 26d, 1Ah)
13:12
Name
Reserved INTR Enable Reserved Mask Mask LINK Mask INTR Mask Reserved Global Interrupt Indicator Change Change LINK Change INTR Status
Description
Ignore read Interrupt enable Ignore when read Full-duplex interrupt mask SPEED Interrupt mask LINK interrupt mask Master interrupt mask Ignore when read Indicates interrupt present within BCM5228 Duplex change interrupt Speed change interrupt Link change interrupt Interrupt status
Default
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Interrupt Enable. Setting this enables Interrupt mode. state this also affects which status signals shifted serial data Serial mode. Figure page details. Mask. When this set, changes duplex mode will generate interrupt. Mask. When this set, changes operating speed will generate interrupt. Link Mask. When this set, changes Link status will generate interrupt. Interrupt Mask. Master Interrupt Mask. When this set, interrupts will generated, regardless state other mask bits. Global Interrupt Indicator. indicates Interrupt present within BCM5228. Change. indicates change Duplex status since last register read. Register read clears bit. Change. indicates change Speed status since last register read. Register read clears bit. Link Change. indicates change Link status since last register read. Register read clears bit. Interrupt Status. Represents status INTR# pin. indicates that interrupt mask that more change bits set. Register read clears bit.
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Page Section Register Summary Document 5228-DS05-R
Final Data Sheet
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BCM5228
AUXILIARY MODE REGISTER
Table Auxiliary Mode Register (Address 27d, 1Bh)
15:12
Name
Reserved 10BT Dribble Correct Token Ring Mode HSTR FIFO Enable Reserved Block 10BT Echo Mode Traffic Meter Mode Activity Force Reserved Reserved Activity/Link Mode Qual Parallel Detect Mode Reserved
Description
Ignore when read Enable, Disable Enable, Disable Enable, Disable Ignore when read Enable, Disable Enable, Disable Normal operation Ignore when read Write ignore when read Enable, Disable Enable, Disable Ignore when read
Default
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
10BT Dribble Correct. When enabled, will round-down nearest nibble when dribble bits present 10BASE-T input stream. Token Ring Mode. When enabled, 100BASE-X unlock timer changes allow long packets. HSTR FIFO Mode. When enabled, RMII/SMII receive FIFO will double from nibbles nibbles. Block 10BT Echo Mode. When enabled, during 10BASE-T half-duplex transmit operation, TXEN signal does echo onto RXDV pin. TXEN echoes onto pin, deassertion directly follows TXEN deassertion. Traffic Meter Mode. When enabled, Activity LEDs (ACTLED# FDXLED# Full-Duplex Interrupt modes enabled) blink based internal clock (approximately microseconds time). Instead, they blink based rate receive transmit activity. Each time receive transmit operation occurs, turns minimum microseconds. During light traffic, blinks rate, while during heavier traffic LEDs remain Activity Force When asserted, Activity LEDs (ACTLED# FDXLED# Full-Duplex Interrupt modes enabled) turned This higher priority than Activity Force Inactive, register 1Dh. Activity/Link Mode. When enabled, receive output goes active upon acquiring link pulses during receive transmit activity. Qualified Parallel Detect Mode. This allows auto negotiation/parallel detection process qualified with information Advertisement Register.
this set, local BCM5228 device enabled auto-negotiate, far-end device 10BASE-T 100BASE-X auto-negotiating legacy type, local device far-end device, regardless contents Advertisement Register (04h).
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BCM5228
Final Data Sheet
10/24/01
this set, local device compares link speed detected contents Advertisement Register. particular link speed enabled Advertisement Register, local device asserts link. link speed disabled this register, then local device does assert link continues monitoring matching capability link speed.
10BASE-T AUXILIARY ERROR GENERAL STATUS REGISTER
Table 10BASE-T Auxiliary Error General Status Register (Address 28d, 1Ch)
15:14
Name
Reserved MDIX Status MDIX Manual Swap Auto-MDIX Disable Manchester Code Error Frame Error Reserved Reserved Reserved Auto Negotiation Indication Force 100/10 Indication Speed Indication Full-duplex Indication
Description
Ignore when read MDIX MDIX MDIX disabled Force MDIX Enable Auto-MDIX Disable Auto-MDIX Manchester code error (10BASE-T) detection error (10BASE-T) Ignore when read Ignore when read Ignore when read Auto negotiation activated Speed forced manually Speed forced 100BASE-X Speed forced 10BASE-T 100BASE-X 10BASE-T Full-duplex active Full-duplex active
Default
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Note Error bits Auxiliary Error General Status Register read-only latched high.
When certain types errors occur BCM5228, more corresponding error bits become They remain until register read, until chip reset occurs. such errors necessarily result data errors, indicated high value RXER output time error occurs.
MDIX Status. This bit, when read indicates that signals BCM5228 have been swapped. cause this following: MDIX Swap manually
Auto-MDIX function enabled BCM5228 detected cross-over cable.
MDIX Manual Swap. When this signals BCM5228 forced into being swapped.
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Final Data Sheet
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BCM5228
Auto-MDIX Disable. When this Auto-MDIX function disabled BCM5228. Manchester Code Error. Indicates that Manchester code violation received. This only valid during 10BASE-T operation. Frame Error. Indicates that frame (EOF) sequence improperly received, received all. This error only valid during 10BASE-T operation. Auto Negotiation Indication. read-only that indicates whether auto negotiation been enabled disabled BCM5228. combination Control Register logic ANEN input required enable auto negotiation. When auto negotiation disabled, Auxiliary Mode Register returns other times, returns Force 100/10 Indication. read-only that returns value when following cases true:
ANEN F100 low, Control Register been written Control Register been written
When Auxiliary Control Register speed chip 10BASE-T. other cases, either speed forced (auto negotiation enabled), speed forced 100BASE-X.
Speed Indication. read-only that shows true current operation speed BCM5228. indicates 100BASEX operation, while indicates 10BASE-T. Note that while auto negotiation exchange performed, BCM5228 always operating 10BASE-T speed. Full-Duplex Indication. read-only that returns when BCM5228 full-duplex mode. other modes, returns
AUXILIARY MODE REGISTER
Table Auxiliary Mode Register (Address 29d, 1Dh)
15:5
Name
Reserved Activity Disable Link Disable Reserved Block TXEN Mode Reserved
Description
Ignore when read Disable XMT/RCV Activity outputs Enable XMT/RCV Activity outputs Disable Link output Enable Link output
Default
000h
Ignore when read Enable Block TXEN mode Disable Block TXEN mode Ignore when read
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Activity Disable. When disables ACTLED# output pin. When ACTLED# output enabled. Link Disable. When disables Link output pin. When Link output enabled. Block TXEN Mode. When this mode enabled, short IPGs cycles result insertion idles before beginning next packet's symbols.
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Document 5228-DS05-R Section Register Summary Page
BCM5228
Final Data Sheet
10/24/01
AUXILIARY MULTIPLE REGISTER
Table Auxiliary Multiple Register (Address 30d, 1Eh)
10:9
Name
HCD_TX_FDX HCD_T4 HCD_TX HCD_10BASE-T_FDX HCD_10BASE-T Reserved Restart Auto Negotiation Auto Negotiation Complete Acknowledge Complete Acknowledge Detected Ability Detect Super Isolate Reserved 10BASE-T Serial Mode Reserved
(SC)
Description
Auto negotiation result 100BASE-TX full-duplex Auto negotiation result 100BASE-T4 Auto negotiation result 100BASE-TX Auto negotiation result 10BASE-T full-duplex Auto negotiation result 10BASE-T Ignore when read Restart auto negotiation process effect) Auto negotiation process completed Auto negotiation process completed Auto negotiation acknowledge completed Auto negotiation acknowledge detected Auto negotiation waiting ability Super Isolate mode Normal operation Ignore when read Enable 10BASE-T Serial mode Disable 10BASE-T Serial mode Write ignore when read
Default
Read/Write, Read Only, Self Clear, Latched Low, Latched High, Clear after read operation. default values reserved bit(s) when writing reserved bit(s).
Bits. Bits 15:11 Auxiliary Multiple Register five read-only bits that report highest common denominator (HCD) result auto negotiation process. Immediately upon entering Link Pass state after each reset restart auto negotiation, only these five bits will Link Pass state identified this register. bits reset every time auto negotiation restarted BCM5228 reset. Note that their intended application, these bits uniquely identify only after first Link Pass after reset restart auto negotiation. later Link Fault subsequent re-negotiations, ability Link Partner different, more than above bits active. Restart Auto Negotiation. self-clearing that allows auto negotiation process restarted, regardless current status state machine. this work, auto negotiation must enabled. Writing this restarts auto negotiation. Because self-clearing, always returns when read. operation this identical Control Register. Auto Negotiation Complete. This read-only returns after auto negotiation process been completed. remains until auto negotiation process restarted, Link Fault occurs, chip reset. auto negotiation disabled process still progress, returns Acknowledge Complete. This read-only returns after acknowledgment exchange portion auto negotiation process been completed arbitrator state machine exited Complete Acknowledge state. remains this value until auto negotiation process restarted, Link Fault occurs, auto negotiation disabled, BCM5228 reset. adco atio
Page Section Register Summary Document 5228-DS05-R
Final Data Sheet
10/24/01
BCM5228
Acknowledge Detected. This read-only when arbitrator state machine exits Acknowledged Detect state. remains high until auto negotiation process restarted, BCM5228 reset. Ability Detect. This read-only returns when auto negotiation state machine Ability Detect state. enters this state specified time period after auto negotiation process begins, exits after first burst link
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