GENERAL DESCRIPTION AC104Z highly integrated, 3.3V, low-power, fourpor

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GENERAL DESCRIPTION AC104Z highly integrated, 3.3V, low-power, fourpor

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AC104Z Ultra Power 10/100 Quad SMII/RII Ethernet Transceiver
GENERAL DESCRIPTION AC104Z highly integrated, 3.3V, low-power, fourport, 10BASE-T/100BASE-TX, Ethernet transceiver implemented 0.35µm CMOS technology. Multiple modes operation, including normal operation, test mode power-saving mode, available through either hardware software control. Features include interfaces, ENDECs, Scrambler/ Descrambler, Auto-Negotiation (ANeg) with support parallel detection. transmitter includes dualspeed clock synthesizer that only needs external clock source. chip built-in, wave shaping driver circuit both Mbps Mbps, thereby eliminating need external hybrid filter. receiver adaptive equalizer/DC restoration circuit accurate clock/data recovery 100BASE-TX signal. receiver also provides on-chip pass filer/Squelch circuit 10BASE-T signal. interfaces support four prots 10/100 RMII SMII. Media interfaces support four ports 10/100TX/FX.
FEATURES
ports with RMII interface ports with 10/100 media interface Full-duplex half-duplex FEFI 100FX Very small package 128PQFP Very power port Cable detect mode port Power Down mode port Selectable drivers 1.25:1 transformers additional power reduction 3.3V micron CMOS (S/R) tolerant 2.5V capable Fully compliant with IEEE 802.3 802.3u SMII/RMII test labs Baseline wander compensation Multi-function outputs Cable length indicator Reverse polarity detection correction with register indication automatic forced programmable interrupts
Port Port Port Port .Framer .Carrier Detect .4B/5B .Clock Recov. .Link Monitor .Signal Detect TP_PMD .MLT-3 .BLW .Stream Cipher 100TX RXIP/N-TXOP/N(0) FXRP/N-FXTP/N(0) RXIP/N-TXOP/N(1) FXRP/N-FXTP/N(1) RXIP/N-TXOP/N(2) 100RX 10BASE-T 10TX 10RX Serial Management Interface Registers Gen. Test/LED Control AutoNegotiation RXIP/N-TXOP/N(3) FXRP/N-FXTP/N(3) FXRP/N-FXTP/N(2)
Interface
SMII/RMII
Control/Status
PHYAD[4:0]
XTLP/N CKIN TEST[3:0] Drivers
Figure
Functional Block Diagram
AC104Z-DS01-R
16215 Alton Parkway P.O. 57013 Irvine, 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
03/20/02
REVISION HISTORY
Revision AC104Z-DS00-R AC104Z-DS01-R
Date 6/28/01 03/20/02
Change Description Initial Release line items Mode Pins Table: DPLX Modify diagram reflect addition DPLX description. Modify values Table "Thermal Parameters."
Altima Communications, Inc. Wholly Owned Subsidiary Broadcom Corporation P.O. 57013 16215 Alton Parkway Irvine, 92619-7013 2002 Altima Communications, Inc. rights reserved Printed U.S.A.
Preliminary Data Sheet
03/20/02
AC104Z
TABLE CONTENTS
Revision History
Section Functional Description.
Interface RMII SMII. Interrupt Carrier Sense RX_DV. Media Interface 10Base-T Transmit Function Receive Function Link Monitor 100Base-TX Transmit Function Parallel Serial, NRZI, MLT3 Conversion. Receive Function Baseline Wander Compensation Clock/Data Recovery Decoder/De-scrambler. Link Monitor 100Base-FX Transmit Function Receive Function Link Monitor Far-End-Fault-Indication (FEFI) 10Base-T/100Base-TF/FX Multi-Mode Transmit Driver. Adaptive Equalizer Clock Synthesizer. Jabber (Heartbeat) Reverse Polarity Detection Correction.
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AC104Z
Preliminary Data Sheet
03/20/02
Initialization Setup. Hardware Configuration.6 Software Configuration Jumbo Packets. LEDs. Auto-Negotiation. Parallel Detection Diagnostics Loopback Operation Cable Length Indicator Reset Power Clock.
Section Description.
Diagram-AC104Z.10 Descriptions (Media Dependent Interface) Pins SMII (Serial Media Independent Interface) Pins RMII (Reduced Media Independent Interface) Pins Serial Management Interface) Pins Address Pins Mode Pins Pins Miscellaneous Pins JTAG Pins Power Ground Pins Connect Pins
Section Register Descriptions
Legend REGISTERS Registers 8-31 Register Control Register Status Register Identifier Register Identifier
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Preliminary Data Sheet
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AC104Z
Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Transmit Register Polarity Interrupt Level Register Interrupt Control/Status Register Test Register Cable Measurement Register Receive Error Counter Register Operation Mode Register Recent Received Packet Mode Table Common Registers Common Register Operation Mode (Map port Register Common Register Test Mode (Map port Register Common Register LEDSPD Setting (Map port Register Common Register LEDSPD Setting (Map port Register Common Register (Map port Register LEDACT Setting Common Register (Map port Register LEDACT Setting Common Register (Map port Register LEDDPX Setting Common Register (Map port Register LEDDPX Setting Common Register (Map port Register Blink Rate Common Register Port Table Common Register Mask Table 4B/5B Code-Group Table Read/Write Sequence Configurations
Section Electrical Characteristics.
Absolute Maximum Ratings Operating Range Total Power Consumption Characteristics REFCLK XTAL Pins Characteristics-LED/CFG Pins
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AC104Z
Preliminary Data Sheet
03/20/02
BASE-TX Transceiver Characteristics BASE-T Transceiver Characteristics BASE-FX Transceiver Characteristics BASE-T Link Integrity Timing Characteristics DIGITAL TIMING CHARACTERISTICS Power Reset Management Data Interface 100Base-TX/FX 10Base-T RMII Transmit System Timing 100Base-TX/FX 10Base-T RMII Receive System Timing 100Base-TX/FX 10Base-T SMII Transmit System Timing 100Base-TX/FX 10Base-T SMII Receive System Timing Recommended Termination APPLICATION TERMINATION APPLICATION TERMINATION Power Ground Filtering
Section Package Drawing
PACKAGING THERMAL CHARACTERISTICS
Section Thermal Specifications. Section Ordering Information
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Preliminary Data Sheet
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AC104L
LIST FIGURES
Figure Functional Block Diagram Figure AC104Z 128-pin Figure Configurations Figure Power Reset Timing. Figure Management Data Interface Timing. Figure 100Base-TX/FX 10Base RMII Transmit Timing. Figure 100Base-TX/FX 10Base-T RMII Receive Timing. Figure SMII Transmit Timing. Figure SMII Receive Timing. Figure Package Drawing
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AC104L
Preliminary Data Sheet
03/20/02
LIST TABLES
Table Mechanical Dimensions (Millimeters).48 Table Theta-JA Airflow AC104Z (128 PQFP) package.49 Table Thermal Parameters
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AC104Z
AC104Z physical layer device (Phy) integrates 100Base-X 10Base-T functions single four-port chip used Fast Ethernet 10/100 Mbps applications. 100Base-X section consists PCS, PMA, functions, 10Base-T section consists Manchester ENDEC transceiver functions. device performs following functions: 4B/5B MLT3 NRZI Manchester Encoding Decoding Clock Data Recovery Stream Cipher Scrambling De-Scrambling Adaptive Equalization Line Transmission Carrier Sense Link Integrity Monitor Auto-Negotiation (ANeg) SMII RMII connectivity Management Function
AC104Z also provides RMII consortium-compatible Reduced Media Independent Interface (RMII) well SMII communicate with Ethernet Media Access Controller (MAC). Selection Mbps operation either based settings internal Serial Management Interface registers determined on-chip ANeg logic. device operate Mbps with full-duplex half-duplex mode per-port basis. four ports also configured 100Base-FX.
INTERFACE
RMII
Reduced Media Independent Interface (RMII) connects MAC. obtain their clock from common source, such clock oscillator. This clock shared ports within transmitting receiving data individual 2-bit data buses. RXDV muxed together indicate when there valid data receive bus. 100M mode, RXD[1:0] sampled every cycle REFCLK. mode, RXD[1:0] sampled every tenth cycle REFCLK. RXER generated indicate receive error MAC. TX_EN generated indicate when there valid data transmit bus. 100M mode, reads bits from TXD[1:0] each cycle REFCLK. mode, reads bits data from TXD[1:0] every tenth cycle REFCLK. Serial Management Interface (SMI) REFCLK shared between ports Phy. This totals seven pins port plus three Phy, whereas pins port.
SMII
Serial Media Independent Interface (SMII) connects with MAC. obtain their clock, REFCLK, from common source, such clock oscillator. Every REFCLK times, one-bit pulse generated SYNC indicate start each 10-bit serial data word both pins. clock SYNC shared ports within transmitting receiving data individual serial data buses. bits receive CRS, RX_DV, RXD[0:7]. examines line relative SYNC
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Preliminary Data Sheet
03/20/02
RX_DV set. set, then next eight bits data. During inter-packet time, when RX_DV inactive, following definitions applied eight data bits: RX_ER (for previous packet) Speed (0=10M, 1=100M) Duplex (0=Half, 1=Full) Link Down, Jabber (0=OK, 1=Error) Upper Nibble (0=Invalid, 1=Valid) False Carrier (0=none, detected)
bits transmit TX_ER, TX_EN, RXD[0:7]. examines relative SYNC TX_EN set. set, then next eight bits data. mode, REFCLK continue 125MHz, sampled every tenth cycle SYNC. Serial Management Interface (SMI) REFCLK shared between ports Phy. This totals pins port plus four Phy, whereas pins port.
SMI. Phy's internal registers accessible only through 2-wire Serial Management Interface (SMI). MDC, clock input Phy, used latch data instructions Phy. clock speed from MHz. MDIO bi-directional connection used write instructions write data read data from Phy. Each data latched either rising edge MDC. required maintain speed duty cycle, provided half cycle less than data presented synchronous MDC.
MDC/MDIO common signal pair ports design. Each port, therefore, needs have unique Physical Address. Physical Address using pins defined PHYAD[4:2]. These input signals strapped externally sampled reset negated. PHYAD[1:0] addressed each port internal Phy. Internal addresses either depending polarity PHYAD_ST during reset. During idle, responsible pulling MDIO line high state. 1.5K Ohms resistor, therefore, required connect MDIO line Vcc. PHYAD reprogrammed software. beginning read write cycle, sends continuous bits clock rate indicate preamble. follow indicate start frame. read code while write code These codes followed five bits indicate address five bits indicate register address. Then, bits follow allow turn around time. read operation, first high impedance. Neither station assert this bit. During second time, asserts this write operation, station drives first time second time. 16-bit data field then presented. first that transmitted register content. (See "SMI Read/Write Sequence" page
Interrupt. INTR asserted whenever eight selectable interrupt events occur. Assertion state programmable either high through INTR_LEVL register bit. Selection made setting appropriate upper half Interrupt Control Status register. When INTR goes active, interface required read Interrupt Control Status register determine which event caused interrupt. Status bits read only cleared read. When INTR asserted, held high impedance state. Carrier Sense RX_DV. Carrier sense asserted asynchronously pins soon activity detected receive data stream. RX_DV asserted soon valid (Start-of-Stream Delimiter) detected. Carrier sense RX_DV de-asserted synchronously upon detection valid stream delimiter consecutive idle code groups receive data stream. carrier sense asserted valid detected immediately, however, RX_ER asserted instead RX_DV.
10Base-T mode, asserted asynchronously when valid preamble data actvity detected RXIP RXIN pins.
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Preliminary Data Sheet
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AC104Z
half-duplex mode, activated during transmiting receiving data. full-duplex mode, activated during data reception only.
MEDIA INTERFACE
10BASE-T
When configured 10Base-T mode, either through hardware configuration, software configuration, ANeg, supports features parameters industry standards.
Transmit Function Parallel Serial logic used convert single-bit (SMII) two-bit (RMII) data into serial
stream. serialized data directly Manchester encoder synthesizing through output waveshaping driver. waveshaper reduces emission filtering harmonics, thereby eliminating need external filter.
Receive Function received signal passes through low-pass filter, which filters noise from cable, board, transformer. This filter eliminates need 10Base-T external filter. Manchester decoder converts incoming serial stream. Serial Parallel logic used generate single-bit (SMII) two-bit (RMII) data. Link Monitor. 10-Base-T link-pulse detection circuit will constantly monitor RXIP/RXIN pins presence valid link pulses. absence valid link pules, Link Status will cleared Link will de-assert.
100BASE-TX
When configured 100Base-TX mode, either through hardware configuration, software configuration, ANeg, supports features parameters industry standards.
Transmit Function 100Base-TX mode, transmit function converts synchronous single-bit (SMII) two-bit
(RMII) data pair Mbps differential serial data streams. serial data transmitted over network twisted pair cables isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel serial, NRZI, MLT-3 encoding. entire operation synchronous clock. Both clocks generated on-chip clock synthesizer that locked external clock source. transmit data transmitted from signals. 4B/5B encoder replaces first nibbles preamble from frame with /J/K/ code-group pair Start-of-Stream Delimiter (SSD), following onset TX_EN signal. 4B/5B encoder appends /T/R/ code-group pair End-of-Stream Delimiter (ESD) transmission place first IDLE code-groups that follow negation TX_EN signal. encapsulated data stream converted from 4-bit nibbles 5-bit code-groups. During inter-packet gap, when there data present, continuous stream IDLE code-groups transmitted. When TX_ER asserted while TX_EN active, Transmit Error code-group substituted translated code word. 4B/5B encoding bypassed when Reg. 21.1 PCSBP strapped high. 100Base-TX mode, 5-bit transmit data stream scrambled defined TP-PMD Stream Cipher function reduce radiated emissions twisted pair cable. scrambler encodes plain text stream using stream periodic sequence 2047 bits generated recursive linear function X[n] X[n-11] X[n-9] (modulo scrambler reduces peak emissions randomly spreading signal energy over transmitted frequency range, thus eliminating peaks single frequency. repeater applications, where ports transmit same data simultaneously, signal energy spread further using non-repeating sequence each Phy, that scrambled seed unique each different based address. When Dis_Scrm data scrambling function disabled 5-bit data stream clocked directly device's sublayer.
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AC104Z
Preliminary Data Sheet
03/20/02
Parallel Serial, NRZI, MLT3 Conversion. 5-bit data clocked into Phy's shift register with clock clocked with clock convert into serial stream. serial data converted from NRZI format, which produces transition Logic transition Logic further reduce emissions, NRZI data converted MLT-3 signal. conversion offers reduction emissions. This allows system designers meet Class limit.
Whenever there transition occurring NRZI data, there corresponding transition occurring MLT-3 data. NRZI data, changes count up/down direction after every single transition. MLT-3 data, changes count down direction after every transitions. NRZI MLT-3 data conversion implemented without reference timing clock information. conversion requires detecting transitions incoming NRZI data setting count up/down direction MLT-3 data. Asserting FX_SEL high disables this encoding. slew rate transmitted MLT-3 signal controlled reduce emissions. MLT-3 signal after magnetic typical rise/fall time approximately which within target range specified ANSI standard. This guaranteed with either 1.25:1 transformer.
Receive Function 100Base-TX receive path functions inverse transmit path. receive path includes receiver with adaptive equalization restoration front end. also includes MLT-3 NRZI converter, data clock recovery, NRZI/NRZ conversion, Serial-to-Parallel conversion, de-scrambler, 5B/4B decoder. receiver circuit starts with bias differential RX+/- inputs, followed with low-pass filter filter high frequency noise from transmission channel media. energy-detect circuit also added determine whether there signal energy media, which useful power-saving mode. amplification ratio slicer's threshold on-chip bandgap reference. Baseline Wander Compensation. 100Base-TX data stream always balanced. transformer blocks components incoming signal, thus offset differential receive inputs drift. shifting signal level, coupled with non-zero rise fall times serial stream cause pulse-width distortion, which creates jitter possible increase error rates. restoration circuit, therefore, needed compensate attenuation component. This implements patent-pending restoration circuit. Unlike traditional implementation, circuit does need feedback information from slicer clock recovery circuit. This design simplifies circuit design eliminates random/systematic offset receive path. 10BaseT 100Base-FX modes, baseline wander correction circuit required, therefore disabled. Clock/Data Recovery. equalized MLT-3 signal passes through slicer circuit, gets converted NRZI format. uses proprietary, mixed-signal, phase locked loop (PLL) extract clock information from incoming NRZI data. extracted clock used re-time data stream data boundaries. transmit clock locked clock input (RMII) clock input (SMII) while receive clock locked incoming data streams. When initial lock achieved, switches data stream, extracts clock, uses framing recovered data. requires external components operation high noise immunity jitter. provides fast phase alignment locks data transition. data/clock acquisition time after power-on less than transitions. maintain lock run-lengths data bits absence signal transitions. When valid data present, that when de-asserted, switches locks REFCLK. Decoder/De-scrambler. de-scrambler detects state transmit Linear Feedback Shift Register (LFSR) looking sequence representing consecutive idle codes. de-scrambler acquires lock data stream recognizing IDLE bursts more bits locks frequency de-ciphering LFSR.
Once lock acquired, device operate with inter-packet-gap (IPG) Before lock acquired, however, de-scrambler needs minimum consecutive idles between packets acquire lock. de-ciphering logic also tracks number consecutive errors received while RX_DV asserted. Once error counter exceeds limit, currently consecutive errors, logic assumes that lock been lost, decipher circuit resets itself. process regaining lock starts again. Stream cipher descrambler used 100Base-FX 10Base-T modes.
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AC104Z
Link Monitor. Signal level detected through squelch detection circuitry. signal detect (SD) circuit allows equalizer assert high whenever peak detector detects post-equalized signal with peak ground voltage greater than This approximately percent normal signal voltage level. addition, energy level must sustained longer than signal detect signal stay gets de-asserted approximately after energy level drops consistently below from peak ground.
link signal forced during local loopback operation (Loopback register set). forced 100Base-TX mode, when cable unplugged valid signal detected receive pair, link monitor enters Link Fail State transmits NLPs. When valid signal detected minimum time, link monitor enters Link Pass State transmits MLT-3 signal.
100BASE-FX
When port configured 100Base-FX mode, either through hardware configuration software configuration (100Base-FX does support ANeg), supports features parameters industry standards.
Transmit Function serialized data bypass scrambler 4B/5B encoder mode. output data
NRZI PECL signals. PECL level signals used drive Fiber-transmitter.
Receive Function 100Base-FX mode, signal received through PECL receiver inputs, directly passed clock recovery circuit data/clock extraction. mode, scrambler/de-scrambler cipher function bypassed. Link Monitor. 100Base-FX mode, external fiber-optic receiver performs signal energy detection function communicates this information directly Phy's pin. Far-End-Fault-Indication (FEFI). ANeg provides mechanism inform link partner that remote fault occurred.ANeg, however, disabled 100Base-FX applications. alternative in-band signaling function (FEFI) used signal remote fault condition. FEFI stream consecutive followed logic This pattern repeated three times. FEFI signals under three conditions:
When activity received from link partner. When clock recovery circuit detects signal error lock error. When management entity sets transmit Far-End-Fault bit.
FEFI mechanism enabled default 100Base-FX mode, disabled 100Base-TX 10Base-T modes. register setting changed software after reset.
10BASE-T/100BASE-TF/FX
Multi-Mode Transmit Driver. multi-mode driver transmits MLT-3 coded signal 100Base-TX mode, NRZI coded signal 100Base-FX mode, Manchester coded signal 10Base-T mode.
100Base-FX mode, filtering performed. transmit driver uses current drive output that well balanced produces noise PECL signal. PECL voltage levels produced with resistive terminations. 10BaseT mode, high frequency pre-emphasis performed extend cable-driving distance without external filter. pulses also driven through 10BaseT driver. 10BaseT 100BaseTX transmit signals multiplexed transmit output driver. This arrangement results using same external transformer both 10BaseT 100BaseTX. driver output level built-in bandgap reference external resistor connected IBREF pin. resistor sets output current modes operation. TXOP/N outputs open drain devices with serial source resistance max. When transformer used, current rating 2Vp-p MLT-3 signal, 5Vp-p Manchester signal. 1.25:1 transmit transformer percent reduction output-driver power, which decreases
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AC104Z
Preliminary Data Sheet
03/20/02
drive current 100Base-TX operation, 10Base-T operation.
Adaptive Equalizer. designed accommodate maximum meters CAT-5 cable. AT&T 1061 CAT-5 cable this length typically attenuation MHz. typical attenuation 100-meter cable worst case 100m cable attenuation around 24-26 defined TP-PMD specification.
amplitude phase distortion from cable causes inter-symbol interference (ISI) which makes clock data recovery difficult. adaptive equalizer designed closely match inverse transfer function twisted-pair cable. equalizer change equalizer frequency response according cable length. equalizer tunes itself automatically cable, compensating amplitude phase distortion introduced cable.
Clock Synthesizer. includes on-chip clock synthesizer that generates clocks 100Base-TX circuitry. clock generator uses fully differential cell that introduces very jitter. Zero Dead Zone Phase Detection method implemented design provides excellent phase tracking. charge pump with charge sharing compensation also included further reduce jitter different loop filter voltages. on-chip loop filter eliminates need external components minimizes external noise sensitivity. Only external (RMII) (SMII) crystal clock source required reference clock.
After power-on reset, clock synthesizer generates clock output until 100Base-X operation mode selected.
Jabber (Heartbeat). After transmitter exceeds jabber timer (46mS), transmit loopback functions disabled signal asserted. After TX_EN goes more than transmitter reactivates gets de-asserted. Setting Jabber Disable disables jabber function.
When test enabled, pulse with 5-15BT asserted after each transmitted packet. enabled 10Base-T default, disabled Test Inhibit.
Reverse Polarity Detection Correction. Certain cable plants have crossed wiring twisted pairs; reversal TXIN TXIP. Under normal circumstances this causes receive circuitry reject data. When Auto Polarity Disable cleared, detects that either NLPs burst FLPs inverted automatically reverses receiver's polarity. polarity state stored Reverse Polarity bit. Auto Polarity Disable set, then Reverse Polarity written force polarity reversal receiver.
INITIALIZATION SETUP
HARDWARE CONFIGURATION
Several different states operation chosen through hardware configuration. External pins pulled either high reset time. combination high values determines power state device. Many these pins multi-function pins that change their meaning when reset ends.
SOFTWARE CONFIGURATION
Several different states operation chosen through software configuration. Refer "SMI" above well "Register Descriptions" page
Jumbo Packets. FIFOs internal logic have been designed handle Jumbo packets 9,000 bytes. This feature enabled disabled through either hardware software setup. LEDs. Each four ports three individual outputs indicate dynamic status associated port. These
multi-function pins inputs during reset output pins thereafter. level these pins during reset determines their active output states. multi-function pulled during reset select particular function, then that output
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Page Section Functional Description Document AC104Z-DS01-R
Preliminary Data Sheet
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AC104Z
would become active low, vice versa; therefore, circuit must designed accordingly. (See "LED Configurations" page 34.) information displayed LEDs determined contents Common Registers. Common Register selections allow each individual turned directly, turned off, blinked event. possible events Collision, Auto-Negotiation, Full-Duplex, 100Base-TX, Activity, Link. combination events directed associated with each port. default ports LEDSPD Active=100Mbps LEDACT Active=Link, Blink=Activity LEDDPX Active=FullDuplex, Blink=Collision
AUTO-NEGOTIATION
definition, 10/100 Transceiver either Mbps over Twisted Pair Copper (10Base-T), Mpbs over Twisted Pair Copper (100Base-TX), Mpbs over Fiber Optics (100Base-FX). addition, canrun either half-duplex (repeater mode) full-duplex mode. determine operational state, hardware selects software selects while also supporting Auto- Negotiation Parallel Detection. 100Base-FX mode, selection must done through hardware configuration. There support Auto-Negotiation interface. environment 802.3 standards limit possible combinations. Valid operating states 10Base-T Half Duplex 10Base-T Full Duplex 100Base-TX Half Duplex 100Base-TX Full Duplex 100Base-FX Half Duplex 100Base-FX Full Duplex
hardware configured force above valid modes. forcing mode, runs only that mode, thus limiting locations where product operate. negotiate mode operation twisted pair environmentby using Auto-Negotiation mechanism defined clause IEEE 802.3u specification. ANeg enabled disabled hardware (ANEGA pin) software (Register 0.12) control. When ANeg enabled, chooses mode operation advertising abilities comparing them with ability received from link partner. configured advertise 100Base-TX 10Base-T operating either full- half-duplex. Register contains current capabilities, speed duplex, Phy, determined through hardware selects chip defaults. contents Register sent link partner during ANeg process using Fast Link Pulses (FLPs). string each which particular meaning, total which called Link Code Word. After reset, software change these bits from back from Therefore, hardware priority over software. When ANeg enabled, sends FLPs during following conditions: Power Link loss. Restart ANeg command software.
During this period, continually sends FLPs while monitoring incoming FLPs from link partner determine their optimal mode operation. FLPs detected during this phase operation, Parallel Detection mode entered (see "Parallel Detection" page When receives three identical link code words (ignoring acknowledge bit) from link partner, stores these code words Register sets acknowledge generated FLPs, waits receive three identical code words
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Preliminary Data Sheet
03/20/02
with acknowledge from link partner. Once this occur, configures itself highest technology that common both ends. technology priorities 100Base-TX, full-duplex 100Base-TX, half-duplex 10Base-T, full-duplex 10Base-T half-duplex.
Once ANeg complete, Register set, Register 1.[14:11] reflects negotiated speed duplex mode, enters negotiated transmission reception state. This state does change until link lost, reset through either hardware software, restart negotiation (Register 0.9) set.
PARALLEL DETECTION
Because there many devices field that support ANeg process, with which must still communicate, necessary detect link through Parallel Detection process. parallel detection circuit enabled absence FLPs. circuit able detect Normal Link Pulse (NLP) 10Base-T receive data 100Base-TX idle
mode operation configured based technology incoming signal. above detected, device automatically configures match detected operating speed half-duplex mode. This ability allows device communicate with legacy 10Base-T 100Base-TX systems while maintaining flexibility Auto-Negotiation.
DIAGNOSTICS
Loopback Operation. Local Loopback provided testing enabled writing Register 0.14 (LPBK)
Local Loopback routes transmitted data through transmit path back receiving path's clock data recovery module. loopback data presented 5-bit symbol format. This loopback checks operation 5bit symbol decoder phase locked loop circuitry. Local Loopback, output forced logic TXOP/N outputs tri-stated.
Cable Length Indicator. detect approximate length cable which it's attached display
result Register 20.[7:4]. reading [0000] translates meters cable used, [0001] translates meters cable, [1111] translates metes cable. cable length value used network manager determine proper connectivity cable manage cable plant distribution
RESET POWER
reset three ways: During initial power Hardware Reset: logic signal pulse width applied RST* pin. Software Reset: Write Reg. 0.15.
device's built-in power management features significantly reduce power consumption. Separate power supply lines power 10BaseT circuitry 100BaseTX circuitry. circuits, therefore, turned-on turned-off independently. When operate 100Base-TX mode, 10Base-T circuitry powered down, vice versa. following power management features supported: Power down mode: This achieved writing Register 0.11 pulling PWRDN high. During power down
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Page Section Functional Description Document AC104Z-DS01-R
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AC104Z
mode, device still able interface through MDC/MDIO management interface. Energy-detect/power-saving mode: Energy-detect mode turns power select internal circuitry when there live network connected. Energy Detect (ED) circuit always turned monitor signal energy present media. circuitry also powered ready respond management transaction. transmit circuit still sends link pulses with minimum power consumption. valid signal received from media, device powers resumes normal transmit/receive operation. (Patent Pending) Reduced Transmit Drive Strength mode: Additional power saving gained level designing with 1.25:1 turns ration magnetic asserting TP125 reset.
CLOCK
clock input must clock oscillator measured MHz-100PPM SMII MHz-100PPM RMII.
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AC104Z
Preliminary Data Sheet
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Section ription
DIAGRAM-AC104Z
Figure
AC104Z 128-pin
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AC104Z
DESCRIPTIONS
Many pins these devices have multiple functions; these multi-function pins designated bolded numbers. Designers must ensure that they have identified modes operation before final design. assignments shown above description tables subject change without notice. Contact Altima Communications Inc. before implementing design based information provided this data sheet. Signal types: Inputs Outputs High Impedance Internal Pull Internal Pull Down Analog Signal Active Signal Connect
Note
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AC104Z
Preliminary Data Sheet
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(MEDIA DEPENDENT INTERFACE) PINS
Name RXIN(0) RXIN(1) RXIN(2) RXIN(3) RXIP(0) RXIP(1) RXIP(2) RXIP(3) TXON(0) TXON(1) TXON(2) TXON(3) TXOP(0) TXOP(1) TXOP(2) TXOP(3) FXRN(0) FXRN(1) FXRN(2) FXRN(3) FXRP(0) FXRP(1) FXRP(2) FXRP(3) FXTN(0) FXTN(1) FXTN(2) FXTN(3) FXTP(0) FXTP(1) FXTP(2) FXTP(3) SDP(0) SDP(1) SDP(2) SDP(3) Type Description Receiver input Negative both 10Base-T 100Base-TX.
Receiver input Positive both 10Base-T 100Base-TX.
Transmitter output Negative both 10Base-T 100Base-TX.
Transmitter output Positive both 10Base-T 100Base-TX.
Receiver input Negative 100Base-FX.
Receiver input Positive 100Base-FX.
Transmitter output Negative 100Base-FX.
Transmitter output Positive 100Base-FX.
Signal Detect Input. Indicates signal quality status fiber-optic link 100Base-FX mode. When signal quality good, should driven high relative pin.
bias level that works partnership with SDP[0.3] pins. sets switch threshold SDP[0.3] pins. should externally volt most applications.
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AC104Z
SMII (SERIAL MEDIA INDEPENDENT INTERFACE) PINS
Name TXD(0) TXD(1) TXD(2) TXD(3) RXD(0) RXD(1) RXD(2) RXD(3) SYNC REFCLK Type Description SMII Transmit Data. will source TXD(n) synchronous with REFCLK.
SMII Receive Data. will source RXD(n) synchronous with REFCLK.
Synchronous with REFCLK indicate start stream. Reference Clock Input-125 MHz-100PPM
RMII (REDUCED MEDIA INDEPENDENT INTERFACE) PINS
Name TXD[1:0](0) TXD[1:0](1) TXD[1:0](2) TXD[1:0](3) TX_EN(0) TX_EN(1) TX_EN(2) TX_EN(3) RXD[1:0](0) RXD[1:0](1) RXD[1:0](2) RXD[1:0](3) CRS_DV(0) CRS_DV(1) CRS_DV(2) CRS_DV(3) RX_ER(0) RX_ER(1) RX_ER(2) RX_ER(3) REFCLK 107,108 94,95 75,76 61,66 98,99 88,89 70,71 56,57 Type Description RMII Transmit Data. will source TXD[1:0](n) synchronous with REFCLK when TX_EN(n) asserted.
RMII Transmit Enable. TX_EN(n) asserted high indicate that valid data transmission presented TXD[1:0](n).
RMII Receive Data. will source RXD[1:0](n) synchronous with REFCLK when CRS_DV(n) asserted.
CRS_DV(n) asserted high when media non-idle.
RMII Receive Error. When RX_ER asserted high, indicates error been detected during frame reception.
Reference Clock Input MHz-100PPM
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AC104Z
Preliminary Data Sheet
03/20/02
SERIAL MANAGEMENT INTERFACE) PINS
Name MDIO INTR Type I/O, Description Management Data Input/Output. Bi-directional data interface. external 1.5K pull-up resistor required specified IEEE-802.3). Management Data Clock. clock sourced transfer MDIO data. Interrupt. Registers polarity sources. INTR high impedance output; pull-up pull-down resistor needed.
ADDRESS PINS
Name PHYAD_ST Type I/O,D Description reset 0-XXX00, 1-XXX01, 2-XXX10, 3-XXX11 reset 0-XXX01, 1-XXX10, 2-XXX11, 3-XXX00 Address [4:2]. These pins three MSBs address. PHYAD [1:0] internally wired four ports. (See PHYAD_ST) PHYAD also determines scramble seed, which helps reduce when there multiple ports switching same time.
PHYAD PHYAD PHYAD
I/O,U I/O,U I/O,U
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Preliminary Data Sheet
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AC104Z
MODE PINS
Name FX_EN(0) FX_EN(1) FX_EN(2) FX_EN(3) TP125 FORCE100 Type AI/O Description Enable (per port). Pulled upon reset sets Port(n) mode. Pull above upon reset sets port(n) 100FX mode.
Transformer Ratio. Pulled upon reset selects transmit transformer ratio 1.25:1. Pulled high selects transformer ratio. FORCE100: Force 100Base-X Operation. When this signal pulled high ANEGA upon reset, ports forced 100Base-TX operation. mode, this should pulled High. When asserted ANEGA low, ports forced 10Base-T operation. When ANEGA high, FORCE100 effect operation. Scrambler Enable. Pulled upon reset bypasses scrambler. Pulled high enables scrambler. This reset read input Copper interface. mode, this floating. Auto-Negotiation Ability. Asserted high means auto-negotiation enabled while means manual selection through DPLX FORCE100. mode, this should pulled Low. Burn-In mode. Burn-in mode reliability assurance control. This reserved internal testing only. Mode1 Mode0 SMII SMII with Jumbo Packets RMII Invalid
SCRAM_EN
ANEGA
BURN_IN* MODE0 MODE1
I/O,U I/O,D
DPLX
Reset read input. Pull High Full Duplex mode, pull Half Duplex mode. mode, this should pulled High.
PINS
Name LEDDPX[0] LEDDPX[1] LEDDPX[2] LEDDPX[3] LEDACT LEDACT LEDACT LEDACT Type I/O,U I/O,U Descriptiona Port[n] Duplex LED. Active state indicates Full-Duplex Collision Half-Duplex mode.
I/O,U I/O,U I/O,U
Port[n] Activity/Link LED. Active state indicates valid link. When there receive transmit activity, toggles between high intervals.
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LEDSPD[0] LEDSPD[1] LEDSPD[2] LEDSPD[3]
I/O,U I/O,U I/O,U I/O,U
Port[n] Speed LED. Active state indicates 100Base-TX mode.
Polarity LEDs determined polarity mode pins. example.
MISCELLANEOUS PINS
Name RST* Type Description Reset. active input forces chip known initialization state. Setting Register 0.15 asserts software reset, which same functionality hardware reset. Must tied directly MCLK_OUT. Must tied directly MCLK_IN. Reference Bias Resistor. Must tied analog ground through external (1%) resistor. Test. Outputs during test mode.
MCLK_IN MCLK_OUT IBREF TST[0] TST[1] TST[2] TST[3]
A/I,O
JTAG PINS
Name TRST Type Description Boundary Scan Input Boundary Scan Control Boundary Scan Reset Boundary Scan Clock Boundary Scan Output
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Preliminary Data Sheet
03/20/02
AC104Z
POWER GROUND PINS
Name OVDD OGND CVDD CGND AVDD 121,122 Type Description Digital +3.3V power supply I/O. Digital ground I/O. Digital +3.3V power supply Core logic. Digital ground Core logic. +3.3V power supply Analog circuit.
AGND
Ground Analog circuit.
GAVDD GAGND VDD_PLL GND_PLL
+3.3V power supply common analog circuits. Ground common analog circuits. Power supply SMII circuit. Ground SMII circuit.
CONNECT PINS
Name 101, 102, 128, 123, 127, 124,126, Type Description Connect.
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AC104Z
Preliminary Data Sheet
03/20/02
Section egis iptions
first seven registers register defined specification. addition these required registers several Altima Communications Inc.-specific registers. There reserved registers and/or bits that Altima internal only. following standard registers supported. Register numbers decimal format; values hexadecimal format. When writing registers, recommended that read/modify/write operation performed, unintended bits unwanted states. This applies registers, including those with reserved bits.
Note
LEGEND
following annotations applicable registers: Read Write Access Self Clearing Latch until cleared reading Read Only Cleared Read Latch High until cleared reading
REGISTERS
Register Description Control Register Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Next Page Advertisement Register Default 1000 7849 0022 5542 01E1 0001 0004 2001
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Preliminary Data Sheet
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AC104Z
REGISTERS 8-31
Register 8-15 24-27 28-31 Description Reserved Polarity Interrupt Level Register Interrupt Control/Status Register Reserved Test Register Cable Measurement Register Receive Error Count Power Management Register Operation Mode Register Reserved Global Register Default XXXX 1000 0000 XXXX 0000 XXXX 0000 XXFF 0000 XXXX XXXX
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AC104Z
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03/20/02
REGISTER CONTROL
0.15 Name Reset Description reset. This self-clearing. Enable loopback mode. This loopbackS ignoreS activity cable media. Normal operation. Mbps Mbps. Enable Auto-Negotiate process (overrides 0.13 0.8). Disable Auto-Negotiate process. Mode selection controlled 0.13 through mode pin. Power down. blocks except will turned off. Setting PWRDN high will achieve same result. Normal operation. Normal operation. Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. Enable collision test, which issues signal response assertion TX_EN signal. Collision test disabled PCSBP high. Collision test enabled regardless duplex mode. Disable test. Mode RW/SC Default
0.14
Loopback
0.13
Speed Select
0.12
ANeg Enable
0.11
Power Down
0.10
Isolate
Restart ANeg
RW/SC
Duplex Mode
Collision Test
0.[6:0]
Reserved
Refer "Mode Table" page
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Page Section Register Descriptions Document AC104Z-DS01-R
Preliminary Data Sheet
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AC104Z
REGISTER STATUS
1.15 1.14 Name 100Base-T4 100Base-TX Full Duplex 100Base-TX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex Reserved Preamble Suppression ANeg Complete able perform management transaction without MDIO preamble. management interface needs minimum bits preamble after reset. Auto-Negotiate process completed. Registers valid after this set. Auto-negotiate process completed. Remote fault condition detected. remote fault. This remain sets until cleared reading register Able perform Auto-Negotiation function, default value determined ANEGA pin. Unable perform Auto-Negotiation function. Link established. link fails, this cleared remains until register read again. Link gone down. Jabber condition detect. Jabber condition detected. Extended register capable. This tied permanently Description Permanently tied zero indicates 100BaseT4 capability. 100BaseTX full duplex capable. 100BaseTX full duplex capable. 100BaseTX half duplex capable. half-duplex capable. 10BaseT full-duplex capable. 10BaseT full-duplex capable. 10BaseT half-duplex capable. 10BaseT half-duplex capable. Mode Default
1.13
1.12
1.11
1.[10:7]
Remote Fault
RO/LH
ANeg Ability
Link Status
RO/LL
Jabber Detect
RO/LH
Extended Capability
Refer "Mode Table" page
REGISTER IDENTIFIER
Reg.bit 2.[15:0] Name OUIa Description Composed third through eigth bits Organizationally Unique Identifier (OUI), respectively. Mode Default 0022(H)
Based 0010A9 (hexadecimal).
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REGISTER IDENTIFIER
3.[15:10] 3.[9:4] 3.[3:0] Name OUIa Model Number Revision Number Description Assigned 19th through 24th bits OUI. Six-bit manufacturer's model number; encoded 010001. Four-bit manufacturer's revision number; example, 0011 stands Revision Mode Default 010101 010100 0011
Based 0010A9 (hexadecimal)
REGISTER AUTO-NEGOTIATION ADVERTISEMENT
4.15 Name Next Page Description Next Page enabled. Next Page disabled. This internally after receiving consecutive consistent bursts. Advertises that this device detected Remote Fault. remote fault detected. Mode Default
4.14 4.13
Acknowledge Remote Fault
4.[12:11] 4.10
Reserved FDFC Full-Duplex Flow Control Advertise that DTE(MAC) implemented both optional control sublayer pause function specified clause annex 802.3u. does support flow control Technology supported. This always
100Base-T4
100Base-TX Full 100BaseTX full duplex capable. plex 100BaseTX full duplex capable. 100Base-TX 100BaseTX half duplex capable. half duplex capable. 10BaseT full duplex capable. 10BaseT full duplex capable. 10BaseT half duplex capable. 10BaseT half duplex capable. [00001] IEEE 802.3.
10Base-T Full Duplex 10Base-T
4.[4:0]
Selector Field
00001
Refer "Mode Table" page
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Preliminary Data Sheet
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AC104Z
REGISTER AUTO-NEGOTIATION LINK PARTNER ABILITY
5.[15:0] Name Technology Description Technology capability field, which indicates technology capability link partner. definition same Register 4.15:0. When this register used Next Page Message, definition same Register 7.15:0. Mode Default 0001
REGISTER AUTO-NEGOTIATION EXPANSION
6.[15:5] Name Reserved Parallel Detection Fault Fault detected parallel detection logic, this fault more than technology detecting concurrent linkup condition. This cleared only using management interface read Register fault detected parallel detection logic. Link partner supports next page function. Link partner does support next page function. Next page supported. This when link code word been received into Auto-Negotiation Link Partner Ability Register. This cleared upon read this register. Link partner Auto-Negotiation capability. Link partner does have Auto-Negotiation capability. Description Mode RO/LH Default
Link Partner Next Page Able Next Page Able Page Received
RO/LH
Link Partner ANegAble
REGISTER AUTO-NEGOTIATION NEXT PAGE TRANSMIT
7.15 Name Description Another Next Page Transfer desired. other Next Page Transfer desired. Mode Default
7.14 7.13
Reserved Message page. Un-formatted page. Will comply with message. comply with message. Previous value transmitted link code word equals Previous value transmitted link code word equals Message/Un-formatted Code Field.
7.12
ACK2
7.11
TOG_TX
17.[10:0]
CODE
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03/20/02
REGISTER POLARITY INTERRUPT LEVEL
16.[15:14] 16.13 Name Reserved TXJAM send pattern Normal operation Description Mode Default
16.12 16.11
Reserved Test Inhibit Disable 10BaseT testing. Enable 10BaseT testing, which generates pulse following completion packet transmission.
16.[10:6] 16.5
Reserved Auto Polarity Disable Reverse Polarity Disable Auto Polarity detection/correction. Enable Auto Polarity detection/correction. Reverse Polarity when Register 16.5 Normal Polarity when Register 16.5 Register 16.5 writing this reverses polarity transmitter.
16.4
16.[3:0]
Reserved
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Preliminary Data Sheet
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AC104Z
REGISTER INTERRUPT CONTROL/STATUS
17.15 17.14 17.13 17.12 17.11 17.10 Name Jabber_IE Rx_Er_IE Page_Rx_IE PD_Fault_IE LP_Ack_IE Link_Status_ Change_IE R_Fault_IE ANeg_Comp_IE Jabber_Int Rx_Er_Int Page_Rx_Int PD_Fault_Int LP_Ack_Int Link_Status_ Changes R_Fault_Int ANeg _Comp Description Jabber Interrupt Enable. Receive Error Interrupt Enable. Page Received Interrupt Enable. Parallel Detection Fault Interrupt Enable. Link Partner Acknowledge Interrupt Enable. Link Status Change Interrupt Enable. Mode Default
17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2
Remote Fault Interrupt Enable. Auto-Negotiation Complete Interrupt Enable. This when jabber event detected. This when RX_ER transitions high. This when page received during ANeg. This when parallel detect fault detected. This when with acknowledge received. This when link status changes.
17.1 17.0
This when remote fault detected. This when ANeg complete.
REGISTER TEST
19.[15:9] 19.8 19.[7:6] 19.[4:2] 19.5 19.4 19.[3:1] Name Reserved TX_FEF Reserved Reserved Watch-dog timer dis- disable watch-dog timer able Low_pwr_mode Reserved disable power management Force transmit Description Mode Default 0000000
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REGISTER CABLE MEASUREMENT
20.[15:9] 20.[7:4] Name Reserved Cable measurement capability These bits used cable-length indicator. bits incremented from 0000 1111, with increment approximately meters. equivalent with increment MHz. value read back from equalizer, measured value absolute. Description Mode Default
20.[3:0]
Reserved
REGISTER RECEIVE ERROR COUNTER
21.[15:0] Name RX_ER Counter Description Count Receive Error Events. Mode Default
REGISTER OPERATION MODE
23.15 Name Enable Description Enable function. function enabled only when this register FX_EN set. port operate mode. port operated mode only when auto-negotiation disabled, speed Mbps. FX_MODE will default auto-negotiation disable. Mode Default
23.14
23.13 23.12 23.11
Reserved Cmsel Scramble Disable Select single ended input signal Disable scrambler. Enable scrambler.
23.[10:8] 23.7 23.6 23.[5:0] 23.15
Reserved Reserved Reserved Reserved Enable Enable function. function enabled only when this register FX_EN set.
XXXXXX
Refer "Mode Table" page
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Preliminary Data Sheet
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AC104Z
REGISTER RECENT RECEIVED PACKET
24.[15:0] Name Description system link testing. Mode Default 0000H
MODE TABLE
FX_En(n) Force Scram_En ANEGA Condition Port 100Base-FX Port Auto Negotiate 10Base-T 100Base-TX Port Forced 100Base-TX Port Forced 10Base-T Port Forced 100Base-TX (unscrambled)
COMMON REGISTERS
Register Description Operation Mode Register(Map Port Register Test Mode Register (Map Port Register Reserved LEDSPD Settings1 (Map Port Register LEDSPD Settings (Map Port Register LEDACT Setting1(Map Port Register LEDACT Setting (Map Port Register LEDDPX Setting1(Map Port Register LEDDPX Setting (Map Port Register Blink Rate (Map Port Register Default 00X4 1000 XXXX 0000 0000 0002 0100 0020 XXXX 0010
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03/20/02
COMMON REGISTER OPERATION MODE (MAP PORT REGISTER
0.28.[15:7] 0.28.[6:4] 0.28.3 Name Reserved Reserved Interrupt Level Interrupt active low. Interrupt active high. Event select. Receive Activity. Activity Description Mode Default 00000000
0.28.2
Select
0.28.1 0.28.0
Reserved Tp125 Select 1:1.25 Transformer.
COMMON REGISTER TEST MODE (MAP PORT REGISTER
0.29.15 0.29.[14:10] Name Reserved FIFO Depth 00100 Normal operation. 10111 Jumbo packet. Description Mode Default 00100
0.29.[9:2] 0.29.1
Reserved Global Address Enable Reduce Timer Reserved Write address writes phys chip. Normal operation. Reduce timer auto-negotiation testing.
00000000
0.29.0 0.29.15
COMMON REGISTER LEDSPD SETTING (MAP PORT REGISTER
2.28.[15:12] Name Force Description Force Force off. "Common Register Port Table" page Force off. Force "Common Register Port Table" page Event will cause blink. Masked. "Common Register Mask Table" page Mode Default 0000
2.28.[11:8]
Force
0000
2.28.[7:0]
Mask Blink
00000000
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Preliminary Data Sheet
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AC104Z
COMMON REGISTER LEDSPD SETTING (MAP PORT REGISTER
2.29.[15:8] Name Mask Description Event turns LED. Masked. "Common Register Mask Table" page Event turns LED. Masked. "Common Register Mask Table" page Mode Default 00000100
2.29.[7:0]
Mask
00000000
COMMON REGISTER (MAP PORT REGISTER LEDACT SETTING
2.30.[15:12] Name Force Description Force Force off. "Common Register Port Table" page Force off. Force "Common Register Port Table" page Event causes blink. Masked. "Common Register Mask Table" page Mode Default 0000
2.30.[11:8]
Force
0000
2.30.[7:0]
Mask Blink
00000010
COMMON REGISTER (MAP PORT REGISTER LEDACT SETTING
2.31.[15:8] Name Mask Description Event turn LED. Masked. "Common Register Mask Table" page Event turns LED. Masked. "Common Register Mask Table" page Mode Default 00000001
2.31.[7:0]
Mask
00000000
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COMMON REGISTER (MAP PORT REGISTER LEDDPX SETTING
3.28.[15:12] Name Force Description Force Force off. "Common Register Port Table" Force off. Force "Common Register Port Table" Event causes blink. Masked. "Common Register Mask Table" page Mode Default 0000
3.28.[11:8]
Force
0000
3.28.[7:0]
Mask Blink
00100000
COMMON REGISTER (MAP PORT REGISTER LEDDPX SETTING
3.29.[15:8] Name Mask Description Event turns LED. Masked. "Common Register Mask Table" page Event turn LED. Masked. "Common Register Mask Table" page Mode Default 00001000
3.29.[7:0]
Mask
00000000
COMMON REGISTER (MAP PORT REGISTER BLINK RATE
3.30.[15:8] 3.30.[7:0] Name Reserved Blink Rate blink rate. blink rate this number Default Description Mode Default 00000000 00010000
COMMON REGISTER PORT TABLE
Port Port Port Port Port Port Port Port
Note
Bits 15-12 have higher priority than bits 11-8.
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Preliminary Data Sheet
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AC104Z
COMMON REGISTER MASK TABLE
Applicable Applicable Applicable Applicable Collision AutoNegotiation AutoNegotiation Full-Duplex 100Base-TX Activity Link
Collision
Full-Duplex
100Base-TX
Activity
Link
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03/20/02
4B/5B CODE-GROUP TABLE
Code Group[4:0] 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 Symbol Name (TXD/RXD [3:0]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Idle Control Code 11111 11000 10001 01101 00111 0000 0101 0101 Undefined Undefined Inter-Packet Idle; used inter-stream fill code. Start stream delimiter, part always pair with symbol. Start stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. Description Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
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Preliminary Data Sheet
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AC104Z
Code Group[4:0]
Symbol Name
(TXD/RXD [3:0]) Invalid Code
Description
00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Transmit Error; used send HALT code-group Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code
READ/WRITE SEQUENCE
Pream bits) Read Write Start bits) OpCode bits) PHYAD bits) AAAAA AAAAA REGAD bits) RRRRR RRRRR TurnAround bits) Data bits) Idle
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03/20/02
CONFIGURATIONS
Mode Link Transmit Receive Collision Transmit Receive 100M Link 100M Transmit 100M Receive Collision 100M Transmit 100M Receive during collision during collision LEDDPX LEDACT TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE LEDSPD
Multi Function pulled high reset. Multi Function pulled reset.
Figure
Configurations
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AC104Z
ction Electr ristics
Note
following electrical characteristics design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Supply Referenced Digital Input Voltage Output Voltage -55oC +150oC -0.5V +5.0V -0.5V -0.5V
OPERATING RANGE
Operating Temperature (Ta) Supply Voltage Range (Vcc) -40oC +85oC 2.97V 3.63V
TOTAL POWER CONSUMPTION
Parameter Supply Current (per port) Symbol Conditions Base-T, Idle Base-T, Normal activity Base-TX Base-FX 10/100 Base-TX, power without cable Power down Units
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CHARACTERISTICS
Parameter Input Voltage High Input Voltage Input Current Output Voltage High Output Voltage Output Current High Output Current Input Capacitance Output Transition Time Tristate Leakage Current |Ioz| Symbol 3.15V 3.45V VCC-0.4 Conditions Units
REFCLK XTAL PINS
Parameter Input Voltage Input Voltage High Input Clock Frequency Tolerance Input Clock Duty Cycle Input Capacitance Symbol Conditions Units
CHARACTERISTICS-LED/CFG PINS
Parameter Output Voltage Output High Voltage Input Current Output Current Symbol Conditions Units
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AC104Z
BASE-TX TRANSCEIVER CHARACTERISTICS
Parameter Peak Peak Differential Output Voltage Output Voltage Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot/Undershoot Output Jitter Receive Jitter Tolerance Output Current High Output Current High Common Mode Input Voltage Common Mode Input Current Differential Input Resistance
resistor each output.
Symbol Trfs
Conditions
1.02
Units
±250
Scrambled Idle
Transformer 1.25:1 Transformer
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BASE-T TRANSCEIVER CHARACTERISTICS
Parameter Peak Peak Differential Output Voltage Signal Rise/Fall Time Output Current Sink Output Current High Output Current High Start Idle Pulse Width Output Jitter Receive Jitter Tolerance Receive Input Impedance Differential Squelch Threshold Common Mode Rejection Differential Input Resistance
resistor each output.
Symbol
Conditions
Units
Transformer 1.25:1 Transformer
BASE-FX TRANSCEIVER CHARACTERISTICS
Parameter Differential Output Voltage High Differential Output Voltage Signal Rise/Fall Time Output Jitter Differential Output Voltage High Differential Output Voltage Common-Mode Input Voltage Input Differential Output Current Sink
3.3V ground.
Symbol
Conditions
Units
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AC104Z
BASE-T LINK INTEGRITY TIMING CHARACTERISTICS
Parameter Time Link Loss Receiver Link Pulse Link Receive Timer Link Receive Timer Link Transmit Period Link Pulse Width Symbol Conditions Units Link Pulses
DIGITAL TIMING CHARACTERISTICS
POWER RESET
Parameter RST* Period Configuration Symbol tRST tCONF Conditions Units
tRST RST* Configuration Pins
Figure Power Reset Timing.
tCONF
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MANAGEMENT DATA INTERFACE
Parameter Symbol Conditions Units
CLOCK CLOCK MDIO Setup MDIO Hold
tMDCL tMDCH Setup Read/Write Cycle Hold Read/Write Cycle
tMDCL
tMDCH
MDIO
Figure Management Data Interface Timing.
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AC104Z
100BASE-TX/FX 10BASE-T RMII TRANSMIT SYSTEM TIMING
Parameter Symbol Conditions Units
REFCLK period REFCLK High period REFCLK period TX_EN (SOP) TX_EN (EOP) Propagation Delay TXD[1:0], TX_EN Setup TXD[1:0], TX_EN Hold TX_EN TX_EN
tCKH tCKL tTXS tTXH tTX_TX From TXD[1:0] TXOP/ N(FXTP/N) From rising edge REFCLK From rising edge REFCLK
19.999 9.000 9.000
20.000 10.000 10.000
20.001 11.000 11.000
tCKH REFCLK tTXS TX_EN tTXH TXD[1:0]
Start Packet tCKL
Packet
tTX_TX
TXOP/N
FXTP/N
TXOP/N
Figure 100Base-TX/FX 10Base RMII Transmit Timing.
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100BASE-TX/FX 10BASE-T RMII RECEIVE SYSTEM TIMING
Parameter Symbol Conditions Units
REFCLK period REFCLK High period REFCLK period /J/K (SOP) CRS_DV /T/R (EOP) CRS_DV Propagation Delay RXD[1:0], CRS_DV, RX_ER Setup RXD[1:0], CRS_DV, RX_ER Hold
tCKH tCKL tRCSA tRCSD tRDVA tRXS tRXH From RXIP/N(FXRP/N) RXD[1:0] From rising edge REFCLK From rising edge REFCLK
19.999 9.000 9.000
20.000 10.000 10.000
20.001 11.000 11.000
tCKH REFCLK tRDVA CRS_DV tRXS RXD[1:0] RX_ER /J/K RXIP/N
Start Packet tCKL
Packet
tRDVD
tRXH
/T/R
FXRP/N RXIP/N
Figure 100Base-TX/FX 10Base-T RMII Receive Timing.
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AC104Z
100BASE-TX/FX 10BASE-T SMII TRANSMIT SYSTEM TIMING
Parameter Symbol Conditions Units
REFCLK period REFCLK High period REFCLK period SYNC rise REFCLK TX_EN (SOP) TX_EN (EOP) Propagation Delay Setup Hold SYNC SYNC
tCKH tCKL tTCS tTXS tTXH From TXOP/ N(FXTP/N) From rising edge REFCLK From rising edge REFCLK
7.999 3.999 3.999
8.000
8.001 4.001 4.001
tCKH REFCLK tTSC SYNC tTXS TXOP/N 100Base-TX tTXH
Start Packet tCKL
Packet
FXTP/N
TXOP/N 10Base-T
Figure SMII Transmit Timing.
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100BASE-TX/FX 10BASE-T SMII RECEIVE SYSTEM TIMING
Parameter Symbol Conditions Units
REFCLK period REFCLK High period REFCLK period SYNC rise REFCLK /J/K (SOP) CRS_DV /T/R (EOP) CRS_DV Propagation Delay Setup Hold
tCKH tCKL tTCS tRXS tRXH From RXIP/N(FXRP/N) From rising edge REFCLK From rising edge REFCLK
19.999 9.000 9.000
20.000 10.000 10.000
20.001 11.000 11.000
tCKH REFCLK tTSC SYNC tRXS /J/K RXIP/N
Start Packet tCKL
Packet
tRXH
/T/R
FXRP/N
RXIP/N
Figure SMII Receive Timing.
dcom
Page Section Electrical Characteristics Document AC104Z-DS01-R
Preliminary Data Sheet
03/20/02
AC104Z
RECOMMENDED TERMINATION
APPLICATION TERMINATION
Contact Altima Communications Inc. latest component value recommendations.
3.3V
49.9
49.9
AC104Z
Transformer TXON TXOP TXC_P TX+_P TX-_P RX+_P RX-_P RXC_P TXC_S TX+_S TX-_S RX+_S RX-_S RXC_S
RJ45 Unused Unused Unused Unused
IBREF
FX_EN
RXIP
49.9
1000
49.9
RXIN
Chassis
dcom
Document AC104Z-DS01-R Section Electrical Characteristics Page
AC104Z
Preliminary Data Sheet
03/20/02
APPLICATION TERMINATION
Contact Altima Communications Inc. latest component value recommendations.
3.3V 69.8 69.8
HFBR-5903 RXVee RXVcc TXVcc TXVee
AC104Z-QF
FXRN
FXRP FXTP
FXTN
FX_EN
Page
Section Electrical Characteristics
dcom
Document AC104Z-DS01-R
Preliminary Data Sheet
03/20/02
AC104Z
POWER GROUND FILTERING
Contact Altima Communications Inc. latest component vaue recommendations.
Ground Power .1uf
Components placed from
AC104ZKQM AC104Z-QF
dcom
Document AC104Z-DS01-R Section Electrical Characteristics Page
AC104Z
Preliminary Data Sheet
03/20/02
Section Packag Drawing
Table Mechanical Dimensions (Millimeters)
3.40
0.25
2.70
0.200 0.07
23.20 0.25
20.0 0.10
18.5 0.10
17.20 14.00 0.25 0.10
12.50 0.10
0.50
0.88
1.60 0.12
AC104ZKQM
Figure Package Drawing
dcom
Page Section Package Drawing Document AC104Z-DS01-R
Preliminary Data Sheet
03/20/02
AC104Z
PACKAGING THERMAL CHARACTERISTICS
Table Theta-JA Airflow AC104Z (128 PQFP) package
Airflow (feet minute)
Theta (C/W) Theta estiamted 19.5 C/W.
C/W.
38.7
36.8
33.7
dcom
Document AC104Z-DS01-R Section Package Drawing Page
AC104Z
Preliminary Data Sheet
03/20/02
ction Specifications
Table Thermal Parameters Airflow (feet minute)
Theta
38.7
36.8
35.0
33.7
Theta 19.5 junction temperature
dcom
Page Section Thermal Specifications Document AC104Z-DS01-R
Preliminary Data Sheet
03/20/02
AC104Z
Part Number Package Ambient Temperature
AC104ZKQM
PQFP
70°C
dcom
Document AC104Z-DS01-R Section Ordering Information Page
AC104Z
Preliminary Data Sheet
03/20/02
Altima Communications, Inc.
Wholly Owned Subsidiary Broadcom Corporation
16215 Alton Parkway P.O. 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
Broadcom Corporation reserves right make changes without further notice products data herein improve reliability, function, design. Information furnished Broadcom Corporation believed accurate reliable. However, Broadcom Corporation does assume liability arising application this information, application product circuit described herein, neither does convey license under patent rights rights others.
Document AC104Z-DS01-R

GENERAL DESCRIPTION AC104Z highly integrated, 3.3V, low-power, fourpor

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