Kingmax Memory Module MT3A83S 86KX MT3A83S-86KX (PC-100 128MB 144

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Kingmax Memory Module MT3A83S 86KX MT3A83S-86KX (PC-100 128MB 144

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Kingmax Memory Module MT3A83S 86KX
Kingmax Memory Module MT3A83S 86KX
MT3A83S-86KX (PC-100 128MB 144Pin Micro-DIMM Module) DESCRIPTION
MT3A83S-86KX Synchronous Dynamic high density memory module. MT3A83S-86KX consists eight CMOS with banks Synchronous DRAMs TinyBGA package EEPROM 8-Pin TSSOP package 144Pin glass-epoxy substrate. 0.1uF decoupling capacitor mounting printed circuit board parallel each SDRAM.
MT3A83S-86KX Small Outline Dual in-line Memory Module intended mounting into 144Pin edge connector sockets. Synchronous design allows precise cycle control with system clock.
transactions possible every clock cycle. Range operating frequencies programmable latencies allows same device useful variety high bandwidth high performance memory system application.
FEATURES
Performance range 100MHz Freq.( CL=3&2 Burst mode operation Auto self refresh capability (4096 Cycles 64ms LVTTL compatible inputs outputs Single 3.3V 0.3V power supply cycle with address programs Latency Access from column address Burst length Full page Data scramble Sequential Interleave inputs sampled positive going edge system clock Signal 3.3V 0.3V power supply Serial presence detect with EEPROM Height 1180 layer, double sided component
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Kingmax Memory Module MT3A83S 86KX
CONFIGURATIONS (Front side/back side)
Front DQM0 DQM1 DQ10 DQ11 DQ12 Front DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM4 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 Front DQ13 DQ14 DQ15 CLK0 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 Back DQ45 DQ46 DQ47 CKE0 CKE1 *A12 *A13 CLK1 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 Back DQ22 DQ23 A10/AP DQM2 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 **SDA Back DQ54 DQ55 DQM6 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 **SCL
NAMES
Name DQ63 CLK0 CKE0 DQM0 Function Address input (Multiplexed) Select bank Data input/output Clock input Clock enable input Chip select input address strobe Column address strobe Write enable Power supply (3.3V) Ground Serial data Serial clock connection
These pins used this module. These pins should system which does support SPD.
CONFIGURATION DESCRIPTION
Name System clock Chip select Input Function Active positive going edge sample inputs. Disables enables device operation masking enabling inputs except CLK, DQM. Masks system clock freeze operation from next clockycle. should enabled least cycle prior comman Disable input buffers power down standby. should enabled 1CLK+tSS prior valid command. Row/column addresses multiplexed same pins. address RA11, Column address Selects bank activated during address latch time. Selects bank read/write during column address latch time Latches addresses positive going edge CLKwith low. Enables access precharge. Latches column addresses positive going edge with low. Enables column access. Enables write operation precharge. Latches data starting from CAS, active. Makes data output Hi-Z, tSHZ after clock masks output. Blocks data input when active. (Byte masking) Data inputs/outputs multiplexed same pins. Power ground input buffers core logic.
Clock enable
DQM0 VDD/VSS
Address Bank select address address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
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Kingmax Memory Module
MT3A83S 86KX
FUNCTIONAL BLOCK DIAGRAM
DQM0 UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM LDQM UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM6 UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM LDQM UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM LDQM UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM LDQM UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQM1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
CKE0 CKE1
SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
Serial
47kW
0603 Capacitors each SDRAM SDRAMs Every SDRAM CLK0/1 U1/5 U2/6 U3/7 U4/8
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Kingmax Memory Module MT3A83S 86KX
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG Value -1.0 -1.0 +125 Unit
Note Permanent device damage occur "ABSOLUTE MAXIMUM RATINGS" exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
OPERATING CONDITIONS CHARACTERISTICS
Recommended operating conditions (Voltage referenced 70°C) Parameter Supply voltage Input high voltage Input voltage Output high voltage Output voltage Input leakage current (Inputs) Input leakage current (I/O pins) Symbol -0.5 VDDQ+0.3 Unit -2mA Note
Notes (max) 5.6V AC.The overshoot voltage duration 5ns. (min) -2.0V undershoot voltage duration 5ns. input VDDQ. Input leakage currents include Hi-Z output leakage bi-directional buffers with Tri-State outputs. Dout disabled, VOUT VDDQ.
CAPACITANCE
(VDD 3.3V, 23°C, 1MHz, VREF 1.4V Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT Unit
Parameter Input capacitance A11, BA1) Input capacitance (RAS, CAS, Input capacitance (CKE0,1 Input capacitance (CLK0,1 Input capacitance (CS0 Input capacitance (DQM0 DQM7) Data input/output capacitance (DQ0 DQ63)
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Kingmax Memory Module MT3A83S 86KX
CHARACTERISTICS
(Recommended operating condition unless otherwise noted, 70°C)
PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN); latency 10ns
SYMBOL IDD1
UNITS
STANDBY CURRENT: Power-Down Mode; 10ns; LOW; banks idle
IDD2 IDD3
STANDBY CURRENT: Active Mode; S0#, HIGH; 10ns; HIGH; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; 10ns; banks active; latency AUTO REFRESH CURRENT: HIGH; S0#, HIGH; 10ns
(MIN);
IDD4 IDD5 IDD6 IDD7
15.625µs; SELF REFRESH CURRENT: 0.2V
Notes Measured with outputs open. Refresh period 64ms.
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Kingmax Memory Module MT3A83S 86KX
OPERATING TEST CONDITIONS
Parameter input levels (Vih/Vil) Input timing measurement reference level Input rise fall time Output timing measurement reference level Output load condition (VDD 3.3V 0.3V, 70°C) Value 2.4/0.4 tr/tf Fig. Unit
3.3V
1.4V
1200 Output 50pF (DC) 2.4V, -2mA (DC) 0.4V, Output
50pF
(Fig. output load circuit
(Fig. output load circuit
OPERATING PARAMETER
Parameter active active delay delay precharge time active time cycle time Last data precharge Last data col. address delay Last data burst stop Col. address col. address delay Number valid output data
operating conditions unless otherwise noted) Symbol tRRD (min) tRCD (min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tCDL(min) tBDL(min) tCCD (min) latency=3 latency=2 Version Unit Note
Notes minimum number clock cycles determined dividing minimum time required with clock cycle time, then rounding next higher integer. Minimum delay required complete write. parts allow every cycle column address change. case precharge interrupt, auto precharge burst stop.
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Kingmax Memory Module MT3A83S 86KX
CHARACTERISTICS operating conditions unless otherwise noted) REFER INDIVIDUAL COMPONENT, WHOLE MODULE.
Parameter latency=3 latency=2 valid output delay latency=3 latency=2 Output data hold time high pulse width pulse width Input setup time Input hold time output Low-Z output Hi-Z latency=3 latency=2 Notes Parameters depend programmed latency. clock rising time longer than 1ns, (tr/2-0.5)ns added parameter. Assumed input rise fall time 1ns. longer than 1ns, transient time compensat should considered, i.e., [(tr tf)/2-1]ns should added parameter latency=3 latency=2 tSLZ tSHZ tSAC Symbol cycle time 100Mhz 1000 Unit Note
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Kingmax Memory Module MT3A83S 86KX
Address
BURST DEFINITION
Mode Register (Mx) Reserved* Mode Latency Burst Length
Burst Length
Starting Column Order Accesses Within Burst Address: Type Sequential Type Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
*Should program M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn+1, Cn+2 Full A0-A9 Cn+3, Cn+4. Page (location 0-1,023) .Cn-1, (1,024) NOTE:
supported
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
MODE REGISTER DEFINITION
burst length two, A1-A9 select block burst; selects starting column within block. burst length four, A2-A9 select block four burst; A0-A1 select starting column within block. burst length eight, A3-A9 select block eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-A9 select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-A9 select unique column accessed, Mode Register ignored.
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Kingmax Memory Module MT3A83S 86KX
SIMPLIFIED TRUTH TABLE
Command Register Mode register Auto refresh Refresh Entry Self refresh Exit
CKEn-1 CKEn BA0,1 A10/AP A11, Note
code
address
Column address Column address
Bank active addr. Read column address Write column address Burst stop Precharge Bank selection banks Clock suspend active power down Entry Exit Entry Precharge power down mode Exit operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
(V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes Code Operand code Program keys. MRS) issued only banks precharge state. command issued after clock cycles MRS. Auto refresh functions same refresh DRAM automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precha state. Bank select addresses. both "Low" read, write, active precharge, bank selected. both "Low" "High" read, write, active precharge, bank selected. both "High" "Low" read, write, active precharge, bank selected. both "High" read, write, active precharge, bank selected. A10/AP "High" precharge, ignored banks selected. During burst read write with auto precharge, read/ write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled positive going edge masks data-in very (Write latency makes Hi-Z state data-out cycles after. (Read latency
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Kingmax Memory Modul MT3A83S-86KX
PACKAGE DIMENSIONS
Units: Millimeter
used device 8Mx16 SDRAM, TinyBGA
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Kingmax Memory Module MT3A83S 86KX MT3A83S-86KX (PC-100 128MB 144

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