MPJA83S -68KX3( PC-150 128MB 168-Pin DIMM SDRAM Module DESCRIPTION

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MPJA83S -68KX3( PC-150 128MB 168-Pin DIMM SDRAM Module DESCRIPTION

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Kingmax Memory Module MPJA83S 68KX3
MPJA83S -68KX3( PC-150 128MB 168-Pin DIMM SDRAM Module DESCRIPTION
MPJA83S-68KX3 Synchronous Dynamic high density memory module.The MPJA83S-68KX3 consists eight CMOS with 4banks Synchronous DRAMs Tiny-BGA package EEPROM 8-Pin 168-Pin glass-epoxy substrate.0.1uFand 0.33uF decoupling capacitors mounted printed circuit board parallel each SDRAM.
MPJA83S-68KX3 Dual in-line Memory Module intended mounting into 168-Pin edge connector sockets. Synchronous design allows precise cycle control with system clock.
transactions possible every clock cycle. Range operating frequencies programmable latencies allows same device useful variety high bandwidth high performance memory system application.
FEATURES
Performance range 150MHz (Max Freq. CL=3 Burst mode operation Auto self refresh capability (4096 Cycles 64ms LVTTL compatible inputs outputs Single 3.3V 0.3V power supply cycle with address programs Latency Access from column address Burst length Full page Data scramble Sequential Interleave inputs sampled positive going edge system clock Serial presence detect with EEPROM Height 1,000 single sided component
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Kingmax Memory Module MPJA83S 68KX3
CONFIGURATIONS (Front side/back side)
Front DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 *CB0 *CB1 DQM0 Front Front Back DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 *CB4 *CB5 DQM4 Back DQM5 CLK1 *A12 CKE0 DQM6 DQM7 *A13 *CB6 *CB7 DQ48 DQ49 Back DQ50 DQ51 DQ52 *VREF DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CLK3 **SA0 **SA1 **SA2 DQM1 A10/AP CLK0 DQM2 DQM3 *CB2 *CB3 DQ16 DQ17 DQ18 DQ19 DQ20 *CKE1 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CLK2 **SDA **SCL
NAMES
Name DQ63 CLK0 ,CLK2 CKE0 DQM0 Function Address input (Multiplexed) Select bank Data input/output Clock input Clock enable input Chip select input address strobe Column address strobe Write enable Power supply (3.3V) Ground Power supply reference Serial data Serial clock Address EEPROM Write protection connection
These pins used this module. These pins should system which does support SPD.
CONFIGURATION DESCRIPTION
Name System clock Chip select Input Function Active positive going edge sample inputs. Disables enables device operation masking enabling inputs except CLK, DQM. Masks system clock freeze operation from next clock cycle. should enabled least cycle prior command. Disable input buffers power down standby. should enabled 1CLK+t prior valid command. Row/column addresses multiplexed same pins. address RA11, Column address Selects bank activated during address latch time. Selects bank read/write during column address latch time. Latches addresses positive going edge with Enables access precharge. low. low.
Clock enable
DQM0 /VSS
Address Bank select address address strobe Column address strobe Write enable Data input/output mask Data input/output Write protection Power supply/ground
Latches column addresses positive going edge with Enables column access. Enables write operation precharge. Latches data starting from CAS, active. Makes data output Hi-Z, after clock masks output. Blocks data input when active. (Byte masking) Data inputs/outputs multiplexed same pins.
connected through Resistor. When "high", EEPROM Programming will inhibited entire memory will write-protected. Power ground input buffers core logic.
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Kingmax Memory Module MPJA83S 68KX3
FUNCTIONAL BLOCK DIAGRAM
DQM0 DQM1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A11, CKE0 0.1uF Capacitors each SDRAM SDRAMs Every DQpin SDRAM CLK0/2 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5
DQM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7
SDRAM SDRAM SDRAM SDRAM SDRAM
Serial 47KW
U1/U3 U2/U4 U5/U7 U6/U8
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Kingmax Memory Module MPJA83S 68KX3
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Storage temperature Power dissipation Short circuit current Symbol VIN, TSTG Value -1.0 -1.0 +125 Unit
Note Permanent device damage occur "ABSOLUTE MAXIMUM RATINGS" exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
OPERATING CONDITIONS CHARACTERISTICS
Recommended operating conditions (Voltage referenced Parameter Supply voltage Input logic high voltage Input logic voltage Output logic high voltage Output logic voltage Input leakage current (Inputs) Input leakage current (I/O pins) Symbol VDDQ
VDDQ +0.3 Unit -2mA Note
-0.3
Note (max) 5.6V overshoot voltage duration 3ns. (min) -2.0V undershoot voltage duration 3ns. input DDQ. Input leakage currents include Hi-Z output leakage bi-directional buffers with Tri-State outputs. Dout disabled, DDQ.
CAPACITANCE
3.3V, 23°C, 1MHz, 1.4V
Address A11, BA1) RAS, CAS, (CKE0 CKE1) Clock (CLK0 CLK3) (CS0, CS2) (DQM0 DQM7) (DQ0 DQ63)
Symbol CCKE COUT
Unit
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Kingmax Memory Module MPJA83S 68KX3
CHARACTERISTICS
(Recommended operating condition unless otherwise noted, Parameter Symbol
Version 128MB Unit Note
Test Condition Active Mode Burst Read Write; tRC=tRC(NIN) Latency=3 Power Down Mode
Operating Current (One bank active)
Icc1
1850
Standby Current
Icc2
CKE=Low; Bank idle Active Mode; -CS0,-CS2=High CKE=High; banks active after tRCD accesses progress Burst Mode;Continuous burst Read Write; banks active Latency=3 =High; -CS0,-CS2=High tRC=tRC(MIN); CL=3 CKE=High; -CS0,-CS2=High tRC=15.625us;CL=3 0.2V
Standby Current
Icc3
Operating Current
Icc4
1560
Auto Refersh Current
Icc5 Icc6
2450
Self Refresh Current
Icc7
Notes dependent output loading cycle rates.Specified values obtained with minimum cycle time outputs open. current will decrease latency reduce.This fact that maximum cycle rates slower latency reduceed. Address transitions average transition every clocks. Other input signals allowed transition more than clocks otherwise vaild levels.
high during refresh command period else .The Icc6 limit actually nominal value does result fail value. Enable on-chip refersh address counters.
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Kingmax Memory Module MPJA83S 68KX3
OPERATING TEST CONDITIONS
Parameter input levels (Vih/Vil) Input timing measurement reference level Input rise fall time Output timing measurement reference level Output load condition
3.3V
3.3V 0.3V, Value 2.4/0.4 tr/tf Fig.
1.4V
Unit
1200W Output 870W 50pF (DC) 2.4V, -2mA (DC) 0.4V, Output
50pF
(Fig. output load circuit
(Fig. output load circuit
OPERATING PARAMETER
operating conditions unless otherwise noted) Parameter active active delay delay precharge time active time cycle time Last data precharge Last data col. address delay Last data burst stop Col. address col. address delay Number valid output data Symbol tRRD (min) tRCD (min) (min) tRAS (min) tRAS (max) (min) tRDL (min) tCDL (min) tBDL (min) tCCD (min) latency=3 latency=2 Version Unit Note
Notes minimum number clock cycles determined dividing minimum time required with clock cycle time then rounding next higher integer. Minimum delay required complete write. parts allow every cycle column address change. case precharge interrupt, auto precharge read burst stop.
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Kingmax Memory Module MPJA83S 68KX3
CHARACTERISTICS operating conditions unless otherwise noted) REFER INDIVIDUAL COMPONENET, WHOLE MODULE.
Parameter latency=3 latency=2 valid output delay latency=3 latency=2 tOHN tSLZ latency=3 latency=2 tSHZ tSAC Symbol cycle time Unit Note
Data output hold time(load) Data output hold time(no load) high pulse width pulse width Input setup time Input hold time output Low-Z output Hi-Z
Notes Parameters depend programmed latency. clock rising time longer than 1ns, (tr/2-0.5)ns should added parameter. Assumed input rise fall time 0.8ns. longer than 1ns, transient time compensation should considered, i.e., [(tr tf)/2-1]ns should added parameter.
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Kingmax Memory Module MPJA83S 68KX3
SIMPLIFIED TRUTH TABLE
Command Register Mode register Auto refresh Refresh Entry Self refresh Exit
CKEn-1 CKEn Note
code
address
Column address Column address
Bank active addr. Read column address Write column address Burst stop Precharge Bank selection banks Clock suspend active power down Entry Exit Entry Precharge power down mode Exit operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
(V=Valid, X=Don care, H=Logic high, L=Logic low) Notes Code Operand code Program keys. MRS) issued only banks precharge state. command issued after clock cycles MRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precharge state. Bank select addresses. both "Low" read, write, active precharge, bank selected. both "Low" "High" read, write, active precharge, bank selected. both "High" "Low" read, write, active precharge, bank selected. both "High" read, write, active precharge, bank selected. "High" precharge, ignored banks selected. During burst read write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled positive going edge masks data-in very (Write latency makes Hi-Z state data-out cycles after. (Read latency
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Kingmax Memory Module MPJA83S 68KX3
PACKAGE DIMENSIONS
Units Inches (Millimeters)
5.250 (133.350) 0.118 5.014 (127.350)
0.089 (2.26) 0.079 2.000) 0.157 0.004 (4.000 0.100
1.000 (25.40)
0.118 (3.000)
.118DIA 0.004 (3.000DIA 0.100) 0.350 (8.890)
0.250 (6.350) .450 (11.430) 1.450 (36.830)
0.250 (6.350)
2.150 (54.61) 4.550 (115.57)
0.100 (2.540 Min)
0.700 (17.780)
0.100Max (2.54Max) (5.08 Min) 0.200
0.050 0.0039 (1.270 0.10)
0.250 (6.350
0.250 (6.350
(2.540 Min)
0.100
0.039 .002 (1.000 .050)
0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100)
0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100)
0.010Max (0.250 Max) 0.050 (1.270
Detail
Detail
Detail
Tolerances .005(.13) unless otherwise specified used device 16Mx8 SDRAM, Tiny-BGA
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MPJA83S -68KX3( PC-150 128MB 168-Pin DIMM SDRAM Module DESCRIPTION

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