MPDA82D-68KX3 16Mx64 SDRAM 184pin DIMM based 16Mx8 Performance ra

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MPDA82D-68KX3 16Mx64 SDRAM 184pin DIMM based 16Mx8 Performance ra

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Kingmax Memory Module MPDA82D 68KX3
MPDA82D-68KX3 16Mx64 SDRAM 184pin DIMM based 16Mx8
Performance range Part MPDA82D-68KX3 Freq. 133MHz(7.5ns@CL=2.5) Interface SSTL_2
GENERAL DESCRIPTION
KINGMAX MPDA82D-68KX3 Double Data Rate SDRAM high density memory modules based first 128Mb SDRAM respectively.
KINGMAX MPDA82D-68KX3 consists eight CMOS Power supply Vdd: 2.5V 0.2V with 4banks Double Data Rate SDRAMs 54pin cycle with address programs packages mounted 184pin glass-epoxy subCAS Latency (Access from column address):2.5 strate. 0.1uF decoupling capacitors mounted Burst length printed circuit board parallel each SDRAM. Data scramble ;Sequential Interleave MPDA82D-68KX3 Dual In-line Memory Modules inten-ded Serial presence detect with EEPROM mounting into 184pin edge connector sockets. Height 1000 (mil), double sided component Synchronous design allows precise cycle control with system clock. Data transactions possible both edges DQS. Range operating frequencies, programmable latencies burst lengths allow same device useful variety high bandwidth, high performance memory system applications.
CONFIGURATIONS (Front side/back side)
Front Front VREF DQS0 DQS1 VDDQ /CK1 DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 DQ18 VDDQ DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 *CB0 *CB1 *DQS8 *CB2 *CB3 DQ32 VDDQ DQ33 DQS4 DQ34 DQ35 DQ40 Front VDDQ DQ41 /CAS DQS5 DQ42 DQ43 DQ48 DQ49 /CK2 VDDQ DQS6 DQ50 DQ51 VDDID DQ56 DQ57 DQS7 DQ58 DQ59 Back VDDQ *A13 VDDQ DQ12 DQ13 DQ14 DQ15 *CKE1 VDDQ *BA2 DQ20 *A12 DQ21 DQ22 DQ23 Back DQ28 DQ29 VDDQ DQ30 DQ31 *CB4 *CB5 VDDQ /CK0 *DM8 *CB6 VDDQ *CB7 DQ36 DQ37 DQ38 DQ39 DQ44 Back /RAS DQ45 VDDQ /CS0 */CS1 DQ46 DQ47 VDDQ DQ52 DQ53 DQ54 DQ55 VDDQ DQ60 DQ61 DQ62 DQ63 VDDQ VDDSPD
DESCRIPTION
Name DQ63 DQS0 DQS7 CKE0 VDDQ VREF VDDSPD VDDID Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock enable input Chip select input address strobe Column address strobe Write enable Data mask Power supply (2.5V) Power Supply DQs(2.5V) Ground Power supply reference Serial EEPROM Power Supply (2.5V) Serial data Serial clock Address EEPROM identification flag
CK0,CK0 CK2,CK2 Clock input
connection These pins used this module.
Preliminary
June 2001 Rev:1.0
Kingmax Memory Module MPDA82D 68KX3
Functional Block Diagram
DQS0
DQS4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS1
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS5
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
Clock Wiring Clock Input CK0/CK0 CK1/CK1 CK2/CK2
SDRAMs SDRAMs SDRAMs SDRAMs
DQS3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
*Clock Wiring Dram1 R=120 Dram3 *(Cap) Dram5
Serial CKE0 /VDDQ BA0-BA1: SDRAMs A0-A13: SDRAMs RAS: SDRAMs CAS: SDRAMs CKE: SDRAMs SDRAMs VREF VDDID DRAMs loaded, will replace DRAM3 Card Edge
0.1uF 0.1uF
Strap: Note
Notes: DQ-to-I/O wiring shown recommended changed. DQ/DQS/DM/CKE/CS relationships must maintained shown. DQS, DM/DQS resistors: Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP (OPEN): VDDQ STRAP (VSS): VDDQ.
Preliminary
June 2001 Rev:1.0
Kingmax Memory Module MPDA82D 68KX3
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Voltage VDDQ supply relative Storage temperature Power dissipation Short circuit current Symbol VIN, VDDQ TSTG Value -0.5 -1.0 -0.5 +125 Unit
Note Permanent device damage occur ABSOLUTE MAXIMUM RATING exceeded. Functional operation should restricted recommended condition. rating Exposure higher than recommended voltage extended perof time could affect device reliability. iods
POWER OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced VSS=0V, TA=0 70°C)
Parameter
Supply voltage(for device with nominal 2.5V) Supply voltage Reference voltage Termination voltage(system) Input logic high voltage Input logic voltage Input Voltage Level, inputs Input Differential Voltage, inputs Input leakage current Output leakage current Output High Current (VOUT 1.95V) Output Current (VOUT 0.35V)
Symbol
VDDQ (DC) IL(DC) (DC) (DC)
0.49*VDDQ VREF-0.04 REF+0.15 -0.3 -0.3 -16.8 16.8
0.51*VDDQ VREF +0.04 DDQ+0.3 REF-0.15 DDQ+0.3 DDQ+0.6
Unit
Note
Notes VREF expected equal 0.5*V transmitting device, track variations inDC level same. Peakthe to-peak noise VREF exceed value applied directly device. system supply signal termination resistors, equal ected VREF, must track variations level VREF magnitude difference between input level input level
Preliminary
June 2001 Rev:1.0
Kingmax Memory Module MPDA82D 68KX3
SDRAM SPEC Items Test Conditions
Recommended operating conditions Unless Otherwise Noted, TA=0 70°C
Conditions Operating current bank Active-Precharge; tRC=tRCmin; 133Mhz DDR266 DQ,DM inputs changing twice clock cycle; address control inputs changing once clock cycle Operating current bank operation bank open, BL=4, Reads Refer following page detailed test condition Percharge power-down standby current; banks idle; power down mode; <VIL(max); 133Mhz DDR266 Vref DQ,DQS Precharge Floating standby current; =VIH(min);All banks idle; VIH(min); 133Mhz DDR266 Address other control inputs changing once clock cycle; Vref DQ,DQS Precharge Quiet standby current; VIH(min); banks idle; VIH(min); 133Mhz DDR266 Address other control inputs stable with keeping VIH(min) =<VIL(max); Vref ,DQS Active power down standby current bank active; power-down mode; CKE=< (max); 133Mhz DDR266 Vref DQ,DQS Active standby current; VIH(min); CKE>=VIH(min); bank active; active precharge; tRC=tRASmax; 133Mhz DDR266 inputs changing twice clock cycle; address other control inputs changing once clock cycle Operating current burst read; Burst length reads; continguous burst; bank active; address control inputs changing once clock cycle; CL=2.5 133Mhz DDR266 data changing every burst; lout Operating current burst write; Burst length writes; continuous burst; bank active address control inputs changing once clock cycle; CL=2.5 133Mhz DDR266B inputs changing twice clock cycle, input data changing every burst Auto refresh current; tRFC(min) 10*tCK DDR266 133Mhz; distributed refresh Self refresh current; 0.2V; External clock should 133Mhz DDR266 Orerating current Four bank operation Four bank interleaving with BL=4 -Refer following page detailed test condition Typical case: 2.5V, Worst case 2.7V, Symbol IDD0 Typical Worst
IDD1 IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Preliminary
June 2001 Rev:1.0
Kingmax Memory Module MPDA82D 68KX3
SDRAM spec table
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 (DDR266@CL=2.5) typical 1120 1200 1080 1560 2080 worst 1200 1320 1200 1640 2240 typical worst typical worst Unit Notes
Module
calculated basis component
differently measured according loading cap.
Detailed test conditions SDRAM IDD1 IDD7
IDD1 Operating current: bank operation Typical Case 2.5V, T=25' Worst Case 2.7V, Only bank accessed with tRC(min), Burst Mode, Address Control inputs edge changing once clock cycle. lout Timing patterns DDR266(133Mhz, CL=2.5) 7.5ns, CL=2.5, BL=4, tRCD 3*tCK, 9*tCK, tRAS 5*tCK Read repeat same timing with random address changing *50% data changing every burst Legend A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Preliminary
June 2001 Rev:1.0
Kingmax Memory Module MPDA82D 68KX3
IDD7 Operating current: Four bank operation Typical Case 2.5V, T=25' Worst Case 2.7V, Four banks being interleaved with tRC(min), Burst Mode, Address Control inputs edge changing. lout Timing patterns DDR266(133Mhz, CL=2.5) 7.5ns, CL=2.5, BL=4, tRRD 2*tCK, tRCD 3*tCK Read with autoprecharge Read repeat same timing with random address changing *50% data changing every burst Legend A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Operating Conditions
Parameter/Condition Input High (Logic Voltage, signals Input (Logic Voltage, signals. Input Differential Voltage, inputs Input Crossing Point Voltage, inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.62 0.5*VDDQ-0.2 VREF 0.31 VREF 0.31 VDDQ+0.6 0.5*VDDQ+0.2 Unit Note
Note Vih(max) 4.2V. overshoot voltage duration VDD. Vil(min) -1.5V. undershoot voltage duration VSS. magnitude difference between input level input value expected equal 0.5*VDDQ transmitting device must track variations level same.
Preliminary
June 2001 Rev:1.0
Kingmax Memory Module MPDA82D 68KX3
OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, 70°C)
Parameter Input reference voltage Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value VREF+0.31/VREF-0.31 VREF Load Circuit Unit V/ns Note
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*V
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, 25°C, f=1MHz)
Parameter Input capacitance(A0 A11, BA1,RAS,CAS, Input capacitance(CKE0) Input capacitance( CS0) Input capacitance( CLK0, CLK1,CLK2 Data input/output capacitance(DQ0~DQ63) Input capacitance(DM0~DM8) Symbol CIN1 CIN2 CIN3 CIN4 COUT CIN5 Unit
Preliminary
June 2001 Rev:1.0
Kingmax Memory Module MPDA82D 68KX3
Timming Parameters Specifications (These charicteristics were tested Component)
Parameter cycle time Refresh cycle time active time delay precharge time active active delay Write recovery time Last data Read command Col. address Col. address delay Clock cycle time CL=2.0 CL=2.5 Clock high level width Clock level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge ouput data edge Read Preamble Read Postamble Data high impedence time from CK/CK valid DQS-in DQS-in setup time DQS-in hold time DQS-in high level width DQS-in level width DQS-in cycle time Address Control Input setup time Address Control Input hold time Mode register cycle time setup time hold time input pulse width Power down exit time Exit self refresh write command tDQSCK tDQSQ tRPRE tRPST tHZQ tDQSS tWPRES tWPREH tDQSH tDQSL tDSC tMRD tDIPW tPDEX tXSW Symbol tRFC tRAS tRCD tRRD tCDLR tCCD (DDR266) 0.45 0.45 -0.75 -0.75 -0.75 0.75 0.25 1.75 0.55 0.55 +0.75 +0.75 +0.5 +0.75 1.25 120K Unit Note
Preliminary
June 2001 Rev:1.0
Kingmax Memory Module MPDA82D 68KX3
(PC266@CL=2.5) 15.6 tHPmin -0.75ns tCLmin tCHmin 0.25
Parameter Exit self refresh bank active command Exit self refresh read command Refresh interval time 128Mb
Symbol tXSA tXSR tREF
Unit Cycle
Note
Output valid window
Clock half period write postamble time setup first edge reads hold after last edge reads Write command delay write Write burst delay write Write burst delay write interrupted Precharge
tWPST tQCS tQCH tQCSW tQCHW tQCHWI
1.25ns
0.5tCK 1.5tCK
Note Maximum burst refresh tHZQ transitions occurs same access time windows valid data transitions. These parameters referenced specific voltage level, specify when device output longer driving. specific requirement that valid(High Low) before this edge. case shown(DQS going from High_Z logic Low) applies when writes were previously progress bus. previous write progress, could High this time, depending tDQSS. maximum limit this parameter device limit. device will operate with great value this parameter, system performance (bus turnaround) will degrade accordingly. value tQCSW min. 1.25ns from last going data strobe edge high. value tQCSW max. 0.5tcK from first high going clock edge after last going data strobe edge high. value tQCSWI max. 1.5tcK from first high going clock edge after last going data strobe edge high. write command applied with tRCD satisfied after this command.
Preliminary
June 2001 Rev:1.0
Kingmax Memory Module MPDA82D 68KX3
Command Truth Table
COMMAND Register Register Extended Mode Register Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
CKEn BA0,1 A10/AP Note
CODE CODE
Address
Column Address ~A9) Column Address ~A9)
Bank Active Addr. Read Column Address Write Column Address Burst Stop Precharge Bank Selection Banks Entry Exit Entry Precharge Power Down Mode Exit operation (NOP) defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
Active Power Down
Note Code Operand Code. Program keys. (@EMRS/MRS) 2.EMRS/ issued only banks precharge state. command issued clock cycles after EMRS MRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precharge state. Bank select addresses. both "Low" read, write, active precharge, bank selected. both "High" "Low" read, write, active precharge, bank selected. both "Low" "High" read, write, active precharge, bank selected. both "High" read, write, active precharge, bank selected. A10/AP "High" precharge, ignored banks selected. During burst write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled rising falling edges Data-in masked both edges (Write latency This combination defined function, which means Operation(NOP)" SDRAM.
Preliminary
June 2001 Rev:1.0
Kingmax Memory Module MPDA82D 68KX3
PACKAGE DIMENSIONS
Units Inches (Millimeters)
5.25 0.006 (133.350 0.15 5.077 (128.950)
0.089 (2.26)
(2X) 0.157
(4.00)
(10.00)
2.55
1.95
0.100 (2.30 Min)
0.393
(64.77)
(49.53)
0.10 (2.54 Max)
0.050 0.0039 (1.270 0.10)
(2.50
0.26 (6.62)
0.100
0.250 (6.350)
0.157 (4.00)
0.039 0.002 (1.000 0.050) 0.0787 (2.00) 0.0078 ±0.006 (0.20 ±0.15) 0.050 (1.270) 0.1575 (4.00)
0.118 (3.00)
0.1496 (3.80)
2.175 Detail
0.071 (1.80)
Detail
Tolerances 0.005(.13) unless otherwise specified. used device 16Mx8 SDRAM, TinyBGA
Preliminary
2001 Rev:1.0
(17.80)
1.18 0.006 (30.00 0.15)

MPDA82D-68KX3 16Mx64 SDRAM 184pin DIMM based 16Mx8 Performance ra

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