GMM7322100CMS/SG-6/7/8 2,097,152 WORDS CMOS DYNAMIC MODULE
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GMM7322100CMS/SG bits Dynamic MODULE which assembled pieces 8bit DRAMs package single sides printed circuit board with decoupling capacitors. GMM7322100CMS/SG optimized application systems which required high density large capacity such main memory computers image memory systems, others which requested compact size. GMM7322100CMS/SG provides common data inputs outputs. GMM7322100CMS/SG (Single Side)
GMM7322100CMS/SG-6/7/8
2,097,152 WORDS
CMOS DYNAMIC MODULE
Features
pins Single In-Line Package GMM7322100CMS Solder plating GMM7322100CMSG Gold plating Fast Page Mode Capability Single Power Supply Fast Access Time Cycle Time (Unit:
tRAC tCAC
GMM7322100CMS/SG-6 GMM7322100CMS/SG-7 GMM7322100CMS/SG-8
Power Active 2,640/2,420/2,200 (MAX) Standby 22mW (CMOS level MAX) Only Refresh, before Refresh, Hidden Refresh Capability inputs outputs Compatible 2048 Refresh Cycles/ 32ms
Configuration (Top View)
Symbol Symbol Symbol Symbol
DQ16 DQ17 DQ18 DQ19
DQ20 DQ21 DQ22 DQ23 RAS2
CAS0 CAS2 CAS3 CAS1 RAS0 DQ24 DQ25 DQ10 DQ26
DQ11 DQ27 DQ12 DQ28 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15
Semicon
GMM7322100CMS/SG
Block Diagram
RAS0
CAS0
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
RAS2
CAS2
-A10
-A10
CAS1
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
CAS3
-A10
-A10
C0-C3
M0-M3 M0-M3
*M0-M3 DRAM *C0-C3 0.22uF Capacitor
Semicon
GMM7322100CMS/SG
A0-A10 DQ0-DQ31 RAS0, RAS2 CAS0-CAS3
Function
Address Inputs Data Input/Output Address Strobe Column Address Strobe Read/Write Enable
PD1-PD4
Function
Presence Detect Power (+5V) Ground Connection
Presence Detect Pins (Optional)
60ns
70ns
80ns
Absolute Maximum Ratings*
Symbol
TSTG VIN/VOUT IOUT
Parameter
Ambient Temperature under Bias Storage Temperature (Plastic) Voltage Relative Power Supply Voltage Short Circuit Output Current Power Dissipation
Rating
-1.0 -1.0
Unit
*Note: Stress greater than above "Absolute Maximum Ratings" cause permanent damage device.
Recommended Operating Conditions 70C)
Symbol
Parameter
Supply Voltage Input High Voltage Input Voltage
-1.0
Unit
Note
*Note: voltages referenced VSS.
Semicon
GMM7322100CMS/SG
Electrical Characteristics (VCC 5V+/-10%, 70C)
Symbol
ICC1
Parameter
Output Level Output Level Voltage (IOUT -5mA) Output Level Output Level Voltage (IOUT 4.2mA) Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: min) 60ns 70ns 80ns
60ns 70ns 80ns 60ns 70ns 80ns 60ns 70ns 80ns
Unit
Note
ICC2
Standby Current (TTL) Power Supply Standby Current (RAS, VIH) Only Refresh Current Average Power Supply Current Only Mode (RAS Cycling, VIH, min) Fast Page Mode Current Average Power Supply Current Fast Page Mode (RAS VIL, CAS, Address Cycling: min) Standby Current (CMOS) Power Supply Standby Current (RAS, CAS>=VCC-0.2V) before Refresh Current (tRC min)
ICC3
ICC4
ICC5
ICC6
ICC7
Standby Current DOUT Enable Input Leakage Current Input (0V<=VIN<=6V) Other Pins Under Test Output Leakage Current (DOUT Disabled, 0V<=VOUT<=6V)
II(L)
IO(L)
Note: depends output load condition when device selected. ICC(max) specified output open condition. Address changed once less while VIL. Address changed once less while VIH.
Semicon
GMM7322100CMS/SG
Capacitance (VCC 5V+/-10%, 25C, 1MHz)
Symbol
CI/O
Parameter
Input Capacitance (A0~A10) Input Capacitance (WE) Input Capacitance (RAS0,RAS2) Input Capacitance (CAS0~CAS3) Capacitance (DQ0~DQ31)
Unit
Note
Note: Capacitance measured with Boonton Meter effective capacitance measuring method. disable DOUT.
Electrical Characteristics (VCC 5V+/-10%, 70C, Notes
GMM7322100CMS/SG writes data only early write cycle (twcs>=twcs(min)). Delayed write cycle available because common.
Read, Write Refresh Cycle (Common Parameters)
Symbol Parameter
Random Read Write Cycle Time Precharge Time Pulse Width Pulse Width Address Setup Time Address Hold Time Column Address Setup Time Column Address Hold Time Delay Time Column Address Delay Time Hold Time Hold Time Precharge Time Transition Time (Rise Fall) Refresh Period 1024 Cycles
GMM7322100 CMS/SG-6 GMM7322100 CMS/SG-7 GMM7322100 CMS/SG-8
Unit
Note
tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tREF
10,000 10,000
10,000 10,000
10,000 10,000
Semicon
GMM7322100CMS/SG
Read Cycle
Symbol Parameter
Access Time from Access Time from Access Time from Column Address Read Command Setup Time Read Command Hold Time Read Command Hold Time Column Address Lead Time Output Buffer Turn-off Time Output low-Z Column Address Lead Time Output Data Hold Time
GMM7322100 CMS/SG-6 GMM7322100 CMS/SG-7 GMM7322100 CMS/SG-8
Unit
Note
tRAC tCAC tRCS tRCH tRRH tRAL tOFF tCLZ tCAL
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command Lead Time Write Command Lead Time Data-in Setup Time Data-in Hold Time
GMM7322100 CMS/SG-6 GMM7322100 CMS/SG-7 GMM7322100 CMS/SG-8
Unit
Note
tWCS tWCH
tRWL tCWL
Semicon
GMM7322100CMS/SG
Refresh Cycle
Symbol Parameter
Setup Time (CAS-before-RAS Refresh Cycle) Hold Time (CAS-before-RAS Refresh Cycle) Precharge Hold Time Set-up Time (CAS-before-RAS Refresh Cycle) Hold Time (CAS-before-RAS Refresh Cycle)
GMM7322100 CMS/SG-6 GMM7322100 CMS/SG-7 GMM7322100 CMS/SG-8
Unit
Note
tCSR tCHR tRPC tWRP tWRH
Fast Page Mode Cycle
Symbol Parameter
Fast Page Mode Cycle Time Fast Page Mode Precharge Time Fast Page Mode Pulse Width Access Time from Precharge Hold Time from Precharge
GMM7322100 CMS/SG-6 GMM7322100 CMS/SG-7 GMM7322100 CMS/SG-8
Unit
Note
100,000
100,000
100,000
tRASP tACP tRHCP
Semicon
Notes: measurements assume 5ns.
GMM7322100CMS/SG
Assumes that tRCD<=tRCD(max) tRAD<=tRAD(max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent 2TTL loads 100pF. Assumes that tRCD>=tRCD(max) tRAD<=tRAD(max). Assumes that tRCD<=tRCD(max) tRAD>=tRAD(max). Either tRCH tRRH must satisfied read cycles. tOFF(max) defines time which outputs achieve open circuit condition referenced output voltage levels. VIH(min) VIL(max) reference levels measuring timing input signals. Also, transition times measured between VIL. Operation with tRCD(max) limit insures that tRAC(max) met, tRCD(max) specified reference point only, tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC. Operation with tRAD(max) limit insures that tRAC(max) met, tRAD(max) specified reference point only, tRAD greater than specified tRAD(max) limit, then access time controlled exclusively tAA. tWCS restrictive operating parameter. included data sheet electrical characteristics only. tWCS>=tWCS(min), cycle early write cycle data will remain open circuit (high impedance) throughout entire cycle. These parameters referenced leading edge early write cycles. tRASP defines pulse width Fast Page Mode cycles. Access time determined longer tCAC tACP. initial pause 200us required after power followed minimum eight initialization cycles (any combination cycles containing clock such only refresh). internal refresh counter used, minimum eight before refresh cycles required.
Timing Waveforms Please refer attached Timing Waveform-5
Semicon
GMM7322100CMS/SG
Unit: (mm) (1mil 1/1000 inches)
Package Dimension
4250(107.95) 133(3.38) (3.175) R62(1.57) (6.35) (2.032) (6.35) 1750(44.45) (6.35) R62(1.57) DETAIL 1750(44.45) 400(10.16) 3984(101.19) 133(3.38)
DETAIL
41+/-3(1.04+/-0.076) Gold plating 36+/-3(0.914+/-0.076) Solder plating (2.540)
200(5.08)
(0.254) (1.27)
125(3.175)
Tolerances +/-5(0.127) unless otherwise specified.
47(1.19) 54(1.37)
1000(25.4)
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