HB54A5129F1U-A75B/B75B/10B (64M words bits, Bank) HB54A5129F1U ba

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

HB54A5129F1U-A75B/B75B/10B (64M words bits, Bank) HB54A5129F1U ba

Datasheet Thumbnail

Top Searches for this datasheet

512MB Registered SDRAM DIMM
HB54A5129F1U-A75B/B75B/10B (64M words bits, Bank)
HB54A5129F1U bank Double Data Rate (DDR) SDRAM Module, mounted pieces 256Mbits SDRAM (HM5425401BTT) sealed TSOP package, piece clock driver, pieces register driver piece serial EEPROM bits EEPROM) Presence Detect (PD). Read write operations performed cross points /CK. This high-speed data transfer realized 2-bit prefetch-pipelined architecture. Data strobe (DQS) both read write available high speed reliable data design. setting extended mode register, on-chip Delay Locked Loop (DLL) enable disable. outline products 184-pin socket type package (dual lead out). Therefore, makes high density mounting possible without surface mount technology. provides common data inputs outputs. Decoupling capacitors mounted beside each TSOP module board.
Features
184-pin socket type package (dual lead out) Outline: 133.35mm (Length) 30.48mm (Height) 4.00mm (Thickness) Lead pitch: 1.27mm 2.5V power supply (VCC/VCCQ) SSTL-2 interface inputs outputs Clock frequency: 143MHz/133MHz/125MHz (max.) Data inputs outputs synchronized with banks operate simultaneously independently (Component) Burst read/write operation Programmable burst length: Burst read stop capability Programmable burst sequence Sequential Interleave Start addressing capability Even Programmable /CAS latency (CL): 8192 refresh cycles: 7.8µs (8192/64ms) variations refresh Auto refresh Self refresh
Document E0191H10 (Ver. 1.0) Date Published July 2001 Printed Japan URL: http://www.elpida.com
Elpida Memory, Inc. 2001
Elpida Memory, Inc. joint venture DRAM company Corporation Hitachi, Ltd.
HB54A5129F1U-A75B/B75B/10B
Ordering Information
Part number HB54A5129F1U-A75B*1 HB54A5129F1U-B75B*2 HB54A5129F1U-10B* Clock frequency (max.) latency Package Contact
184-pin dual lead socket Gold type
Notes: 143MHz operation /CAS latency 3.5. 100MHz operation /CAS latency 3.0. 125MHz operation /CAS latency 3.5.
Configurations
Front side
Back side
name VREF DQS0 /RESET DQS1 VCCQ DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 DQ18
name DQS8 DQ32 VCCQ DQ33 DQS4 DQ34 DQ35 DQ40 VCCQ DQ41 /CAS DQS5 DQ42 DQ43 DQ48 DQ49
name VCCQ DM0/DQS9 VCCQ DQ12 DQ13 DM1/DQS10 DQ14 DQ15 VCCQ DQ20 DQ21 DM2/DQS11
name DM8/DQS17 VCCQ DQ36 DQ37 DM4/DQS13 DQ38 DQ39 DQ44 /RAS DQ45 VCCQ DM5/DQS14 DQ46 DQ47 VCCQ DQ52 DQ53
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
name VCCQ DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 name VCCQ DQS6 DQ50 DQ51 VCCID DQ56 DQ57 DQS7 DQ58 DQ59 name DQ22 DQ23 DQ28 DQ29 VCCQ DM3/DQS12 DQ30 DQ31 VCCQ /CK0 name DM6/DQS15 DQ54 DQ55 VCCQ DQ60 DQ61 DM7/DQS16 DQ62 DQ63 VCCQ VCCSPD
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
name BA0, DQ63 /RAS /CAS CKE0 /CK0 DQS0 DQS8 DM8/DQS9 DQS17 VCCQ VCCSPD VREF VCCID /RESET Function Address input address Column address
Bank select address Data input/output Check (Data input/output) address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input output data strobe Clock input serial Data input/output serial Serial address input Power internal circuit Power circuit Power serial EEPROM Input reference voltage Ground indentication flag Reset (forces register inputs low) connection
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
Serial Matrix*
Byte
Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM banks Module data width Module data width continuation
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments byte SDRAM bits SSTL 2.5V 2.5*5
Voltage interface level this assembly SDRAM cycle time, -A75B -B75B -10B
SDRAM access from clock (tAC) -A75B/B75B -10B
0.7ns*5 0.8ns*5 Self refresh 2/2.5 Registered 0.2V
DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: latency SDRAM device attributes: latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time -A75B -B75B/10B
Maximum data access time (tAC) from clock -A75B/B75B -10B Minimum clock cycle time Maximum data access time (tAC) from clock Minimum precharge time (tRP)
0.7ns*5 0.8ns*5
20ns
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
Byte Function described Minimum active active delay (tRRD) Minimum /RAS /CAS delay (tRCD) Minimum active precharge time (tRAS) -A75B/B75B -10B Module bank density Address command setup time before clock (tIS) -A75B/B75B -10B Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value (ASCII-8bit code) Comments 15ns 20ns 45ns 50ns bank 512MB 1.1ns*5 1.2ns*5 1.1ns*5 1.2ns*5 0.5ns*5 0.6ns*5 0.5ns*5 0.6ns*5 Future 65ns*5 70ns*5 75ns*5 80ns*5 15ns*5 500ps*5 600ps*5 750ps*5 1000ps*5 Future Initial HITACHI
Address command hold time after clock (tIH) -A75B/B75B -10B Data input setup time before clock (tDS) -A75B/B75B -10B Data input hold time after clock (tDH) -A75B/B75B -10B
Superset information Active command period (tRC) -A75B/B75B -10B Auto refresh active/ Auto refresh command cycle (tRFC) -A75B/B75B -10B
SDRAM cycle max. (tCK max.) Dout skew -A75B/B75B -10B Data hold skew (tQHS) -A75B/B75B -10B
Superset information revision Checksum bytes -A75B -B75B -10B
Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturing location Module part number Module part number Module part number
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
Byte Function described Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -A75B -B75B -10B Module part number -A75B/B75B -10B Module part number -A75B/B75B -10B Module part number -A75B/B75B -10B Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Manufacturer specific data Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD)
Notes: serial data protected. Serial data, "driven Low", Serial data, "driven High" These based JEDEC Committee Ballot JC-42.5-99-129. Byte72 manufacturing location code. (ex: case Japan, byte72 4AH. shows ASCII code.) Bytes through assembly serial number. bits through defined ("1" "0"). These specifications defined based component specification, module.
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
Block Diagram
/RS0 DQS0 DQS1 DQ11 DQS2 DQ16 DQ19 DQS3 DQ24 DQ27 DQS4 DQ32 DQ35 DQS5 DQ40 DQ43 DQS6 DQ48 DQ51 DQS7 DQ56 DQ59 DQS8
DM0/DQS9 DM1/DQS10 DQ12 DQ15 DM2/DQS11 DQ20 DQ23 DM3/DQS12 DQ28 DQ31 DM4/DQS13 DQ36 DQ39 DM5/DQS14 DQ44 DQ47 DM6/DQS15 DQ52 DQ55 DM7/DQS16 DQ60 DQ63 DM8/DQS17
/RAS /CAS CKE0
/RS0 /CS: SDRAMs RBA0 RBA1 BA1: SDRAMs RA12 A12: SDRAMs /RRAS /RAS: SDRAMs /RCAS /CAS: SDRAMs RCKE0A CKE: SDRAMs /RWE /WE: SDRAMs /RESET
D17: HM5425401 bits EEPROM PLL: CDCV857 Register: SSTV16857 Serial
/PCK VCCQ VREF VCCID open
CK0, /CK0 PLL* Note: Wire Clock loading table/Wiring diagrams.
Notes: pull-up resistor required open-drain/open-collector output. pull-up resistor recommended because normal line inacitve "high" state.
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
Differential Clock Wiring (CK0, /CK0)
(nominal) SDRAM stack
OUT1
SDRAM stack Register1
/CK0
OUT'N'
(Typically registers DIMM)
Feedback
Register2
Notes: clock delay from input clock input SDRAM register willl (nominal). Input, output feedback clock lines terminated from line line shown, from line ground. Only output shown output type. additional outputs will wired similar manner. Termination resistors feedback path clocks located after pins PLL.
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
Functions
(CLK), (/CLK) (input pin): master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (/CS) (input pin): When Low, commands data input. When High, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins): These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation". (input pins): address (AX0 AX12) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9, AY11) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin): defines precharge mode when precharge command, read command write command issued. High when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. High when read write command, auto-precharge function enabled. While Low, auto-precharge function disabled. BA0, (input pin): BA0/BA1 bank select signals. memory array divided into bank bank bank bank Low, bank selected. High Low, bank selected. High, bank selected. High High, bank selected. (input pin): controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes High. level must kept cycle LCKEPW) least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH.
Functions
(input output pins): Data input output from these pins. (input output pin): provide read data strobes output) write data strobes input). VCCQ (power supply pins): 2.5V applied. (VCC internal circuit VCCQ output buffer.) VCCSPD (power supply pin): 2.5V applied (For serial EEPROM). (power supply pin): Ground connected. /RESET (input pin): LVCMOS reset input. When /RESET low, registers reset outputs low.
Detailed Operation Part, Characteristics Timing Waveforms
Refer Series datasheet (E0086H10). pins component device fixed level module board. DIMM /CAS latency Device registered type.
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VCC, VCCQ IOUT Topr Tstg Value -1.0 +4.6 -1.0 +4.6 +100 Unit Note
Notes: Respect VSS. Operating Conditions +55°C)
Parameter Supply voltage Symbol VCC, VCCQ Input reference voltage Termination voltage Input high voltage Input voltage Input signal voltage differential input voltage VREF (dc) min. 1.15 VREF 0.04 VREF 0.18 -0.3 -0.3 1.25 VREF max. 1.35 VREF 0.04 VCCQ VREF 0.18 VCCQ VCCQ Unit Notes
VSWING (dc) 0.36
Notes:
parameters referred VSS, when measured. VCCQ must lower than equal VCC. allowed exceed 4.6V period shorter than equal 5ns. allowed outreach below down -1.0V period shorter than equal 5ns. (dc) specifies allowable execution each differential input. VSWING (dc) specifies input differential voltage required switching.
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
Characteristics 55°C, VCC, VCCQ 2.5V 0.2V,
Parameter Operating current (ACTV-PRE) Symbol ICC0 Grade -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B max. 2194 2096 1819 3184 2996 2719 1114 1016 1294 1196 1099 4444 4256 4069 4084 3896 3709 4084 3986 3619 Unit Test condition Notes
VIH, min. VIH, 3.5, min.
Operating current (ACTV-READICC1 PRE) Idle power down standby current ICC2P
Idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current
ICC2N
VIH,
ICC3P
VIH, tRAS max. VIH, VIH, tRFC min., Input Input 0.2V Input 0.2V.
ICC3N
ICC4R
ICC4W
ICC5
Self refresh current
ICC6
Notes.
These data measured under condition that pins connected. bank operation. bank active. banks idle. Command/Address transition once cycle. Data/Data mask transition twice cycle. data this table measured with regard min. general.
Characteristics2 55°C, VCC, VCCQ 2.5V 0.2V,
Parameter Input leakage current Output leakage current Output high voltage Output voltage Symbol min. 0.76 max. 0.76 Unit Test condition VOUT (max.) -15.2mA (min.) 15.2mA Notes
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
Capacitance 25°C, VCC, VCCQ 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data input/output capacitance Symbol Pins max. Unit Notes
Address, /RAS, /CAS, /WE, DQS,
Notes: These parameters measured conditions: 100MHz, VOUT VCCQ/2, VOUT 0.2V. Dout circuits disabled. This parameter sampled 100% tested. Timing Parameter Measured Clock Cycle Registered DIMM
Number clock cycle Parameter Write pre-charge command delay (same bank) Read pre-charge command delay (same bank) Write read command delay input data) Burst stop command write command delay 3.5) Burst stop command High-Z 3.5) Read command write command delay output data) 3.5) Pre-charge command High-Z 3.5) Write command data latency Write recovery Register command active register command Self refresh exit non-read command Self refresh exit read command Power down entry Power down exit command input minimum pulse width Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP tWCD tMRD tSNR tSRD tPDEN tPDEX tCKEPW min. BL/2 BL/2 BL/2 BL/2 BL/2 max.
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
Physical Outline
133.35 0.15 128.95 4.00 (64.48) (DATUM -A-) Unit:
2.30
Component area (Front)
64.77 49.53
1.27 0.10
2.50 0.10
10.00
4.00
Component area (Back)
4.00 0.10
2.00
3.00
Detail
2.50 0.20
Detail 1.27 6.62
0.20 0.15
(DATUM -A-) 2.175 0.90
6.35
3.80
1.00 0.05
1.80 0.10
Note: Tolerance dimensions 0.13 unless otherwise specified.
Preliminary Data Sheet E0191H10 (Ver. 1.0)
30.48 0.15
17.80
HB54A5129F1U-A75B/B75B/10B
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Preliminary Data Sheet E0191H10 (Ver. 1.0)
HB54A5129F1U-A75B/B75B/10B
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
Preliminary Data Sheet E0191H10 (Ver. 1.0)

HB54A5129F1U-A75B/B75B/10B (64M words bits, Bank) HB54A5129F1U ba

Top Searches for this datasheet

Other recent searches