GM71C4800C GM71CS4800CL 524,288WORDS CMOS DYNAMIC Features

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GM71C4800C GM71CS4800CL 524,288WORDS CMOS DYNAMIC Features

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GM71C4800C/CL generation dynamic organized 524,288 bit. GM71C4800C/CL realized higher density, higher performance various functions utilizing advanced CMOS process technology. GM71C4800C/CL offers Fast Page Mode high speed access mode. Multiplexed address inputs permit GM71C4800C/CL packaged standard 28pin plastic SOJ. package size provides high system densities compatible with widely available automated testing insertion equipment. System oriented features include single power supply 5V+/-10% tolerance, direct interfacing capability with high performance logic families such Schottky TTL.
GM71C4800C GM71CS4800CL
524,288WORDS CMOS DYNAMIC
Features
524,288 Words Organization Fast Page Mode Capability Single Power Supply (5V+/-10%) Fast Access Time Cycle Time (Unit:
tRAC tCAC
GM71C(S)4800C/CL-60 GM71C(S)4800C/CL-70
Power Active 715/660 mW(MAX) Standby 5.5mW (CMOS level MAX) 1.1mW (L-series) Only Refresh, before Refresh, Hidden Refresh Capability inputs outputs Compatible 1024 Refresh 1024 Refresh (L-series) Battery Back Operation (L-series) Self-Refresh Operation (GM71C4800C/CL)
Configuration
I/O0 I/O1 I/O2 I/O3
I/O7 I/O6 I/O5 I/O4
(Top View)
GM71C4800C GM71CS4800CL
A0-A9 A0-A9 I/O0-I/O7
Function
Address Inputs Refresh Address Inputs Data-In/Out Address Strobe Column Address Strobe
Function
Read/Write Enable Output Enable Power (+5V) Ground Connection
Ordering Information
Type
GM71C4800CJ-60 GM71C4800CJ-70
Access Time
60ns
Package
Plastic 28Pin Plastic
GM71CS4800CLJ-60 GM71CS4800CLJ-70
60ns
GM71C4800C GM71CS4800CL Absolute Maximum Ratings*
Symbol TSTG VIN/VOUT IOUT Parameter
Ambient Temperature under Bias Storage Temperature (Plastic) Voltage Relative Voltage Relative Short Circuit Output Current Power Dissipation
Rating
-1.0 -1.0
Unit
*Note: Operation above Absolute Maximum Ratings adversely affect device reliability.
Recommended Operating Conditions* 70C)
Symbol Parameter
Supply Voltage Input High Voltage Input Voltage
-1.0
Unit
*Note: voltage reffered
Truth Table
I/O0-I/O7
High-Z High-Z DOUT High-Z DOUT Don't Care High-Z High-Z High-Z High-Z
I/O8-I/O15
High-Z High-Z High-Z DOUT DOUT Don't Care High-Z High-Z High-Z High-Z
Operation
Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Refresh Self Refresh
GM71C4800C GM71CS4800CL Electrical Characteristics (VCC 5V+/-10%, 70C)
Symbol ICC1 Parameter
Output Level Output Level Voltage (IOUT -2mA) Output Level Output Level Voltage (IOUT 2mA) Operating Current Average Power Supply Operating Current (RAS, Cycling: min) Standby Current (TTL) Power Supply Standby Current (RAS, VIH, DOUT High-Z) RAS-Only Refresh Current Average Power Supply Current (tRC min)
Unit Note
ICC2
ICC3
ICC4
Fast Page mode current Average Power Supply Current (tPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, CAS, OE>=VCC-0.2V, DOUT=High-Z) CAS-before-RAS Refresh Current (tRC min)
ICC5
ICC6
ICC7
Battery Back Current (Standby with Refresh) OE=VIH, =VIL, DOUT=High-Z) Standby Current DOUT Enable Self-Refresh Mode Current (RAS, CAS<=0.2V, DOUT High-Z) Input Leakage Current Input (0V<=VIN<=6.5V) Output Leakage Current (DOUT Disabled, 0V<=VOUT<=6.5V)
GM71C4800C GM71CS4800CL
ICC8
ICC9 II(L) IO(L)
Note: depends output load condition when device selected. ICC(max) specified output open condition. Address changed once less while VIL. Address changed once less while LCAS UCAS VIH. VIH>=VCC-0.2V, 0<=VIL<=0.2V, Address changed once less while RAS=VIL. L-Series. Self-refresh series. (GM71C(S)4800C/CL)
GM71C4800C GM71CS4800CL Capacitance (VCC 5V+/-10%, 25C)
Symbol CI/O Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-In/Out)
Unit
Note
Note: Capacitance measured with Boonton Meter effective capacitance measuring method. disable DOUT.
Characteristics (VCC 5V+/-10%, 70C, Notes
Test Conditions Input rise fall times Input level 3.0V Input timing reference level 0.8V, 2.4V Output timing reference level 0.8V, 2.4V Output load 2TTL gate (100pF) (Including scope jig)
GM71C(S)4800 C/CL-60 GM71C(S)4800 C/CL-70
Read, Write, Read-Modify-Write Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read Write Cycle Time Precharge Time Percharge Time Pulse Width Pulse Width Address Set-up Time Address Hold Time Column Address Set-up Time Column Address Hold Time Delay Time Column Address Delay Time Hold Time Hold Time Precharge Time Delay Time Delay Time from Setup Time from TransitionTime (Rise Fall) Refresh Period Refresh Period (L-Series)
Unit Note
tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tOED tDZO tDZC tREF
10,000 10,000
10,000
GM71C4800C GM71CS4800CL Read Cycle
Symbol Parameter
Access Time from Access Time from Access Time from Address Access Time from Read Command Setup Time Read Command Hold Time Read Command Hold Time Column Address Lead Time Column Address Lead Time Output Low-Z Output Data Hold Time Output Data Hold Time from Output Buffer Turn-off Time Output Buffer Turn-off Time from Delay Time
GM71C(S)4800 C/CL-60 GM71C(S)4800 C/CL-70
Unit Note
tRAC tCAC tOAC tRCS tRCH tRRH tRAL tCAL tCLZ tOHO tOFF tOEZ tCDD
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command Lead Time Write Command Lead Time Data-in Setup Time Data-in Hold Time
GM71C(S)4800 C/CL-60 GM71C(S)4800 C/CL-70
Unit Note
tWCS tWCH
tRWL tCWL
GM71C4800C GM71CS4800CL Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time Delay Time Delay Time Column Address Delay Time Hold Time from
GM71C(S)4800 C/CL-60 GM71C(S)4800 C/CL-70
Unit Note
tRWC tRWD tCWD tAWD tOEH
Refresh Cycle
Symbol Parameter
Setup Time (CAS-before-RAS Refresh Cycle) Hold Time (CAS-before-RAS Refresh Cycle) Precharge Hold Time Setup time( refresh cycle
GM71C(S)4800 C/CL-60 GM71C(S)4800 C/CL-70
Unit Note
tCSR tCHR tRPC tWRP
Fast Page Mode Cycle
Symbol Parameter
Fast Page Mode Cycle Time Fast Page Mode Pulse Width Access Time from Precharge Hold Time from Precharge Fast Page ModeRead-Modify-Write Cycle Precharge Delay Time Fast Page Mode Read-Modify-Write Cycle Time
GM71C(S)4800 C/CL- GM71C(S)4800 C/CL-
100,000
100,000
Unit Note
10,20
tRASC tACP tRHCP tCPW tPCM
GM71C4800C GM71CS4800CL Self-Refresh Mode
Symbol Parameter
Pulse Width (Self-Refresh) Precharge Time (Self-Refresh) Hold Time (Self-Refresh)
GM71C(S)4800 C/CL-60 GM71C(S)4800 C/CL-70
Unit Note
tRASS tRPS tCHS
Notes:
Measurements assume Assumes that tRCD<=tRCD(max) tRAD<=tRAD(max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent loads Assumes that tRCD>=tRCD(max) tRAD<=tRAD(max). Assumes that tRCD<=tRCD(max) tRAD>=tRAD(max). tOFF(max) define time which output achieves open circuit condition referenced output voltage levels. VIH(min) VIL(max) reference levels measuring timing input signals. Also, transition times measured between VIL. Operation with tRCD(max) limit insures that tRAC(max) met, tRCD(max) specified reference point only; tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC. Operation with tRAD(max) limit insures that tRAC(max) met, tRAD(max) specified reference point only; tRAD greater than specified tRAD(max) limit, then access time controlled exclusively tAA. tWCS, tRWD, tCWD, tAWD tCPW restrictive operating parameters. They included data sheet electrical characteristics only tWCS >=tWCS(min), cycle early write cycle thedata will remain open circuit (high impedance) throughout entire cycle; tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) tCPW>=tCPW(min), cycle read modify write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate. These parameters referred leading edge early write cycle leading edge delayed write read modify write cycle. tRASC defines pulse width Fast Page mode cycles. Access time determined longer tCAC tACP. initial pause required after power followed minimum eight initialization cycles (RAS only refresh cycle before refresh cycle). internal refresh counter used, minimum eitht before refresh cycles required.
GM71C4800C GM71CS4800CL
delayed write read-modify-write cycles, must disable output buffer prior applying data device. Either TRCH TRRH must satisfied read cycle. supply voltage with pins must same level. supply voltage with pins must same level. enable DOUT buffer when using delayed write timing. distributed refresh mode with interval normal read/write cycle, refresh should executed within immediately affter exiting from before entering into self refresh mode. only refresh burst refresh mode normal read/write cycle, 1024 cycles distributed refresh with 15.6us interval should executed within 16ms immediately after exiting from before entering into self refresh mode. Repetitive self refresh mode without refreshing memory allowed. once exit from self refresh mode, memory cells need refreshed before re-entering self refresh mode again.
GM71C4800C GM71CS4800CL Package Dimensions
Unit: Inches (mm)
0.405(10.29) 0.445(11.31) 0.395(10.03) 0.435(11.05)
0.025(0.64)
0.7197(18.28) 0.730(18.54)
0.128(3.25) 0.148(3.76) 0.050(1.27) 0.015(0.38) 0.020(0.51) 0.026(0.66) 0.032(0.81)
0.380(9.65)
0.360(9.15)

GM71C4800C GM71CS4800CL 524,288WORDS CMOS DYNAMIC Features

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