GM71C4263C GM71CS4263CL 262,144 WORDS CMOS DYNAMIC Features

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GM71C4263C GM71CS4263CL 262,144 WORDS CMOS DYNAMIC Features

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GM71C(S)4263C/CL generation dynamic organized 262,144 bit. GM71C(S)4263C/CL realized higher density, higher performance various functions utilizing advanced CMOS process technology. GM71C(S)4263C/CL offers Extended Data Out(EDO) Mode high speed access mode. Multiplexed address inputs permit GM71C(S)4263C/CL packaged standard plastic SOJ. package size provides high system densities compatible with widely available automated testing insertion equipment. System oriented features include single power supply 5V+/-10% tolerance, direct interfacing capability with high performance logic families such Schottky TTL.
GM71C4263C GM71CS4263CL
262,144 WORDS CMOS DYNAMIC
Features
262,144 Words Organization Extended Data (EDO) Mode Capability Single Power Supply (5V+/-10%) Fast Access Time Cycle Time (Unit:
tRAC tCAC tHPC
GM71C(S)4263C/CL-60 GM71C(S)4263C/CL-70 GM71C(S)4263C/CL-80
Power Active 715/660/605 mW(MAX) Standby 5.5mW (CMOS level MAX) 1.1mW (L-version) Only Refresh, before Refresh, Hidden Refresh Capability inputs outputs Compatible Refresh Refresh (L-version) Battery Back Operation (L-version) byte Control Self-Refresh Operation (L-version)
Configuration
I/O0 I/O1 I/O2 I/O3
I/O15 I/O14 I/O13 I/O12
I/O4 I/O5 I/O6 I/O7
I/O11 I/O10 I/O9 I/O8 LCAS UCAS
(Top View)
Semicon
GM71C4263C GM71CS4263CL
Function
Address Inputs Refresh Address Inputs Data Input Data Output Address Strobe Column Address Strobe
A0-A8 A0-A8 I/O0-I/O15 UCAS, LCAS
Function
Read/Write Enable Output Enable Power (+5V) Ground Connection
Ordering Information
Type
GM71C4263CJ-60 GM71C4263CJ-70 GM71C4263CJ-80 GM71CS4263CLJ-60 GM71CS4263CLJ-70 GM71CS4263CLJ-80
Access Time
60ns 60ns
Package
Plastic Plastic
Semicon
GM71C4263C GM71CS4263CL
Parameter
Ambient Temperature under Bias Storage Temperature (Plastic) Voltage Relative Voltage Relative Short Circuit Output Current Power Dissipation
Absolute Maximum Ratings*
Symbol TSTG VIN/VOUT IOUT Rating
-1.0 -1.0
Unit
Note: Operation above Absolute Maximum Ratings adversely affect device reliability.
Recommended Operating Conditions* 70C)
Symbol Parameter
Supply Voltage Input High Voltage Input Voltage
-1.0
Unit
Note: voltage referred
Truth Table
LCAS
UCAS
I/O0-I/O7
High-Z High-Z DOUT High-Z DOUT Don't Care High-Z High-Z High-Z High-Z
I/O8-I/O15
High-Z High-Z High-Z DOUT DOUT Don't Care High-Z High-Z High-Z High-Z
Operation
Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Refresh Self Refresh
Semicon
GM71C4263C GM71CS4263CL
Parameter Unit Note
Electrical Characteristics (VCC 5V+/-10%, 70C)
Symbol ICC1
Output Level Output Level Voltage (IOUT -2mA) Output Level Output Level Voltage (IOUT 2mA) Operating Current Average Power Supply Operating Current (RAS, LCAS UCAS Cycling: min) Standby Current (TTL) Power Supply Standby Current (RAS, LCAS, UCAS VIH, DOUT High-Z) RAS-Only Refresh Current Average Power Supply Current RAS-Only Refresh Mode (tRC min) mode current Average Power Supply Current (tHPC tHPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, LCAS, UCAS, OE>=VCC-0.2V, DOUT=High-Z) CAS-before-RAS Refresh Current (tRC min) Battery Back Current (Standby with Refresh)
OE=VIH, LCAS, UCAS=VIL, DOUT=High-Z)
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
ICC8
ICC9 II(L) IO(L)
Standby Current LCAS UCAS DOUT Enable Self-Refresh Mode Current (RAS, LCAS, UCAS <=0.2V, DOUT High-Z) Input Leakage Current Input (0V<=VIN<=6.5V) Output Leakage Current (DOUT Disabled, 0V<=VOUT<=6.5V)
Note: depends output load condition when device selected. ICC(max) specified output open condition. Address changed once less while VIL. Address changed once less while LCAS UCAS VIH. VIH>=VCC-0.2V, 0<=VIL<=0.2V, Address changed once less while RAS=VIL. L-version. Self-refresh series. (GM71CS4263CL)
Semicon
GM71C4263C GM71CS4263CL
Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-In/Out)
Capacitance (VCC 5V+/-10%, 25C)
Symbol CI/O
Unit
Note
Note: Capacitance measured with Boonton Meter effective capacitance measuring method. disable DOUT.
Characteristics (VCC 5V+/-10%, 70C, Notes
Test Conditions Input rise fall times Input level 3.0V Input timing reference level 0.8V, 2.4V Output timing reference level 0.8V, 2.0V Output load 1TTL gate (100pF) (Including scope jig)
GM71C(S)4263 C/CL-60 GM71C(S)4263 C/CL-70 GM71C(S)4263 C/CL-80
Read, Write, Read-Modify-Write Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read Write Cycle Time Precharge Time Precharge Time Pulse Width Pulse Width Address Set-up Time Address Hold Time Column Address Set-up Time Column Address Hold Time Delay Time Column Address Delay Time Hold Time Hold Time Precharge Time Delay Time Delay Time from Setup Time from Transition Time (Rise Fall) Refresh Period Refresh Period (L-version)
Unit
Note
tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tREF
10,000 10,000 10,000
10,000 10,000
Semicon
GM71C4263C GM71CS4263CL
GM71C(S)4263 C/CL-60 GM71C(S)4263 C/CL-70 GM71C(S)4263 C/CL-80
Read Cycle
Symbol Parameter
Access Time from Access Time from Access Time from Address Access Time from Read Command Setup Time Read Command Hold Time Read Command Hold Time Column Address Lead Time Column Address Lead Time Output Low-Z Output Data Hold Time Output Data Hold Time from Output Buffer Turn-off Time Output Buffer Turn-off Time from Delay Time Output Data Hold Time from Output Buffer Turn-off Time from Output Buffer Turn-off Time from Delay Time Delay Time
Unit
Note
tRAC tCAC tOAC tRCS tRCH tRRH tRAL tCAL tCLZ tOHO tOFF tOEZ tCDD tOHR tOFR tWEZ tWDD tRDD
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command Lead Time Write Command Lead Time Data-in Setup Time Data-in Hold Time
GM71C(S)4263 C/CL-60 GM71C(S)4263 C/CL-70 GM71C(S)4263 C/CL-80
Unit
Note
tWCS tWCH
tRWL tCWL
Semicon
GM71C4263C GM71CS4263CL
GM71C(S)4263 C/CL-60 GM71C(S)4263 C/CL-70 GM71C(S)4263 C/CL-80
Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time Delay Time Delay Time Column Address Delay Time Hold Time from
Unit
Note
tRWC tRWD tCWD tAWD tOEH
Refresh Cycle
Symbol Parameter
Setup Time (CAS-before-RAS Refresh Cycle) Hold Time (CAS-before-RAS Refresh Cycle) Precharge Hold Time
GM71C(S)4263 C/CL-60 GM71C(S)4263 C/CL-70 GM71C(S)4263 C/CL-80
Unit
Note
tCSR tCHR tRPC
Mode Cycle
Symbol Parameter
Mode Cycle Time Mode Pulse Width Access Time from Precharge Hold Time from Precharge Mode Read-Modify-Write Cycle Precharge Delay Time Mode Read-Modify-Write Cycle Time hold time referred setup time Read command hold time from Precharge Output data hold time from
GM71C(S)4263 C/CL- GM71C(S)4263 C/CL- GM71C(S)4263 C/CL-
100,000
Unit
Note
tHPC tRASP tACP tRHCP tCPW tHPRWC tCOL tCOP tRCHP tDOH
100,000
100,000
10,20
Semicon
GM71C4263C GM71CS4263CL
GM71CS4263 CL-60 GM71CS4263 CL-70 GM71CS4263 CL-80
Self-Refresh Mode
Symbol Parameter
Pulse Width (Self-Refresh) Precharge Time (Self-Refresh) Hold Time (Self-Refresh)
Unit
Note
tRASS tRPS tCHS
Notes:
Measurements assume Assumes that tRCD<=tRCD(max) tRAD<=tRAD(max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent loads Assumes that tRCD>=tRCD(max) tRAD<=tRAD(max). Assumes that tRCD<=tRCD(max) tRAD>=tRAD(max). tOFF(max), tOEZ(max), tOFR(max), tWEZ(max) define time which output achieves open circuit condition referenced output voltage levels. VIH(min) VIL(max) reference levels measuring timing input signals. Also, transition times measured between VIL. Operation with tRCD(max) limit insures that tRAC(max) met, tRCD(max) specified reference point only; tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC. Operation with tRAD(max) limit insures that tRAC(max) met, tRAD(max) specified reference point only; tRAD greater than specified tRAD(max) limit, then access time controlled exclusively tAA. tWCS, tRWD, tCWD, tAWD tCPW restrictive operating parameters. They included data sheet electrical characteristics only tWCS >=tWCS(min), cycle early write cycle data will remain open circuit (high impedance) throughout entire cycle; tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) tCPW>=tCPW(min), cycle read modify write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate. These parameters referred UCAS LCAS leading edge early write cycle leading edge delayed write read modify write cycle. tRASP defines pulse width mode cycles. Access time determined longer tCAC tACP. initial pause required after power followed minimum eight initialization cycles (RAS only refresh cycle before refresh cycle). internal refresh counter used, minimum eight before refresh cycles required.
Semicon
GM71C4263C GM71CS4263CL
delayed write read-modify-write cycles, must disable output buffer prior applying data device. After reset, tOEH tCWL will remain open circuit (high impedance tOEH tCWL invalid data will each I/O. Either tRCH tRRH must satisfied read cycle. When both LCAS UCAS same time, 16-bits data written into device. LCAS UCAS cannot staggered within same write/read cycles. pins shall supplied with same voltages. tASC, tCAH, tRCS, tRCH, tWCS, tWCH, tCSR tRPC determined earlier falling edge UCAS LCAS. tCRP, tCHR, tACP tCPW determined later rising edge UCAS LCAS. tCWL, tDH, tCHS should satisfied both UCAS LCAS. determined time that both UCAS LCAS high. When output buffers enabled once, sustain impedance state until valid data obtained. When output buffer turned within very short time, generally causes large VCC/VSS line noise, which causes degrade min/VIL level. Either tODD tCDD must satisfied. Either tDZO tDZC must satisfied. tHPC (min) achieved during series mode write cycles mode read cycles. both write read operation mixed mode cycle (EDO mode cycle (1), (2)), minimum value cycle tCAS +2tT becomes greater than specified tHPC (min) value. value cycle time mixed mode shown mode cycle(1) (2).
Semicon
GM71C4263C GM71CS4263CL
Notes concerning 2CAS control
Please separate UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS allowed under following conditions. Each UCAS/LCAS should satisfy timing specifications individually. Different operation mode upper/lower byte allowed; such following.
UCAS
Delay Write Early Write
LCAS
Closely separated upper/lower byte control allowed. However when condition(tCP<=tUL) satisfied, page mode performed.
UCAS
LCAS
Byte control operation remaining LCAS UCAS high guaranteed.
Semicon
GM71C4263C GM71CS4263CL
tRAS
Timing Waveforms
tCSH tRCD
UCAS LCAS
tCRP tRSH tCAS
tRAD
tRAL tCAL
tOFR tOHR
tASR
ADDRESS
tRAH
tASC
tCAH
tRDD
COLUMN
tRCHR tRCS
tRRH tRCH tWEZ
tDZC
High-Z
tCDD
tWDD
tDZO
tOAC
tODD
tCAC tRAC tCLZ
High-Z DOUT
INVALID DOUT DOUT
tOEZ tOHO tOFF
FIGURE READ CYCLE
Don't care
Semicon
tRAS
GM71C4263C GM71CS4263CL
tRSH tRCD tCSH tCAS tCRP
UCAS LCAS
tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tWCS
tWCH
High-Z*** DOUT
Don't care
Don't care tWCS tWCS (min)
FIGURE EARLY WRITE CYCLE
Semicon
tRAS
GM71C4263C GM71CS4263CL
tRSH tRCD tCSH tCAS tCRP
UCAS LCAS
tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tCWL tRCS
tRWL
tDZC
High-Z
tDZO
tODD
tOEH
tOEZ tCLZ
DOUT
INVALID DOUT
High-Z Don't care
FIGURE DELAYED WRITE CYCLE
*Note delayed write read-modify-write cycles, must disable output buffer prior applying data device. After reset, tOEH>=tCWL, will remain open circuit (high impedance); tOEH<=tCWL, invalid data will each I/O.
Semicon
tRWC tRAS
GM71C4263C GM71CS4263CL
tRCD
tCAS
tCRP
UCAS LCAS
tRAD tASR tRAH tASC tCAH
COLUMN
ADDRESS
tRCS tRWD
tCWD tAWD
tCWL tRWL
tDZC
High-Z
tDZO tOAC
tODD
tOEH
tCAC tRAC
DOUT
INVALID DOUT
tOEZ tOHO
DOUT
High-Z Don't care
tCLZ
FIGURE READ MODIFY WRITE CYCLE
*Note delayed write read-modify-write cycles, must disable output buffer prior applying data device. After reset, tOEH>=tCWL, will remain open circuit (high impedance); tOEH<=tCWL, invalid data will each I/O.
Semicon
tRAS
GM71C4263C GM71CS4263CL
tCRP
UCAS LCAS
tRPC
tCRP
tASR
ADDRESS
tRAH
tOFR tOFF
DOUT
INVALID DOUT
High-Z
Don't care
Don't care
FIGURE ONLY REFRESH CYCLE
Semicon
GM71C4263C GM71CS4263CL
tRAS
tRAS
tRPC
UCAS LCAS
tCSR tCHR
tRPC tCSR tCHR
tCRP
ADDRESS
tOFF
DOUT
INVALID DOUT
tOFR
High-Z
Don't care
Don't care
FIGURE BEFORE REFRESH CYCLE
Semicon
tRAS
GM71C4263C GM71CS4263CL
tRAS tRAS
tRCD tRSH tCHR tCRP
UCAS LCAS
tRAD tASR
ADDRESS
tRAL tCAH
COLUMN
tRAH
tASC
tRRH tRCS
tRCH
tWDD
High-Z
tDZC tDZO tOAC
tRDD tCDD tODD
tCAC tRAC tCLZ
High-Z DOUT
INVALID DOUT DOUT
tOFF
tOHO
tOEZ tWEZ
tOHR
FIGURE HIDDEN REFRESH CYCLE
Don't care
tOFR
Semicon
GM71C4263C GM71CS4263CL
tRASP tRHCP
tRCD
UCAS LCAS
tCSH tCAS
tHPC tCAS
tRSH tCAS tCRP
tRAD tASR tRAH tASC
tCAL tCAH tASC
tCAL tCAH tASC
tRAL tCAH
ADDRESS
COLUMN
COLUMN
COLUMN
tRCHP tRCS
tRCH tRRH
tCAL tACP tCAC tACP tCAC tOEZ tDOH tDOH
DOUT DOUT
tWEZ tOHR tOFR tOFF
tOAC tRAC tCAC
DOUT
High-Z
DOUT
INVALID DOUT
INVALID DOUT
INVALID DOUT
Don't care
FIGURE EXTENDED DATA MODE READ CYCLE
Semicon
GM71C4263C GM71CS4263CL
tRASP tRHCP
tHPC tCSH
UCAS LCAS
tHPC tCAS
tHPC tRSH tCAS tRCHP
tCRP
tCAS tRCHR tCAS
tRCS
tRCH
tRCS
tRRH tRCH
tRAL tASC tCAH tASR
ADDRESS
tWDD tRDD tCDD
tASC
tCAH
tASC
tCAH
tASC
tCAH
tRAH
COLUMN COLUMN COLUMN COLUMN
tCAL tDZC
High-Z
tCAL
tCAL
tCAL
tOFR tOHR tOFF
tDZO tCOL
tCOP
tODD
tACP tOAC tCAC tRAC tWEZ
DOUT High-Z
DOUT
tOEZ tCAC tOHO tOAC
DOUT
tACP tCAC tDOH
DOUT INVALID DOUT
tACP tOEZ tOHO
DOUT
tOEZ tOHO tCAC
tOAC
DOUT
Don't care
FIGURE EXTENDED DATA MODE READ CYCLE CONTROL)
*Note Hi-Z control rising edge disables data outputs. When goes high during high, data will come until next access. When goes during high, data will come until next access.
Semicon
GM71C4263C GM71CS4263CL
tRASP tHPC tCAS tCAS tCAS tHPC tHPC tCAS tRSH tCRP
tCSH
LCAS
UCAS
tASR tRAH tASC
ADDRESS
tASC tCAH
COLUMN
tASC
tCAH
tCAH
COLUMN
tASC
tCAH
COLUMN
COLUMN
tDZC tRCS
tCAL
tCAL
tCAL
tRCHP tCAL
tRRH tRCH
tWDD
High
tDZO
tCAC tDOH
tCAC tCOL tOAC tOHO tOEZ tCOP tODD
tRAC
High
tOAC tACP
DOUT INVALID DOUT
tOEZ tOHO
tCAC tOAC tACP
DOUT
tOEZ tOHO tOFF tOFR tOHR
DOUT
LDOUT
DOUT
DOUT
tACP
tCAC
DOUT
High UDOUT
DOUT
Don't care
FIGURE EXTENDED DATA MODE READ CYCLE (2CAS TYPE)
Semicon
GM71C4263C GM71CS4263CL
tRASP tRCD
tCSH tCAS
tHPC tCAS
tRSH tCAS
tCRP
UCAS LCAS
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
ADDRESS
COLUMN
COLUMN
COLUMN
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
High-Z** DOUT
Don't care tWCS >=tWCS (min)
Don't care
FIGURE EXTENDED DATA MODE EARLY WRITE CYCLE
Semicon
GM71C4263C GM71CS4263CL
tRASP
tRCD
UCAS LCAS
tCSH tCAS tHPC tCAS
tRSH tCAS
tCRP
tRAD tASR tRAH tASC tCAH
COLUMN
tASC tCAH
COLUMN
tASC tCAH
COLUMN
ADDRESS
tCWL tRCS
tCWL tRCS tRCS
tCWL tRWL
tDZC
tDZC
tDZC
High-Z
tDZO tODD tOEH
tDZO tODD tOEH
tDZO tODD tOEH
tCLZ tOEZ
DOUT
INVALID DOUT
tCLZ tOEZ
tCLZ tOEZ
High-Z
INVALID DOUT
INVALID DOUT
Don't care
FIGURE EXTENDED DATA MODE DELAYED WRITE CYCLE
Semicon
GM71C4263C GM71CS4263CL
tRASP
tRCD
UCAS LCAS
tHPRWC tRSH tCAS tCAS tCAS
tCRP
tRAD tASR tRAH tASC tCAH
COLUMN
tASC tCAH
COLUMN
tASC tCAH
COLUMN
ADDRESS
tRCS
tRWD tAWD tCWD
tCWL tRCS
tCPW tAWD tCWD
tCWL tRCS
tCPW tAWD tCWD
tCWL tRWL
tDZC
tDZC
tDZC
High-Z
tDZO tODD tOEZ
tDZO tDZO tOEH tOEZ tOHO tOAC tCAC tCLZ tOHO tODD tOEH tOEZ tOAC tCAC tACP tCLZ
High-Z
tODD tOEH tOHO
tOAC tCAC tRAC tCLZ
DOUT
INVALID DOUT
tACP
DOUT
INVALID DOUT
DOUT
INVALID DOUT
DOUT
Don't care
FIGURE EXTENDED DATA MODE READ MODIFY WRITE CYCLE
Semicon
GM71C4263C GM71CS4263CL
tRASP
tRCD tCAS tCSH tWCS tWCH
tCAS
tCAS
tCAS tRCHP tRSH tRAL tCAL tASC tCAH tCAH
COLUMN
tCRP
UCAS LCAS
tCPW tAWD
tRRH tRCH
tRAH tASR
ADDRESS
tASC tCAH
COLUMN
tASC tCAH
COLUMN
tASC
COLUMN
tCAL
High
tRDD tCDD
tWDD tODD
tOHO tCAC tOAC tACP
High
tDOH tACP
DOUT
tCAC tOEZ
tCAC tOAC tACP tOFF tOFR
DOUT
tOEZWEZ tOHO
DOUT
DOUT
Don't care
FIGURE EXTENDED DATA MODE CYCLE
Semicon
GM71C4263C GM71CS4263CL
tRASP
tRCD tCSH tCAS tRCHR tRCS tRCH tWCH tWCS tCPW tASC tASC tCAH tCAH
COLUMN
tCAS tCAS
tCAS
tCRP
UCAS LCAS
tRSH tRAL
tRRH tRCH
tRAH tASR
ADDRESS
tCAH
COLUMN
tASC
tASC tCAH
COLUMN
COLUMN
tCAL
High
tCAL
tCAL
tCAL
tRDD tCDD tWDD
tODD
tCOL
tODD
tCAC tOAC tRAC
DOUT
tOEZ tOHO
DOUT
tCAC tACP tOAC
High
tCOP tOEZ
tCAC tOAC tACP
tOFF tOFR
DOUT
tWEZ tOEZ tOHO
DOUT
Don't care
FIGURE EXTENDED DATA MODE CYCLE
*Note :tHPC(min) achieved during series mode write cycles mode read cycles. both write read operation mixed mode cycle(EDO mode cycle (1),(2) minimum value cycle (tCAS 2tT) becomes greater than specified tHPC(min) value. value cycle time mixed mode shown mode cycle (2).
Semicon
GM71C4263C GM71CS4263CL
tRASS tCSR tCHS tCRP tRPS
tRPC
UCAS LCAS
tOFR tOFF
DOUT
INVALID DOUT
High-Z
Don't care
Address, Don't care
self refresh current achieved introducing extremely long internal refresh cycle. Therefore some care needs taken refresh. Please tRASS timing, 10us<=tRASS<=100us. During this period, device transition state from normal operation mode self refresh mode. tRASS>=100us, then precharge time should tRPS instead tRP. only refresh burst refresh mode normal read/write cycle, cycles distributed refresh with 15.6us interval should executed within immediately after exiting from before entering into self refresh mode. distributed refresh mode with 15.6us interval normal read/write cycle, refresh should executed within 15.6us immediately after exiting from before entering into self refresh mode. Repetitive self refresh mode without refreshing memory allowed. Once exit from self refresh mode, memory cells need refreshed before re-entering self refresh mode again.
FIGURE SELF-REFRESH CYCLE
Semicon
GM71C4263C GM71CS4263CL
Unit: Inches (mm)
Package Dimension
0.025(0.64) 0.405(10.29) 0.445(11.30) 0.395(10.03) 0.435(11.06) 0.375(9.55) 0.366(9.30)
1.010(25.67) 1.021(25.93)
0.083(2.10)
0.128(3.25) 0.148(3.75) 0.050(1.27) 0.015(0.38) 0.020(0.50) 0.026(0.66) 0.032(0.81)

GM71C4263C GM71CS4263CL 262,144 WORDS CMOS DYNAMIC Features

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