GM71C4260C GM71CS4260CL 262,144 WORDS CMOS DYNAMIC Features

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GM71C4260C GM71CS4260CL 262,144 WORDS CMOS DYNAMIC Features

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GM71C(S)4260C/CL generation dynamic organized 262,144 bit. GM71C(S)4260C/CL realized higher density, higher performance various functions utilizing advanced CMOS process technology. GM71C(S)4260C/CL offers Fast Page Mode high speed access mode. Multiplexed address inputs permit GM71C(S)4260C/CL packaged standard plastic SOJ. package size provides high system densities compatible with widely available automated testing insertion equipment. System oriented features include single power supply 5V+/-10% tolerance, direct interfacing capability with high performance logic families such Schottky TTL.
GM71C4260C GM71CS4260CL
262,144 WORDS CMOS DYNAMIC
Features
262,144 Words Organization Fast Page Mode Capability Single Power Supply (5V+/-10%) Fast Access Time Cycle Time
(Unit:
tRAC tCAC
GM71C(S)4260C/CL-60 GM71C(S)4260C/CL-70 GM71C(S)4260C/CL-80
Configuration
Power Active 715/660/605 mW(MAX) Standby 5.5mW (CMOS level MAX) 1.1mW (L-version) Only Refresh, before Refresh, Hidden Refresh Capability inputs outputs Compatible Refresh Cycles/8ms Refresh Cycles/128ms (L-version) Battery Back Operation (L-version) byte Control Self-Refresh Operation (L-version)
I/O0 I/O1 I/O2 I/O3
I/O15 I/O14 I/O13 I/O12
I/O4 I/O5 I/O6 I/O7
I/O11 I/O10 I/O9 I/O8 LCAS UCAS
(Top View)
Semicon
GM71C4260C GM71CS4260CL
Function
Address Inputs Refresh Address Inputs Data Input Data Output Address Strobe Column Address Strobe
A0-A8 A0-A8 I/O0-I/O15 UCAS, LCAS
Function
Read/Write Enable Output Enable Power (+5V) Ground Connection
Ordering Information
Type
GM71C4260CJ-60 GM71C4260CJ-70 GM71C4260CJ-80 GM71CS4260CLJ-60 GM71CS4260CLJ-70 GM71CS4260CLJ-80
Access Time
60ns 60ns
Package
Plastic Plastic
Semicon
GM71C4260C GM71CS4260CL
Parameter
Ambient Temperature under Bias Storage Temperature (Plastic) Voltage Relative Voltage Relative Short Circuit Output Current Power Dissipation
Absolute Maximum Ratings*
Symbol TSTG VIN/VOUT IOUT Rating
-1.0 -1.0
Unit
Note: Operation above Absolute Maximum Ratings adversely affect device reliability.
Recommended Operating Conditions* 70C)
Symbol Parameter
Supply Voltage Input High Voltage Input Voltage
-1.0
Unit
Note: voltage referred
Truth Table
LCAS
UCAS
I/O0-I/O7
High-Z High-Z DOUT High-Z DOUT Don't Care High-Z High-Z High-Z High-Z
I/O8-I/O15
High-Z High-Z High-Z DOUT DOUT Don't Care High-Z High-Z High-Z High-Z
Operation
Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Refresh Self Refresh
Semicon
GM71C4260C GM71CS4260CL
Parameter Unit Note
Electrical Characteristics (VCC 5V+/-10%, 70C)
Symbol ICC1
Output Level Output Level Voltage (IOUT -2mA) Output Level Output Level Voltage (IOUT 2mA) Operating Current Average Power Supply Operating Current (RAS, LCAS UCAS Cycling: min) Standby Current (TTL) Power Supply Standby Current (RAS, LCAS, UCAS VIH, DOUT High-Z) RAS-Only Refresh Current Average Power Supply Current (tRC min) Fast Page mode current Average Power Supply Current (tPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, LCAS, UCAS, OE>=VCC-0.2V, DOUT=High-Z) CAS-before-RAS Refresh Current (tRC min)
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
Battery Back Current (Standby with Refresh) OE=VIH, LCAS, UCAS=VIL, DOUT=High-Z)
ICC8
ICC9 IL(I) IL(O)
Standby Current LCAS UCAS DOUT Enable Self-Refresh Mode Current (RAS, LCAS, UCAS <=0.2V, DOUT High-Z) Input Leakage Current Input (0V<=VIN<=6.5V) Output Leakage Current (DOUT Disabled, 0V<=VOUT<=6.5V)
Note: depends output load condition when device selected. ICC(max) specified output open condition. Address changed once less while VIL. Address changed once less while LCAS UCAS VIH. VIH>=VCC-0.2V, 0<=VIL<=0.2V, Address changed once less while RAS=VIL. L-version. Self-refresh series. (GM71CS4260CL)
Semicon
GM71C4260C GM71CS4260CL
Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-In/Out)
Capacitance (VCC 5V+/-10%, 25C)
Symbol CI/O
Unit
Note
Note: Capacitance measured with Boonton Meter effective capacitance measuring method. disable DOUT.
Characteristics (VCC 5V+/-10%, 70C, Notes
Test Conditions Input rise fall times Input level 3.0V Input timing reference level 0.8V, 2.4V Output timing reference level 0.8V, 2.4V Output load 2TTL gate (100pF) (Including scope jig)
GM71C(S)4260 GM71C(S)4260 C/CL-60 C/CL-70 GM71C(S)4260 C/CL-80
Read, Write, Read-Modify-Write Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read Write Cycle Time Precharge Time Precharge Time Pulse Width Pulse Width Address Set-up Time Address Hold Time Column Address Set-up Time Column Address Hold Time Delay Time Column Address Delay Time Hold Time Hold Time Precharge Time Delay Time Delay Time from Setup Time from Transition Time (Rise Fall) Refresh Period Refresh Period (L-version)
Unit
Note
10,000
10,000 10,000
tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tREF
10,000 10,000
Semicon
GM71C4260C GM71CS4260CL
GM71C(S)4260 GM71C(S)4260 C/CL-70 C/CL-60 GM71C(S)4260 C/CL-80
Read Cycle
Symbol Parameter
Access Time from Access Time from Access Time from Address Access Time from Read Command Setup Time Read Command Hold Time Read Command Hold Time Column Address Lead Time Column Address Lead Time Output Low-Z Output Data Hold Time Output Data Hold Time from Output Buffer Turn-off Time Output Buffer Turn-off Time from Delay Time
Unit
Note
tRAC tCAC tOAC tRCS tRCH tRRH tRAL tCAL tCLZ tOHO tOFF tOEZ tCDD
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command Lead Time Write Command Lead Time Data-in Setup Time Data-in Hold Time
GM71C(S)4260 C/CL-60 GM71C(S)4260 C/CL-70 GM71C(S)4260 C/CL-80
Unit
Note
tWCS tWCH
tRWL tCWL
Semicon
GM71C4260C GM71CS4260CL
GM71C(S)4260 C/CL-60 GM71C(S)4260 C/CL-70 GM71C(S)4260 C/CL-80
Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time Delay Time Delay Time Column Address Delay Time Hold Time from
Unit
Note
tRWC tRWD tCWD tAWD tOEH
Refresh Cycle
Symbol Parameter
Setup Time (CAS-before-RAS Refresh Cycle) Hold Time (CAS-before-RAS Refresh Cycle) Precharge Hold Time Setup time( refresh cycle
GM71C(S)4260 C/CL-60 GM71C(S)4260 C/CL-70 GM71C(S)4260 C/CL-80
Unit
Note
tCSR tCHR tRPC tWRP
Fast Page Mode Cycle
Symbol Parameter
Fast Page Mode Cycle Time Fast Page Mode Pulse Width Access Time from Precharge Hold Time from Precharge Fast Page Mode Read-Modify-Write Cycle Precharge Delay Time Fast Page Mode Read-Modify-Write Cycle Time
GM71C(S)4260 C/CL- GM71C(S)4260 C/CL- GM71C(S)4260 C/CL-
100,000
100,000
Unit
Note
tRASC tACP tRHCP tCPW tPRWC
100,000
10,20
Semicon
GM71C4260C GM71CS4260CL
GM71CS4260 CL-60 GM71CS4260 CL-70 GM71CS4260 CL-80
Self-Refresh Mode
Symbol Parameter
Pulse Width (Self-Refresh) Precharge Time (Self-Refresh) Hold Time (Self-Refresh)
Unit
Note
tRASS tRPS tCHS
Notes:
Measurements assume Assumes that tRCD<=tRCD(max) tRAD<=tRAD(max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent loads Assumes that tRCD>=tRCD(max) tRAD<=tRAD(max). Assumes that tRCD<=tRCD(max) tRAD>=tRAD(max). tOFF(max), tOEZ(max), tOFR(max), tWEZ(max) define time which output achieves open circuit condition referenced output voltage levels. VIH(min) VIL(max) reference levels measuring timing input signals. Also, transition times measured between VIL. Operation with tRCD(max) limit insures that tRAC(max) met, tRCD(max) specified reference point only; tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC. Operation with tRAD(max) limit insures that tRAC(max) met, tRAD(max) specified reference point only; tRAD greater than specified tRAD(max) limit, then access time controlled exclusively tAA. tWCS, tRWD, tCWD, tAWD tCPW restrictive operating parameters. They included data sheet electrical characteristics only tWCS >=tWCS(min), cycle early write cycle data will remain open circuit (high impedance) throughout entire cycle; tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) tCPW>=tCPW(min), cycle read modify write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate. These parameters referred UCAS LCAS leading edge early write cycle leading edge delayed write read modify write cycle. tRASC defines pulse width Fast Page mode cycles. Access time determined longer tCAC tACP. initial pause required after power followed minimum eight initialization cycles (RAS only refresh cycle before refresh cycle). internal refresh counter used, minimum eight before refresh cycles required.
Semicon
GM71C4260C GM71CS4260CL
delayed write read-modify-write cycles, must disable output buffer prior applying data device. After reset, tOEH tCWL will remain open circuit (high impedance tOEH tCWL invalid data will each I/O. Either tRCH tRRH must satisfied read cycle. When both LCAS UCAS same time, 16-bits data written into device. LCAS UCAS cannot staggered within same write/read cycles. pins shall supplied with same voltages. tASC, tCAH, tRCS, tRCH, tWCS, tWCH, tCSR tRPC determined earlier falling edge UCAS LCAS. tCRP, tCHR, tACP tCPW determined later rising edge UCAS LCAS. tCWL, tDH, tCHS should satisfied both UCAS LCAS. determined time that both UCAS LCAS high. When output buffers enabled once, sustain impedance state until valid data obtained. When output buffer turned within very short time, generally causes large VCC/VSS line noise, which causes degrade min/VIL level. Either tODD tCDD must satisfied. Either tDZO tDZC must satisfied.
Semicon
GM71C4260C GM71CS4260CL
Notes concerning 2CAS control
Please separate UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS allowed under following conditions. Each UCAS/LCAS should satisfy timing specifications individually. Different operation mode upper/lower byte allowed; such following.
UCAS
Delay Write Early Write
LCAS
Closely separated upper/lower byte control allowed. However when condition (tCP<=tUL) satisfied, fast page mode performed.
UCAS
LCAS
Semicon
GM71C4260C GM71CS4260CL
Timing Waveforms
tRAS
tCSH tRCD
UCAS LCAS
tCRP tRSH tCAS
tRAD tASR
ADDRESS
tRAL tASC tCAH
tRAH
COLUMN
tRRH tRCS
tRCH tCAC tOFF1
DOUT
High-Z DOUT
tRAC
tOFF2
tDZC
High-Z
tCDD
tDZO
tOAC
tODD
FIGURE READ CYCLE
Don't care
Semicon
GM71C4260C GM71CS4260CL
tRAS
tRSH tRCD tCSH tCAS tCRP
UCAS LCAS
tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tWCS
tWCH
High-Z** DOUT
Don't care
Don't care
FIGURE EARLY WRITE CYCLE
Semicon
GM71C4260C GM71CS4260CL
tRAS
tRSH tRCD tCSH tCAS tCRP
UCAS LCAS
tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tCWL tRCS
tRWL
tDZC
tDZO
DOUT
tODD
INVALID DOUT
tOEH
tCOD
tOFF2
Don't care
enable DOUT during delayed write cycle FIGURE DELAYED WRITE CYCLE
Semicon
GM71C4260C GM71CS4260CL
tRWC tRAS
tRCD
tCRP
UCAS LCAS
tRAD tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tRCS tRWD
tCWD tAWD
tCWL tRWL
tRAC tDZC tCAC
High-Z
tODD
tOEH
DOUT
DOUT
tDZO
tOAC
tOFF2
FIGURE READ MODIFY WRITE CYCLE
Don't care
Semicon
tRAS
GM71C4260C GM71CS4260CL
tCRP
UCAS LCAS
tRPC
tCRP
tASR
tRAH
ADDRESS
High-Z DOUT
Don't care Refresh Address: A0-A8 (AX0-AX8) FIGURE ONLY REFRESH CYCLE
tRAS
tRAS tCSR tCHR
tRPC tCPN
UCAS LCAS
tRPC tCPN tCSR tCHR
tCRP
ADDRESS
tOFF1
High-Z DOUT
Don't care
Don't care Don't extend tRAS>= tRAS(Max).
Untested self refresh mode actived loss data resulted
FIGURE BEFORE REFRESH CYCLE
Semicon
GM71C4260C GM71CS4260CL
tRAS
tRAS
(Refresh)
tRAS
(Refresh)
tRCD
UCAS LCAS
tRSH
tCHR tCAS
tCRP
tRAD tASR
ADDRESS
tRAL tCAH
COLUMN
tRAH
tASC
tRCH tRCS
tRRH tCAC tRAC tOFF1
DOUT
DOUT
tDZC
High-Z
tOFF2 tCDD
tDZO
tOAC
tODD
Don't care
FIGURE HIDDEN REFRESH CYCLE
Semicon
GM71C4260C GM71CS4260CL
tRASP tRHCP
tCSH tRCD tCAS
tCAS
tRSH tCAS
tCRP
UCAS LCAS
tRAL tASR
ADDRESS
tRAD tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN
COLUMN
COLUMN
tRCS tRCS
tRCS tRCH
tRRH tRCH
tRCH
tDZC tCDD
High-Z
tDZC tCDD
High-Z
tDZC tCDD
High-Z
tCAC tRAC
tODD
tCAC tACP tOFF1
DOUT
tCAC tACP tDZO
DOUT
tOFF1 tODD
tOFF1
DOUT
DOUT
tOAC tDZO tOFF2 tDZO
tOAC tODD tOFF2
tOAC tOFF2
FIGURE FAST PAGE MODE READ CYCLE
Don't care
Semicon
GM71C4260C GM71CS4260CL
tRASP
tRCD
UCAS LCAS
tCSH tCAS
tCAS
tRSH
tCAS
tCRP
tASR
ADDRESS
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN
COLUMN
COLUMN
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
High-Z DOUT
Don't care
Don't care
FIGURE FAST PAGE MODE EARLY WRITE CYCLE
Semicon
GM71C4260C GM71CS4260CL
tRASP
tRCD
UCAS LCAS
tCSH tCAS tCAS
tRSH tCAS
tCRP
tRAD tASR tRAH tASC tCAH
COLUMN
tASC tCAH
COLUMN
tASC tCAH
COLUMN
ADDRESS
tCWL tRCS
tCWL tRCS tRCS
tCWL tRWL
High-Z DOUT
tODD
tOEH
Don't care
FIGURE FAST PAGE MODE DELAYED WRITE CYCLE
Semicon
GM71C4260C GM71CS4260CL
tRASP
tRCD
UCAS LCAS
tPRWC
tCRP
tRAD tASC tRAH tASR
ADDRESS
tACP tCAH tASC tCAH tASC tCAH
tRCS
tAWD tCWD tRWD
tCWL tRCS
tCWL tAWD tCWD tCPW
tRCS
tCPW tAWD tCWD
tCWL tRWL
tCAC tDZC
tCAC tDZC
tACP tDZC
tRAC
tOAC tOEH
DOUT
tDZO tOAC
DOUT
tDZO tOEH tOAC
DOUT
DOUT
tOFF2 tDZO
tODD
tOFF2 tODD
tOFF2 tODD
tOEH
Don't care
FIGURE FAST PAGE MODE READ MODIFY WRITE CYCLE
Semicon
GM71C4260C GM71CS4260CL
tRASS tCSR tCHS tCRP tRPS
tRPC tCPN
ADDRESS
tOFF1
High-Z DOUT
Don't care
Don't care
self refresh current achieved introducing extremely long internal refresh cycle. Therefore some care needs taken refresh. Please tRASS timing, 10us<=tRASS<=100us. During this period, device transition state from normal operation mode self refresh mode. tRASS>=100us, then precharge time should tRPS instead tRP. only refresh burst refresh mode normal read/write cycle, cycle distributed refresh with 15.6us interval should executed within immediately after exiting from before entering into self refresh mode. distributed refresh mode with 15.6us interval normal read/write, refresh should executed within 15.6us immediately after exiting from before entering into self refresh mode. Repetitive self refresh mode without refreshing memory allowed. Once exit from self refresh mode, memory cells need refreshed before re-entering self refresh mode again.
FIGURE SELF-REFRESH CYCLE
Semicon
GM71C4260C GM71CS4260CL
Unit: Inches (mm)
Package Dimension
0.025(0.64) 0.405(10.29) 0.445(11.30) 0.395(10.03) 0.435(11.06) 0.375(9.55) 0.366(9.30)
1.010(25.67) 1.021(25.93)
0.083(2.10)
0.128(3.25) 0.148(3.75) 0.050(1.27) 0.015(0.38) 0.020(0.50) 0.026(0.66) 0.032(0.81)

GM71C4260C GM71CS4260CL 262,144 WORDS CMOS DYNAMIC Features

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