GM71C16100C 16,777,216 WORDS CMOS DYNAMIC Features 16,7
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GM71C16100C generation dynamic organized 16,777,216 Bit. GM71C16100C realized higher density, higher performance various functions utilizing advanced CMOS process technology. GM71C16100C offers Fast Page Mode high speed access mode. Multiplexed address inputs permit GM71C16100C packaged standard 24(26) SOJ. package size provides high system densities compatible with widely available automated testing insertion equipment. System oriented features include single power supply 5V+/-10% tolerance, direct interfacing capability with high performance logic families such Schottky TTL.
GM71C16100C
16,777,216 WORDS CMOS DYNAMIC
Features
16,777,216 Words Fast Page Mode Capability Single Power Supply (5V+/-10%) Fast Access Time Cycle Time (Unit:
tRAC
GM71C16100C-5 GM71C16100C-6 GM71C16100C-7
tCAC
Power Active 495/440/385mW (MAX) Standby 11mW (CMOS level MAX) Only Refresh, before Refresh, Hidden Refresh Capability inputs outputs Compatible 4096 Refresh Test function 16-bit parallel test mode
Configuration 24(26)
Dout
(Top View)
Semicon
A0-A11 A0-A11
GM71C16100C
Function
Address Inputs Refresh Address Inputs Data Input Address Strobe Column Address Strobe
DOUT
Function
Read/Write Enable Data Output Connection Power (+5V) Ground
Ordering Information
Type
GM71C16100CJ-5 GM71C16100CJ-6 GM71C16100CJ-7
Access Time
Package
24(26) Plastic
Absolute Maximum Ratings*
Symbol TSTG VIN/OUT IOUT Parameter
Ambient Temperature under Bias Storage Temperature (Plastic) Voltage Relative Voltage Relative Short Circuit Output Current Power Dissipation
Rating
-1.0 -1.0
Unit
Note: Operation above Absolute Maximum Ratings adversely affect device reliability.
Recommended Operating Conditions 70C)
Symbol Parameter
Supply Voltage Input High Voltage Input Voltage
-1.0
Unit
Semicon Electrical Characteristics (VCC 5V+/-10%, 70C)
Symbol ICC1 Parameter
Output Level Output Level Voltage (IOUT -5mA) Output Level Output Level Voltage (IOUT 4.2mA) Operating Current Average Power Supply Operating Current (RAS, Cycling: min)
GM71C16100C
Unit
Note
ICC2
Standby Current (TTL) Power Supply Standby Current (RAS, VIH, DOUT High-Z) RAS-Only Refresh Current Average Power Supply Current RAS-Only Refresh Mode (RAS Cycling, VIH, min) Fast Page Mode Current Average Power Supply Current Fast Page Mode (RAS VIL, CAS, Address Cycling: min) Standby Current (CMOS) Power Supply Standby Current (RAS, CAS>=VCC-0.2V, DOUT High-Z) CAS-before-RAS Refresh Current (tRC min)
ICC3
ICC4
ICC5
ICC6
ICC7
Standby Current DOUT Enable Input Leakage Current Input (0V<=VIN<=6V) Output Leakage Current (DOUT Disabled, 0V<=VOUT<=6V)
IL(I) IL(O)
Note: depends output load condition when device selected. ICC(max) specified output open condition. Address changed once less while VIL. Address changed once less while VIH.
Semicon Capacitance (VCC 5V+/-10%, 25C)
Symbol Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-Out)
GM71C16100C
Unit
Note
Note: Capacitance measured with Boonton Meter effective capacitance measuring method. disable DOUT.
Characteristics (VCC 5V+/-10%, 70C, Notes
Test Conditions Input rise fall times: Input timing reference levels: 0.8V, 2.4V Output timing reference levels: 0.4V, 2.4V Output timing reference levels: 0.4V, 2.4V Output load gate (Including scope jig)
Read, Write, Read-Modify-Write Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read Write Cycle Time Precharge Time Precharge Time Pulse Width Pulse Width Address Time Address Hold Time Column Address Set-up Time Column Address Hold Time Delay Time Column Address Delay Time Hold Time Hold Time Precharge Time Transition Time (Rise Fall)
GM71C16100 GM71C16100 GM71C16100
10,000 10,000
Unit
Note
tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP
10,000 10,000
10,000 10,000
Semicon Read Cycle
Symbol Parameter
Access Time from Access Time from Access Time from Address Read Command Setup Time Read Command Hold Time Read Command Hold Time Column Address Lead Time Column Address Lead Time Output Low-Z Output Data Hold Time Output Buffer Turn-off Time
GM71C16100 GM71C16100
GM71C16100C
GM71C16100
Unit
Note
6,7,16 7,8,15 7,9,16
tRAC tCAC tRCS tRCH tRRH tRAL tCAL tCLZ tOFF
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command Lead Time Write Command Lead Time Data-in Setup Time Data-in Hold Time
GM71C16100 GM71C16100 GM71C16100
Unit
Note
tWCS tWCH
tRWL tCWL
Semicon Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time Delay Time Delay Time Column Address Delay Time
GM71C16100 GM71C16100
GM71C16100C
GM71C16100
Unit
Note
tRWC tRWD tCWD tAWD
Refresh Cycle
Symbol Parameter
Setup Time (CAS-before-RAS Refresh Cycle) Hold Time (CAS-before-RAS Refresh Cycle) Setup Time (CAS-before-RAS Refresh Cycle) Hold Time (CAS-before-RAS Refresh Cycle) Precharge Hold Time
GM71C16100 GM71C16100 GM71C16100
Unit
Note
tCSR tCHR tWRP tWRH tRPC
Fast Page Mode Cycle
Symbol Parameter
Fast Page Mode Cycle Time Fast Page Mode Pulse Width Access Time from Precharge Hold Time from Precharge
GM71C16100 GM71C16100 GM71C16100
Unit
Note
100,000
tRASP tACP tRHCP
100,000
100,000
7,15,16
Semicon Fast Page Mode Read-Modify-Write Cycle
Symbol Parameter
Fast Page Mode Read-Modify-Write Cycle Time Delay Time from Precharge
GM71C16100C
GM71C16100 GM71C16100 GM71C16100
Unit
Note
tPRWC tCPW
Test Mode Cycle
Symbol Parameter
Test Mode Setup Time Test Mode Hold Time
GM71C16100 GM71C16100 GM71C16100
Unit
Note
tWTS tWTH
Notes: Measurements assume initial pause 200us required after power followed minimum eight initialization cycles (any combination cycles containing RAS-only refresh CAS-beforeRAS refresh). internal refresh counter used, minimum eight CAS-before-RAS refresh cycles required. Operation with tRCD(max) limit insures that tRAC(max) met, tRCD(max) specified reference point only; tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC. Operation with tRAD(max) limit insures that tRAC(max) met, tRAD(max) specified reference point only; tRAD greater than specified tRAD(max) limit, then access time controlled exclusively tAA. VIH(min) VIL(max) reference levels measuring timing input signals. Also, transition times measured between VIH(min) VIL(max). Assume that tRCD<=tRCD(max) tRAD<=tRAD(max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent loads Assume that tRCD>=tRCD(max) tRAD<=tRAD(max). Assume that tRCD<=tRCD(max) tRAD>=tRAD(max). Either tRCH tRRH must satisfied read cycles.
Semicon
GM71C16100C
tOFF(max) tOEZ(max) define time which outputs achieve open circuit condition referenced output voltage levels. tWCS, tRWD, tCWD, tAWD tCPW restrictive operating parameters. They included data sheet electrical characteristics only; tWCS>=tWCS(min), cycles early write cycle data will remain open circuit (high impedance) throughout entire cycle; tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), tCWD>=tCWD(min), tAWD>= tAWD(min) tCPW>=tCPW(min), cycle read-modify-write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate. These parameters referenced leading edge early write cycles leading edge delayed write read-modify-write cycles. tRASP defines pulse width fast page mode cycles. Access time determined longer tCAC tACP DRAM offers 16-bit time saving parallel test mode. Address CA1, CA10 CA11 don't care during test mode. Test mode performing WE-and-CAS-before-RAS (WCBR) cycle. 16-bit parallel test mode, data written into bits parallel read from Dout. bits equal (all 0s), data output high state during test mode read cycle, then device passed. they equal, data output state, then device failed. Refresh during test mode operation performed normal read cycles WCBR refresh cycles. test mode enter normal operation mode, perform either regular CAS-before-RAS refresh cycle RAS-only refresh cycle. test mode read cycle, value tRAC, tAA, tCAC tACP delayed specified value. These parameters should specified test mode cycles adding above value specified value this data sheet.
Semicon Timing Waveforms
tRAS
GM71C16100C
tCSH tRCD
tCRP tRSH tCAS
tRAD
tRAL tCAL
tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tRRH tRCS
tRCH tCAC
tRAC tCLZ
High-Z DOUT
INVALID DOUT DOUT
tOFF
Don't care
FIGURE READ CYCLE
Semicon
tRAS
tRSH tRCD tCSH tCAS tCRP
tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tWCS
tWCH
High-Z** DOUT
Don't care
tWCS tWCS (min)
FIGURE EARLY WRITE CYCLE
GM71C16100C
INVALID
care
FIGURE DELAYED WRITE CYCLE
Semicon
GM71C16100C
tRWC tRAS
tCRP tRCD tCAS
tRAD tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tRCS tRWD
tCWD tAWD
tCWL tRWL
tCAC tRAC tCLZ
DOUT
INVALID DOUT DOUT
tOFF
Don't care
FIGURE READ MODIFY WRITE CYCLE
Semicon
GM71C16100C
tRAS
tCRP
tRPC
tCRP
tASR
ADDRESS
tRAH
tOFF
DOUT
INVALID DOUT
High-Z
Don't care Don't care
FIGURE ONLY REFRESH CYCLE
Semicon
GM71C16100C
tRAS
tRAS
tRPC
tCSR tCHR
tRPC tCSR tCHR
tCRP
tWRP
tWRH
tWRP
tWRH
ADDRESS
tOFF
DOUT
INVALID DOUT
High-Z
Don't care
FIGURE BEFORE REFRESH CYCLE
Semicon
tRAS
GM71C16100C
tRAS tRAS
tRCD tRSH tCHR tCRP
tRAD tASR
ADDRESS
tRAL tCAH
COLUMN
tRAH
tASC
tWRP tRCS
tRRH tCAC
tWRH
tWRP
tWRH
tRAC tCLZ
DOUT High-Z
INVALID DOUT DOUT
tOFF
Don't care
FIGURE HIDDEN REFRESH CYCLE
Semicon
GM71C16100C
tRASP tRHCP
tRCD
tCSH tCAS
tCAS
tRSH tCAS
tCRP
tRAL tRAD tASR
ADDRESS
tCAL tCAH
COLUMN
tCAL tASC tCAH tASC
tRAH
tASC
tCAL tCAH
COLUMN
COLUMN
tRCS tRCS
tRRH tRCS tRCH
tRCH tCAC
tRCH tCAC tACP tOFF tOFF
DOUT INVALID DOUT
tCAC tACP tCLZ
DOUT
tRAC tCLZ
DOUT High-Z
INVALID DOUT DOUT
tOFF
INVALID DOUT
Don't care
FIGURE FAST PAGE MODE READ CYCLE
Semicon
GM71C16100C
tRASP
tRCD
tCSH tCAS
tCAS
tRSH
tCAS
tCRP
tASR
ADDRESS
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN
COLUMN
COLUMN
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
High-Z** DOUT
Don't care
tWCS tWCS (min)
FIGURE FAST PAGE MODE EARLY WRITE CYCLE
Semicon
GM71C16100C
tRASP
tRCD
tCSH tCAS
tCAS
tRSH tCAS tCRP
tRWL tASR
ADDRESS
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN
COLUMN
COLUMN
tRCS
tCWL
tRCS
tCWL
tRCS
tCWL
tCLZ
High-Z DOUT
tOFF
INVALID DOUT
tCLZ
tOFF
INVALID DOUT
tCLZ
tOFF
INVALID DOUT
Don't care
FIGURE FAST PAGE MODE DELAYED WRITE CYCLE
Semicon
GM71C16100C
tRASP
tRCD
tPRWC tCAS tCAS
tRSH tCAS tCRP
tRAD tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tASC
tCAH
tASC
tCAH
COLUMN
COLUMN
tRCS tRWD
tAWD
tCWL
tRCS tAWD
tRCS tCWL tAWD tCWD tCPW
tRWL tCWL
tCWD
tCWD tCPW
tCAC tRAC tCLZ
High-Z DOUT
INVALID DOUT
tOFF
DOUT
tCAC tOFF
DOUT
tCAC tACP tCLZ
DOUT
tACP tCLZ
tOFF
INVALID DOUT
INVALID DOUT
Don't care
FIGURE FAST PAGE MODE READ MODIFY WRITE CYCLE
Semicon
GM71C16100C
Cycle***
Test Mode Cycle
Reset Cycle*,*** Normal Mode
RAS-only refresh
Don't care
Address, Don't care FIGURE TEST MODE CYCLE
tRAS
tRPC
tCSR
tCHR
tRPC
tCRP
tWTS tWTH
ADDRESS
tOFF
High-Z DOUT INVALID DOUT
Don't care
FIGURE TEST MODE CYCLE
Semicon Test Mode Reset Cycle
GM71C16100C
tRAS tCSR tCHR tRPC
tCRP
tRPC
tWRP
tWRH
ADDRESS
tOFF
DOUT
INVALID DOUT
High-Z
FIGURE CAS-BEFORE-RAS REFRESH CYCLE
Don't care
tRAS
tCRP
tRPC
tASR
ADDRESS
tRAH
tOFF
DOUT
INVALID DOUT
High-Z
Don't care
FIGURE ONLY REFRESH CYCLE
Semicon Package Dimension
24(26)
GM71C16100C
Unit: Inches (mm)
0.025(0.64) 0.305(7.75) 0.295(7.49) 0.329(8.38) 0.340(8.64) 0.260(6.60) 0.275(6.99) 0.085(2.16)
0.661(16.80) 0.669(17.00)
0.128(3.25) 0.147(3.75) 0.050(1.27) 0.015(0.38) 0.020(0.50) 0.026(0.66) 0.032(0.81)
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