PM8620 NSE-20G Narrowband Switch Element Data Sheet
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
PM8620
NSE-20G
Narrowband Switch Element
Data Sheet
Preliminary Issue March 2002
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2000170, Issue
NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
Legal Information
Copyright
Copyright 2002 PMC-Sierra, Inc. rights reserved. information this document proprietary confidential PMC-Sierra, Inc., customers' internal use. event, part this document reproduced redistributed form without express written consent PMC-Sierra, Inc. PMC-2000170 (P4), 1991274 (R5)
Disclaimer
None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement. event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage.
Trademarks
PMC-Sierra, NSE-20G, CHESS, CHESS-II, SPECTRA, SBS, SBSLITE, TSE, TBS, TUPP+622, SPECTRA-2488, TEMAP-84 trademarks PMC-Sierra, Inc. Other product company names mentioned herein trademarks their respective owners.
Patents
technology discussed this document protected more patent grants.
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
Contacting PMC-Sierra
PMC-Sierra 8555 Baxter Place Burnaby, Canada Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Site: http://www.pmc-sierra.com
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Revision History
Issue
Issue Date
March 2002
Details Change
Updated followings sections: Section Ball Diagram Section Description: Removed items Notes Description grouped information Section 12.1 Power Sequencing. Section Cross Switch (DCB): Expanded Table Switching Control Layout, with more details clarify information. Section Normal Mode Register Description: Renamed Reg003h, Reg004h, Reg00Eh, Reg00Fh, Reg010h (i.e. page user bit) consistent with naming convention. Clarified relationship between Reg009h, Reg00Dh, Reg102h+N*20h R8TD operations. Removed internal signal name Reg012h, Reg013h, Reg014h descriptions. Corrected descriptions Reg00Ah, Reg00Bh, Reg048h, Reg101h+N*20h, Reg115h+N*20h. Corrected default value RX_THRESHOLD_VAL bits Reg116h+N*20h added notes conditions achieve specified default values. Changed description SWAPV Reg04Ch. Changed description Reg10Ah+N*20h Reg10Bh+N*20h. Changed Center default value Reg108h+N*20h. Updated Table NSE-20G Register Map. Added better description clarify correct usage CRC_ERR Reg115h+N*20h Section 11.1 JTAG Test Port: Changed Register (i.e. SCAN_EN cell) Logic cell updated NOTES with change. Section Absolute Maximum Ratings: Corrected values 1.8V Supply Voltage, Voltage Digital Pin, Voltage LVDS Table Characteristic Section Characteristics: Updated values Table Characteristic Added Section 15.1 Power Sequencing. Updated following diagrams: Replaced TCMP with ICMP Fig19, Fig21, Fig22, Fig23, Fig24. Removed figure showing Input Interface. Changed Fig25. Operation with Removed ambiguous description from Section 12.8. Updated MPIF timing numbers (Table 16/17): Moved tSalw, tSlw, tSar, tSalr,tPrd, tZrd, tZinth from specification specification. Changed value tSaw, tSalw, tVl, tHdw, tHaw, tVwr; tSar, tSalr, tVl,
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
Issue
Issue Date
Details Change
tPrd. Changed numbering convention RP/RN, TP/TN [31:0] instead [32:1] Ball Diagram Description section order consistent with convention Normal Mode Register Description section. Clarified handling unused LVDS pairs Description section Design Notes section. Updated Section 12.11 12.12 Updated delay values section 13.2 Transmit Interface Timing Added Thermal Information Changed SBS-lite SBSLITE Added Application Diagrams Fixed small series typos
Issue
May, 2001
Edited document modified section registers 012h, 013h, 014h, 04ch, 10ah+ n*20h, 111h+n*20h, section Modified diagram, description added section Issue datasheet created. Document creation.
Issue Issue
June, 2000 February, 2000
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
Table Contents
Legal Information. Copyright. Disclaimer Trademarks Patents Contacting PMC-Sierra. Revision History. Table Contents. List Registers. List Figures List Tables. Features Applications. References. Application Examples. Block Diagram. Description Ball Diagram. Description Functional Description 9.10 LVDS Overview Receive 8B/10B Frame Aligner (R8TD) Transmit 8B/10B Encoder (T8TE) Cross switch (DCB) Clock Synthesis Transmit Reference Digital Wrapper (CSTR) Fabric Latency. JTAG Support. Microprocessor Interface. In-band Link Controller (ILC). Microprocessor Interface.
Normal Mode Register Description Test Features Description 11.1 JTAG Test Port Operation
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9
Software Default settings "C1" Synchronization. Synchronized Control Setting Changes Interaction with Switching Cycle When Using Controlling Frame Alignment Receive Port Cross-Bar Switch (DCB) Operation. TelecomBus Mode Operation. Column Mode Operation Mode Operation.
12.10 with Mode Operation. 12.11 Using In-Band Link Controller (ILC) 12.12 Switch Setting Algorithm 12.13 JTAG Support. Functional Timing. 13.1 13.2 Receive Interface Timing. Transmit Interface Timing.
Absolute Maximum Ratings Power information 15.1 15.2 Power Sequencing Analog Power Filtering Recommendations
D.C. Characteristics Microprocessor Timing Characteristics A.C. TIMING CHARACTERISTICS 18.1 18.2 18.3 18.4 19.1 19.2 20.1 Notes Input Timing. Reset Timing Serial Interface JTAG Port Interface. Packaging Information Thermal Information UBGA -35x35 BODY SUFFIX)
NSE-20G Ordering Thermal Information
Mechanical Information.
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
List Registers
Register 000H:NSE Master Reset. Register 001H:NSE Individual Channel Reset Register 002H: Master JTAG Register 003H: In-Band Link Transmit Page Register 004H: In-Band Link Transmit Page Register 005H: Master Interrupt Source Register 006H: Master Interrupt Source Register 007H: Master R8TD Interrupt Source. Register 008H: Master T8TE Interrupt Source Register 009H: Master Clock Monitor, Accumulation Trigger. Register 00AH: select. Register 00BH: Interrupt Enable Register Register 00CH: Subsystem Interrupt Enable Register Register 00DH: R8TD Register Register 00EH: In-Band Link Transmit User Register 00FH: In-Band Link Transmit User Register 010H: In-Band Link Transmit User Register 011H: FREE User Register Register 012H: Correct R8TD_RX_C1 Pulse Monitor Register 013H: Unexpected R8TD_RX_C1 Interrupt. Register 014H: Missing R8TD_RX_C1 Interrupt. Register 015H: Unexpected R8TD_RX_C1 Interrupt Enable Register 016H: Missing R8TD_RX_C1 Interrupt Enable Register 020H, 024H: CSTR Control Register 021H, 025H: CSTR Interrupt Enable Lock Status. Register 022H, 026H: CSTR Interrupt Indication Register 040H: Configuration port 31-30 Register Register 041H: Configuration port 29-24 Register Register 042H: Configuration port 23-18 Register Register 043H: Configuration port 17-12 Register Register 044H: Configuration port 11-6 Register Register 045H: Configuration port Register Register 046H: Configuration Output Register 047H: Access Mode Register
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
Register 048H: delay (RC1DLY) Register Register 04AH: Frame Size Register. Register 04CH: Configuration Register Register 04DH: Interrupt Status Register Register 100H N*20H, R8TD Control Status Register 101H N*20H, R8TD Interrupt Status. Register 102H N*20H, R8TD Line Code Violation Count Register 103H N*20H, RXLV Control. Register 108H N*20H, T8TE Control Status Register 109H N*20H, T8TE Interrupt Status Register 10AH N*20H: T8TE Time-slot Configuration Register 10BH N*20H: T8TE Time-slot Configuration Register 10CH N*20H, T8TE Test Pattern. Register 10DH N*20H, TXLV PISO Control. Register 110H N*20H, Transmit FIFO Data Register 111h N*20H, Transmit Control Register Register 112h N*20H, Transmit Misc. Status FIFO Synch Register Register 113h N*20H, Receive FIFO Data Register Register 114h N*20H, Receive Control Register Register 115h N*20H, Receive Auxiliary, Status FIFO Synch Register. Register 116h N*20H, Interrupt Enable Control Register. Registers: 117h N*20H, Interrupt Reason Register
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
List Figures
Figure Voice/Media Gateway DS-0 Switch Fabric Solution Figure OC-48 T1/E1 (Individually Drop/Add T1/E1 STS-48). Figure VT/TU One-Armed Cross-Connect Figure DS-0/T1/E1/VT/TU/STS-1-Capable OC-48/STM-12 Any-Service-AnyPort (ASAP) Architecture Figure NSE-20G Block Diagram Figure UBGA-480 Ball Diagram (Bottom-View). Figure Generic LVDS Link Block Diagram Figure Character Alignment State Machine Figure Frame Alignment State Machine. Figure In-Band Signaling Channel Message Format Figure In-Band Signaling Channel Header Format Figure Input Observation Cell (IN_CELL) Figure Output Cell (OUT_CELL) Figure Bidirectional Cell (IO_CELL) Figure Layout Output Enable Bidirectional Cells. Figure Shutting Down Link Figure "C1" Synchronization Control Figure Temux84/SBS/NSE/SBS/AALIGATOR32 System Switching with Figure Multi-frame Timing Figure Switch Timing DSOs with Figure Temux84/SBS/NSE/SBS/FREEDM336 System Switch CAS. Figure Switch Timing DSOs Without Figure Switch Timing Figure Operation with Figure Boundary Scan Architecture Figure Controller Finite State Machine. Figure Receive Interface Timing Figure Transmit Interface Timing Figure Timing. Figure Analog Power Filter Circuit. Figure Microprocessor Interface Read Timing Figure Microprocessor Interface Write Timing
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
Figure Input Timing Figure RSTB Timing Figure JTAG Port Interface Timing.
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
List Tables
Table Descriptions Table SBI336S Character Encoding Table Serial TelecomBus Character Encoding Table Switching control layout. Table In-band Message Header Fields Table NSE-20G Register Map. Table FIFO Message Level Table RXFIFO Threshold Values Table RXFIFO Timeout Delay Table Instruction Register (Length bits) Table Identification Register Table Boundary Scan Register Table Absolute Maximum Ratings. Table Analog Power Filters Table Characteristics Table Microprocessor Interface Read Access Table Microprocessor Interface Write Access. Table Input Timing (Figure 33). Table RSTB Timing (Figure Table Serial Interface Table JTAG Port Interface (Figure
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Features
Implements Scaleable Bandwidth Interconnect granularity Space switch. Implements SONET/SDH VT1.5/VT2/TU11/TU12 granularity Space switch serial 777.6MHz LVDS TelecomBus. With allied device, implements granularity Memory-Space-Memory switch. Supports STS-12 equivalent serial ports 777.6MHz, 8b/10b encoded LVDS links (each port either Serial TelecomBus Serial SBI336) When configured mode switches N*DS0 tributaries aggregate columns switching TVT1.5, TVT2, tributaries. When configured serial 777.6MHz TelecomBus interface switches SONET/SDH virtual tributary tributary unit STS-1. Switching arbitrary non-standard octet aggregates supported. Unicast, multicast, broadcast supported switching modes. Provides 20Gb/s (258,048 DS0s, 10,752 T1s/VT1.5s, 8,064 E1s/VT2s, DS3s/E3s) fullduplex switching. allied SBSLITE devices support four 19.44 77.76MHz SBI336 which communicate with PMC-Sierra's device family. Alternatively SBSLITE devices support four 19.44MHz STS-3 TelecomBuses 77.76MHz STS-12 TelecomBus connection with PMC-Sierra's SPECTRAfamily devices. combined applications with PMC-Sierra CHESSSet devices (TSEand TBSdevices). Supports 32-bit microprocessor interface that used configure/control NSE, make DS0-granularity switch settings. Supports clean error checked 8Mb/s full-duplex, in-band communications channels from NSE's attached microprocessor attached microprocessors each attached SBS336S devices. This channel used initialize control SBSs, other such devices, implement call-establishment set-up changes. Supports JTAG non-LVDS signals. Requires dual power supplies 1.8V 3.3V. Packaged ball UBGA. conjunction with SBSor SBSLITEdevice, supports "1+1" "1:n" fabric redundancy.
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Applications
T1/E1 SONET/SDH Cross-connects T1/E1 SONET/SDH Add-Drop Multiplexers OC-48 Multi-service Access Multiplexers Channelized OC-12/OC-48 Service Port Switches Serial backplane board interconnect Shelf Shelf cabled serial interconnect Voice Gateways
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References
ANSI T1.105-1995, "Synchronous Optical Network (SONET) Basic Description including Multiplex Structure, Rates, Formats", 1995. Bell Communications Research SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue Revision January 1999. ITU, Recommendation G.707 "Digital Transmission Systems Terminal Equipment General", March 1996. IEEE 802.3, "Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method Physical Layer Specifications", Section 36.2, 1998. A.X. Widmer P.A. Franaszek, DC-Balanced, Partitioned-Block, 8B/10B Transmission Code," Journal Research Development, Vol. September 1983, 440-451. U.S. Patent 4,486,739, P.A. Franaszek A.X. Widmer, "Byte Oriented Balanced (0,4) 8B/10B Partitioned Block Transmission Code," December 1984. IEEE 1596.3-1996, "IEEE Standard Low-Voltage Differential Signals (LVDS) Scalable Coherent Interface (SCI)", Approved March 1996 L.R. Ford, D.R. Fulkerson, "Flows Networks'', Maximum Cardinality Matchings Bipartite Graphs Electronic Industries Association. Methodology Thermal Measurement Component Packages (Single Semiconductor Device): EIA/JESD51. December 1995. Electronic Industries Alliance 1999. Integrated Circuit Thermal Test Method Environmental Conditions -Junction-to-Board: JESD51-8. October 1999. Telcordia Technologies. Network Equipment-Building System (NEBS) Requirements: Physical Protection: Telcordia Technologies Generic Requirements GR-63-CORE. Issue October 1995. SEMI (Semiconductor Equipment Materials International). SEMI G30-88 Test Method Junction-to-Case Thermal Resistance Measurements Ceramic Packages. 1988.
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
Application Examples
voice/media gateways, softswitches wireless voice gateways (MSC/BSC/BTS) require DS-0 cross-connect groom traffic among line cards voice/data processing cards. Figure illustrates typical voice/media gateway implementation. FPGA required interconnect H-MVIP interfaces voice/data processing cards. code FPGA (SHB) available from PMC-Sierra under license agreement.
Figure Voice/Media Gateway DS-0 Switch Fabric Solution
TEMUX PM8316
SBSLITE PM861
SBSLITE
H-MVIP
NSE-20G
Termination Card DS-3, STS-3/STM-1
PM861
PM8620
SPECTRA-622 PM5313 TelecomBus
TEMUX TEMUX TEMUX TEMUX PM8316 PM8316 PM8316 PM8316
SBSLITE PM861
Ethernet Switch Fabric
Voice Processing Cards
SONET/SDH STS-12/STM4 Termination Card
Figure illustrates possible T1/E1 add/drop multiplexer (ADM) architectures. this example, SBSLITE NSE-20G operate TelecomBus mode. SBSLITE requires path pointer justifications translated into tributary pointer movements that fixed location following TUPP+622device performs Switching within SBSLITE utilizing Transparent Virtual Tributary (TVT), mapping across SBI336S LVDS links.
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NSE-20G ASSP Telecom Standard Product Data Sheet Prelimnary
Figure OC-48 T1/E1 (Individually Drop/Add T1/E1 STS-48)
SPECTRA 2488 PM5315
TUPP+622 TUPP+622 TUPP+622 TUPP+622
PM5363 PM5363 PM5363 PM5363
SBSLITE SBSLITE SBSLITE PM861 SBSLITE PM861 PM861 PM861
NSE-20G PM8620
SBSLITE SBSLITE SBSLITE PM861 SBSLITE PM861 PM8611 PM861
TUPP+622 TUPP+622 TUPP+622 TUPP+622
PM5363 PM5363 PM5363 PM5363
SPECTRA 2488 PM5315
PM8610
TEMAP-84 TEMAP-84 TEMAP-84 TEMAP-84
PM5366 PM5366 PM5366 PM5366
OCTLIU OCTLIU OCTLIU OCTLIU PM4318 PM4318 PM4318 PM4318
provide customers with cost-effective groom some STS-1/AU-3 granularity traffic VT/TU level, equipment vendors consider adding one-armed narrowband cross-connect cards part their access, metro edge, metro core product offerings. Figure illustrates possible architecture that integrates CHESS-IIand CHESSNB family devices. this example, narrowband cross-connect comprises four 2.5G VT/TU processing cards VT/TU cross-connect fabric.
Figure VT/TU One-Armed Cross-Connect
160G STS-1/AU-3 Switch Fabric
SerDes/ Optics SerDes/ Optics
OC-192/ STM-64 Line Card
SPECTRA 9953
9953
9953
SPECTRA 9953
PM517
PM5307
PM5374
PM5307
PM517
OC-192/ STM-64
Line Card VT/TU Switch Fabric Card
PM5310
High-Speed Serial Links Parallel TelecomBus
TUPP+622
FPGA
PM5363
SBSLITE PM8611
NSE-20G PM8620
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Figure illustrates DS-0/T1/E1/VT/TU/STS-1-capable OC-48/STM-12 Any-Service-AnyPort (ASAP) architecture. high-capacity optical signals channelized down DS-0 level groomed variety service cards. T1s, E1s, Transparent VTs, subrate rate links switched between physical layer layer devices using SBS, SBSLITE NSE-20G devices.
Figure DS-0/T1/E1/VT/TU/STS-1-Capable OC-48/STM-12 Any-Service-Any-Port (ASAP) Architecture
Optics/ SERDES
TelecomBus
SPECTRA 2488 PM5315
TEMUX-84 TEMUX-84 TEMUX-84 TEMUX-84 PM831 PM831 PM831 PM831 TEMUX TEMUX TEMUX TEMUX PM831 PM831 PM831 PM831 TEMUX TEMUX-84 TEMUX-84 TEMUX TEMUX PM831 PM831 PM831 PM831 TEMUX TEMUX TEMUX PM831 TEMUX PM831 PM831 PM831
OC-48
SBSLITE SBSLITE PM861 SBSLITE PM861 SBSLITE PM861
LVDS
NSE-20G PM8620
NSE-20G PM8620
LVDS
SBSLITE PM861
PM8610
PM8610
PM8610
FREEDM-336
PM7388
S/UNI S/UNI S/UNI S/UNI IMA-84 IMA-84 IMA-84 IMA-84 PM7341 PM7341 PM7341 PM7341
AAL1gator-32 PM73122
OCTLIU PM4318
Any-PHY (Packet Cell)
Serial Clock Data
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Block Diagram
organized granularity space switch. Alternatively organized self-aligning (with respect STS-12 boundaries TelecomBus mode) VT1.5/VT2 granularity space switch. R8TD, combination with RXLV receive, decode align incoming SBI336/STS-12-equivalent LVDS links; outputs provided primary switching flow, in-band signaling channel. These provide analog digital functions terminate full-duplex 777.6MHz serial SBI336 777.6MHz serial TelecomBus LVDS. Crossbar Switch (DCB) stage switches data control signals between ports. switching instructions stored pages configured offline online allowing user modify offline page. T8TE, combination with PISO TXLV perform 8b/10b coding emits LVDS streams. These provide analog digital functions launch full-duplex 777.6MHz serial SBI336 777.6MHz serial TelecomBus LVDS. microprocessor interface in-band link controllers, (ILCs) provide clean (error checked) channel between SBSLITEs. This used send messages between microprocessor-and microprocessors user-defined format.
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Figure NSE-20G Block Diagram
RP[0] RN[0]
LVDS Receiver (RXLV)
Data Recovery Unit (DRU)
Receive 8B/10B Decoder (R8TD)
In-Band Link Controller (ILC) In-Band Link Controller (ILC)
In-Band Link Controller (ILC) In-Band Link Controller (ILC)
Transmit 8B/10B Encoder (T8TE)
LVDS Transmit Transmitt Serializer (PISO) (TXLV)
TP[0] TN[0]
RP[1] RN[1]
LVDS Receiver (RXLV)
Data Recovery Unit (DRU)
Receive 8B/10B Decoder (R8TD)
Transmit 8B/10B Encoder (T8TE)
LVDS Transmit Transmitt Serializer (PISO) (TXLV)
TP[1] TN[1]
RP[31] RN[31]
LVDS Receiver (RXLV)
Data Recovery Unit (DRU)
Receive 8B/10B Decoder (R8TD)
In-Band Link Controller (ILC)
In-Band Link Controller (ILC)
Transmit 8B/10B Encoder (T8TE)
LVDS Transmit Transmitt Serializer (PISO) (TXLV)
TP[31] TN[31]
Crossbar Switch (DCB) Clock Synthesis Units RC1FP SYSCLK
Microprocessor Interface
JTAG
A[11:0]
D[31:0]
INTB
TRSTB
RSTB
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Description
PM8620 NSE-20G monolithic CMOS integrated circuits packaged ball UBGAs that performs above granularity space switching full duplex SBI336 streams carried SBI336Sin 8b/10b coding over LVDS 777.6Mb/s. NSEs also perform VT1.5/VT2 above granularity switching full duplex STS-12/STM-4 SONET/SDH streams, carried Serial TelecomBus signals 8b/10b coding over LVDS 777.6Mb/s. NSE-20G typically used with PM8610 PM8611 SBSLITE devices provide Memory-Space-Memory switching systems. each supports either four buses 19.44MHz SBI336 77.76MHz, overall system supports mixture SBI336 byte serial buses, ranging from 19.44MHz buses SBI336 77.76MHz buses which does exceed aggregate bandwidth STS-384, about 20Gb/s. TelecomBus mode devices support same range flexibility 19.44MHz 77.76MHz TelecomBuses VT1.5/VT2 granularity Central cross switch, NSE-20G. Every clock cycle cross switches byte data with control signals from each input port output port. byte data channel from T1/E1 byte column comprising DS3, VT1.5, STS-1. order switching take place input output streams must synchronized. This done RC1FP input signal. When switching T1s, E1s, other higher order units only SBI336 multi-frame alignment required. same applies TelecomBus mode where only frame alignment required. in-band control link over serial LVDS interface allows communicate with microprocessors attached SBS, SBSLITE other serial SBI336 devices. effective bandwidth each in-band link each device 8Mb/s. in-band link provides error detection byte user messages some near realtime control signals between devices. Using near realtime control signals able synchronize page switching, indicate switchover between working protected links exchange three user defined signals (software) Auxiliary signals (software). User Auxiliary signals used indicate events such interrupt handshaking between point microprocessors. message format left user devices. only constraint that each message maximum length bytes.
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Ball Diagram
NSE-20G packaged 35mm 35mm ball UBGAs.
Figure UBGA-480 Ball Diagram (Bottom-View)
Upper Left Corner
VDDO
RESERV
RESERV
RESERV
VDDI
AVDH
VDDO
VDDO
VDDO
VDDI
VDDI
RESERV
RESERV
RESERV
RESERV
RESERV
RESERV
RSTB
AVDH
AVDH
VDDO
VDDI
RESERV
VDDI
RESERV
VDDI
RESERV
RESERV
RESERV
RESERV
VDDI
AVDH
AVDH
AVDH
VDDO
VDDI
VDDO
RESERV
VDDO
RESERV
RESERV
RESERV
VDDO
VDDI
RESK1
RES1
RN[31]
RP[31]
RN[30]
RP[30]
AVDL
RN[29]
RP[29]
RN[28]
RP[28]
TP[31]
TN[31]
AVDH
TP[30]
TN[30]
TP[29]
TN[29]
TP[28]
TN[28]
VDDI
RN[27]
RP[27]
RN[26]
RP[26]
RN[25]
RP[25]
AVDH
VDDI
AVDL
RN[24]
RP[24]
TP[27]
TN[27]
VDDI
TP[26]
TN[26]
TP[25]
TN[25]
TP[24]
TN[24]
CSU_AVD CSU_AVD
RN[23]
RP[23]
CSU_AVD CSU_AVD
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Upper Right Corner
SYSCLK
RESERV
RESERV
VDDI
RESERV
RESERV
RESERV
RESERV
RESERV
VDDO
VDDO
VDDO
TC1FP
VDDI
VDDI
RESERV
RESERV
RESERV
RESERV
VDDI
VDDO
VDDO
AVDH
RC1FP
VDDI
TRSTB
VDDI
VDDO
VDDI
RESERV
VDDO
RESERV
RESERV
VDDO
AVDH
AVDH
AVDH
ATB0[1]
AVDH
AVDH
ATB1[1]
TN[0]
TP[0]
TN[2]
TP[2]
TN[1]
TP[1]
AVDH
VDDI
RP[0]
RN[0]
TN[3]
TP[3]
VDDI
RP[1]
RN[1]
VDDI
AVDL
RP[2]
RN[2]
AVDH
RP[3]
RN[3]
TN[5]
TP[5]
TN[4]
TP[4]
VDDI
TN[6]
TP[6]
RP[4]
RN[4]
TN[7]
TP[7]
AVDH
VDDI
AVDL
RP[6]
RN[6]
RP[5]
RN[5]
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Lower Left Corner
RN[21] RP[21] RN[22] RP[22]
AVDL
VDDI
AVDH
TP[23]
TN[23]
RN[20]
RP[20]
TP[22]
TN[22]
VDDI
TP[20]
TN[20]
TP[21]
TN[21]
RN[19]
RP[19]
AVDH
RN[18]
RP[18]
AVDL
VDDI
RN[17]
RP[17]
VDDI
TP[19]
TN[19]
RN[16]
RP[16]
VDDI
AVDH
TP[17]
TN[17]
TP[18]
TN[18]
TP[16]
TN[16]
ATB1[2]
AVDH
AVDH
ATB0[2]
AVDH
AVDH
AVDH
VDDO
VDDI
VDDO
A[6]
A[2]
VDDI
VDDO
D[27]
VDDI
VDDI
AVDH
VDDO
VDDO
VDDI
A[9]
A[5]
A[3]
D[31]
D[29]
VDDI
D[25]
VDDI
D[21]
D[20]
VDDO
VDDO
VDDO
INTB
A[10]
A[7]
A[4]
A[0]
D[30]
D[28]
D[26]
D[22]
D[19]
A[11]
A[8]
A[1]
D[24]
D[23]
D[18]
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Lower Right Corner
CSU_AVD CSU_AVD RP[7] RN[7]
CSU_AVD CSU_AVD TN[8]
TP[8]
TN[9]
TP[9]
TN[10]
TP[10]
VDDI
TN[11]
TP[11]
RP[8]
RN[8]
AVDL
VDDI
AVDH
RP[9]
RN[9]
RP[10]
RN[10]
RP[11]
RN[11]
VDDI
TN[12]
TP[12]
TP[13]
TN[13]
TN[14]
TP[14]
AVDH
TN[15]
TP[15]
RP[12]
RN[12]
RP[13]
RN[13]
AVDL
RP[14]
RN[14]
RP[15]
RN[15]
RES2
RESK2
D[17]
VDDO
D[13]
D[11]
D[8]
VDDO
D[5]
D[3]
D[0]
VDDO
VDDO
AVDH
AVDH
AVDH
VDDI
D[15]
VDDI
D[10]
D[9]
D[7]
D[2]
D[1]
VDDO
AVDH
AVDH
D[16]
D[14]
D[12]
VDDI
D[6]
D[4]
VDDI
VDDO
VDDO
VDDO
AVDH
VDDI
VDDI
VDDO
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Description
Table Descriptions Name LVDS Ports (128 Balls)
RP[0] RN[0] RP[1] RN[1] RP[2] RN[2] RP[3] RN[3] RP[4] RN[4] RP[5] RN[5] RP[6] RN[6] RP[7] RN[7] RP[8] RN[8] RP[9] RN[9] RP[10] RN[10] RP[11] RN[11] RP[12] RN[12] RP[13] RN[13] RP[14] RN[14] RP[15] RN[15] RP[16] RN[16] RP[17] RN[17] RP[18] RN[18] RP[19] RN[19] RP[20] RN[20] RP[21] RN[21] RP[22] RN[22] RP[23] RN[23] RP[24] RN[24] RP[25] Analog LVDS Input AF31 AF32 AE32 AE33 AD33 AD34 AC32 AC33 Receive Serial Data. differential receive serial data links (RP[31:0]/RN[31:0]) carry receive SBI336S SONET/SDH STS-12 frame data from upstream sources serial format. Each differential pair RP[X]/RN[X] carries constituent SBI336 STS-12 stream. Data RP[X]/RN[X] encoded 8B/10B format extended from IEEE Std. 802.3. 8B/10B character transmitted first transmitted last. RP[X]/RN[X] differential pairs must frequency locked phase aligned (within certain tolerance) each other. RP[31:0]/RN[31:0] nominally 777.6 Mbps data streams. Unused RP[X]/RN[X] pairs left floating, grounded. either case analog blocks (RXLV DRU) disabled reduce power consumption. Tying high corresponding input pair will apply voltage across internal termination resistor, which will increase system power consumption.
Type
Function
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Name
RN[25] RP[26] RN[26] RP[27] RN[27] RP[28] RN[28] RP[29] RN[29] RP[30] RN[30] RP[31] RN[31] TP[0] TN[0] TP[1] TN[1] TP[2] TN[2] TP[3] TN[3] TP[4] TN[4] TP[5] TN[5] TP[6] TN[6] TP[7] TN[7] TP[8] TN[8] TP[9] TN[9] TP[10] TN[10] TP[11] TN[11] TP[12] TN[12] TP[13] TN[13] TP[14] TN[14] TP[15] TN[15] TP[16] TN[16] TP[17] TN[17] TP[18] TN[18] TP[19] TN[19] TP[20] TN[20] TP[21] TN[21] TP[22]
Type
Function
Analog LVDS Output
AJ33 AJ32 AH34 AH33 AH32 AH31 AF34 AF33 AB34 AB33 AB32 AB31 AA33
Transmit Serial Data. differential transmit working serial data links (TP[31:0]/TN[31:0]) carry transmit SBI336S SONET/SDH STS-12 frame data downstream sinks serial format. Each differential pair carries constituent STS-12 stream. Data TP[X]/TN[X] encoded 8B/10B format extended from IEEE Std. 802.3. 8B/10B character transmitted first transmitted last. TP[X]/TN[X] differential pairs frequency locked phase aligned (within certain tolerance) each other. TP[31:0]/TN[31:0] nominally 777.6 Mbps data streams. Unused TP[X]/TN[X] pairs should left floating
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Name
TN[22] TP[23] TN[23] TP[24] TN[24] TP[25] TN[25] TP[26] TN[26] TP[27] TN[27] TP[28] TN[28] TP[29] TN[29] TP[30] TN[30] TP[31] TN[31] SYSCLK
Type
AA32
Function
NSE-20G Control Clocking Balls)
Input System Clock. system clock signal (SYSCLK) master clock NSE20G device. SYSCLK must 77.76 clock, with nominal duty cycle. RC1FP sampled rising edge SYSCLK. RC1FP Input Receive Serial Interface Frame Pulse. receive serial interface frame pulse signal (RC1FP) provides system timing receive serial interface. RC1FP supplied common devices system containing more NSE-20G devices. TelecomBus mode RC1FP high once every frames, mode without switching, when switching DS0s (WITHOUT CAS) RC1FP also high once every frames, multiple thereof. When mode switching DS0s WITH RC1FP indicates signaling multi-frame alignment pulsing once every frames multiples thereof. software configurable delay from RC1FP used indicate that multi-frame boundary 8B/10B characters have been delivered receive serial data links (RP[31:0]/RN[31:0]) ready processing time-space-time switching elements. RC1FP sampled rising edge SYSCLK. Reserved Output Input Factory test pin, must left floating Connection Memory Page. connection memory page select signal (CMP) controls selection connection memory page NSE. When high, connection
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Name
Type
Function
memory page selected. When low, connection memory page selected. Changes connection memory page selection synchronized boundary next C1FP frame multi-frame depending mode: 4-Frame SBI/SBI336 mode: sampled byte position incoming first frame fourframe multi-frame. Changes connection memory page selection synchronized frame boundary byte position) next four-frame multi-frame. 48-Frame SBI/SBI336 mode: sampled byte position incoming first frame 48-frame multi-frame. Changes connection memory page selection synchronized frame boundary byte position) next 48-frame multi-frame. TelecomBus mode: sampled byte position every frame incoming bus. Changes connection memory page selection synchronized frame boundary byte position) next frame. sampled rising edge SYSCLK RC1FP frame position.
RSTB
Input
Reset Enable Bar. active reset signal (RSTB) provides asynchronous reset NSE. RSTB Schmitt triggered input with integral pull-up resistor. Chip Select Bar. active chip select signal (CSB) controls microprocessor access registers NSE-20G device. during NSE-20G Microprocessor Interface Port register accesses. high disable microprocessor accesses. required (i.e. register accesses controlled using signals only), should connected inverted version RSTB input.
Microprocessor Interface Balls)
Input AM30
Input
AM29
Read Enable Bar. active read enable signal (RDB) controls microprocessor read accesses registers NSE-20G device. also during NSE-20G Microprocessor Interface Port register read accesses. NSE-20G drives D[31:0] with contents addressed register while low. Write Enable Bar. active write enable
Input
AN29
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Name
Type
Function
signal (WRB) controls microprocessor write accesses registers NSE-20G device. also during NSE-20G Microprocessor Interface Port register write accesses. contents D[31:0] clocked into addressed register rising edge while low.
D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A{0]
AM24 AN23 AM23 AN22 AL22 AN21 AM21 AP20 AP19 AN19 AM19 AM18 AN18 AP18 AL17 AN17 AM16 AN16 AL15 AN15 AL14 AM14 AM13 AL13 AM12 AN12 AL11 AN11 AL10 AM10 AP28 AN27 AM27 AP26 AN26 AL26 AM26 AN25 AM25 AL25 AP24 AN24 AL30
Microprocessor Data Bus. bi-directional data bus, D[31:0] used during NSE-20G Microprocessor Interface Port register reads write accesses. D[31] most significant data words D[0] least significant bit.
Input
Microprocessor Address Bus. microprocessor address (A[11:0]) selects specific Microprocessor Interface Port registers during NSE-20G register accesses.
Input
Address Latch Enable. address latch enable signal (ALE) active high latches address (A[11:0]) when low. internal address latches transparent when high. allows NSE20G interface multiplexed address/data
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Name
INTB
Type
Open Drain Output
AN30
Function
bus. integral pull resistor. Interrupt Request Bar. active interrupt enable signal (INTB) output goes when NSE-20G interrupt source active that source unmasked. INTB returns high when interrupt acknowledged appropriate register access. INTB open drain output. Test Clock. JTAG test clock signal (TCK) provides timing test operations that carried using IEEE P1149.1 test access port. Test Mode Select. JTAG test mode select signal (TMS) controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull-up resistor. Test Data Input. JTAG test data input signal (TDI) carries test data into NSE-20G IEEE P1149.1 test access port. sampled rising edge TCK. integral pull-up resistor. Test Data Output. JTAG test data output signal (TDO) carries test data NSE20G IEEE P1149.1 test access port. updated falling edge TCK. tri-state output which inactive except when scanning data progress. Test Reset Bar. active JTAG test reset signal (TRSTB) provides asynchronous NSE-20G test access port reset IEEE P1149.1 test access port. TRSTB Schmitt triggered input with integral pull-up resistor. Note that when TRSTB being used, must connected RSTB input.
JTAG Port Balls)
Input
Input
Input
Tri-state
TRSTB
Input
Reserved Balls)
RESERVED Input These pins RESERVED. Must left floating.
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Name
Type
Function
RESERVED
Input
This RESERVED must tied normal operation. Reference Resistor Connection. off-chip 3.16kW resistor connected between these positive resistor reference Kelvin ground contact RESK. onchip negative feedback path will force 0.8V VREF voltage onto RES, therefore forcing 252µA current flow through resistor. Reference Resistor Connection. off-chip 3.16kW resistor connected between these positive resistor reference Kelvin ground contact RESK. onchip negative feedback path will force 0.8V VREF voltage onto RES, therefore forcing 252µA current flow through resistor. Analog test validation testing. Should tied normal operation. Analog test validation testing. Should tied normal operation. digital core power pins (VDDI[44:0]) should connected well-decoupled +1.8 supply.
External Resistors Balls)
RES[2] RES[1] Analog Input
RESK[2] RESK[1]
Analog Input
Analog Test Balls)
ATB0[2] ATB0[1] ATB1[2] ATB1[1] VDDI[44:0] Analog Analog AK32 AJ31 AN10 AN13 AP13 AP15 AM15 AM17 AL18 AM20 AL21
Digital Core Power Balls)
Power
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Name
Type
AM22 AL24 AM28 AL28 AG32 AE31 AD31 AA31
Function
Digital Power Balls)
VDDO[33:0] Power AL12 AL16 AL23 AL27 AL31 AM31 AM32 AN31 AN32 AN33 digital power pins (VDDO[33:0]) should connected well-decoupled +3.3 supply.
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Name
Type
Function
Digital Ground Balls)
[72:0] Ground AP10 AP12 AP14 AP16 AP21 AP23 AP25 AP27 AP29 AP31 AP32 AP33 AP34 digital ground pins (VSS [72:0]) should connected GND.
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Name
Type
AA34 AC34 AE34 AG34 AJ34 AL34 AM34 AN34
Function
Analog Power Balls)
AVDL[7:0] Power AD32 These balls should connected welldecoupled +1.8 supply. These balls supply RXLVs.
Clock Synthesis 1.8V Power Balls)
CSU_AVDL[5:0] Power These balls should connected welldecoupled +1.8 supply. These balls supply CSUs.
Clock Synthesis 3.3V Power Balls)
CSU_AVDH[1:0] Power These balls should connected welldecoupled +3.3 supply. analog power pins (AVDH[33:0]) should connected well-decoupled +3.3 supply.
Analog Power Balls)
AVDH[33:0] Power
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Name
Type
AG31 AC31 AK31 AK33 AK34 AL32 AL33 AM33
Function
Connect Balls)
NC[49:0] AG33 AP30 AL29 AN28 AP22 AN20 AL20 AL19 AP17 AN14 AM11 AP11 Connect pins (NC[49:0]) should left floating.
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Name
Type
Function
TOTAL Notes Description:
NSE-20G inputs bi-directional balls except LVDS links present minimum capacitive loading operate logic levels. Inputs RSTB, ALE, TMS, TRSTB have internal pull-up resistors. outputs have minimum drive capability this includes TDO, INTB D[31:0]). VDDI AVDL power pins internally connected each other. Failure connect these pins externally cause malfunction damage device. AVDH, CSU_AVDH VDDO power pins internally connected each other. Failure connect these pins externally cause malfunction damage device. VDDI, VDDO, AVDH, CSU_AVDH AVDL power pins share common ground VSS. details power-up power-down VDDI, VDDO, AVDH, CSU_AVDH AVDL power pins, Section 15.1 Power Sequencing. details analog power filtering recommendations, please Section 15.2 Analog Power Filtering Recommendations
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Functional Description
LVDS Overview
LVDS family cells allow implementation 777.6 Mb/s LVDS links. reference clock 77.76MHz required. generic LVDS link according IEEE 1596.3-1996 illustrated Figure below. transmitter drives differential signal through pair characteristic interconnects, such board traces, backplane traces, short lengths cable. receiver presents 100W differential termination impedance terminate lines. Included standard sufficient common-mode range receiver accommodate much 925mV common-mode ground difference.
Figure Generic LVDS Link Block Diagram
Transmitter
Interconnect Zo=50
Receiver
Zo=50
Complete SERDES transceiver functionality provided. Ten-bit parallel data sampled line rate divided-by-10 clock (77.76MHz SYSCLK) then serialized line rate LVDS output pins 777.6MHz clock synthesized from SYSCLK. Serial line rate LVDS data sampled de-serialized 10-bit parallel data. Parallel output transfers synchronized gated line rate divided-by-10 clock. 10-bit data passed 8B/10B decoding block. gating duty cycle adjusted such that throughput parallel interface equals receive input data rate (Line Rate 100ppm). expected that clock source transmitter same clock source receiver ensure data throughput both ends link identical. Data guaranteed contain sufficient transition density allow reliable operation data recovery units 8B/10B block coding decoding provided T8TE R8TD blocks. system level, reliable operation will obtained proper signal integrity maintained through signal path receiver requirements respected. Namely, worst case opening 0.7UI 100mV differential amplitude needed. These conditions should achievable with system architecture consisting board traces, sets backplane connectors, backplane interconnect. This assumes proper design 100W differential lines minimization discontinuities signal path. power constraints, output differential amplitude approximately 350mV
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LVDS system comprised LVDS Receiver (RXLV), LVDS Transmitter (TXLV), Transmitter reference (TXREF), data recovery unit (DRU), parallel serial converter (PISO Clock Synthesis Unit (CSU).
9.1.1
LVDS Receiver (RXLV) RXLV block 777.6 Mb/s Voltage Differential Signaling (LVDS) Receiver according IEEE 1596.3-1996 LVDS Specification. RXLV block receiver Figure accepting 777.6 Mb/s LVDS signals from transmitter, over RP[X]/RN[X] pins, amplifying them converting them digital signals, then passing them data recovery unit (DRU). Holding IEEE 1596.3-1996 specification, RXLV differential input sensitivity better than 100mV, includes least 25mV hysteresis. There instances RXLV block NSE-20G.
9.1.2
LVDS Transmitter (TXLV) TXLV block 777.6 Mb/s Voltage Differential Signaling (LVDS) Transmitter according IEEE 1596.3-1996 LVDS Specification. TXLV accepts 777.6 Mb/s differential data from "parallel-in, serial-out" (PISO) circuit then transmits data off-chip voltage differential signal TP[X]/TN[X] pins. TXLV uses reference current voltage from TXREF block control output differential voltage amplitude output common-mode voltage. There instances TXLV block NSE-20G.
9.1.3
LVDS Transmit Reference (TXREF) TXREF provides on-chip bandgap voltage reference (1.20V ±5%) precision current TXLV (777.6 Mb/s LVDS Transmitter) block's. reference voltage used control common-mode level TXLV output, while reference current used control output amplitude. precision currents generated forcing reference voltage across external, offchip 3.16KW(±1%) resistor. resulting current then mirrored through several individual reference current outputs, each TXLV receives reference current. There instances TXREF NSE-20G.
9.1.4
Data Recovery Unit (DRU) fully integrated data recovery serial parallel converter that used 777.6 Mb/s data. 8B/10B block code used guarantee transition density optimal performance.
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recovers data outputs ten-bit word synchronized with line rate divided ten, gated clock allow frequency deviations between data source local oscillator. output clock recovered clock. accumulates data bits outputs them next clock edge. 10-bits available transfer given clock cycle, output clock gated. provides moderate high frequency jitter tolerance suitable inter-chip serial link applications. support frequency deviations ±100ppm. There instances NSE-20G.
9.1.5
Parallel Serial Converter (PISO) PISO parallel-to-serial converter designed high-speed transmit operation, supporting 777.6 Mb/s. There instances PISO NSE-20G.
9.1.6
Clock Synthesis Unit (CSU) fully integrated clock synthesis unit. generates jitter multi-phase differential clocks 777.6 transmitter. There instances NSE-20G. ensure proper operation CSUs, they must reset minimum 1ms. This accomplished setting ARESET register 000H 1ms.
Receive 8B/10B Frame Aligner (R8TD)
Receive 8B/10B SBI336S frame aligner, R8TD, frames receive stream find 8B/10B character boundaries. also contains FIFO bridge between timing domain receive LVDS links system clock timing domain. R8TD blocks perform framing elastic store functions data retrieved from receive LVDS links, RP[x]/RN[x].
9.2.1
FIFO Buffer FIFO buffer sub-block provides isolation between timing domains associated receive LVDS link that system clock, SYSCLK. Data with arbitrary alignment 8B/10B characters, written into 10-bit 24-word deep FIFO link clock rate. Data read from FIFO every SYSCLK cycle.
Transmit 8B/10B Encoder (T8TE)
Transmit 8B/10B Encoder blocks, T8TE, construct 8B/10B character stream from incoming translated SBI336 TelecomBus carrying STS-12/STM-4 equivalent channelized stream. T8TE block corrects running disparity 8B/10B character stream buffers data FIFO before transmission transmit serializer block. total T8TE blocks instantiated NSE-20G device.
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mode, these blocks encode SBI336S stream shown Table When configured Synchronous mode switching, 8B/10B encoder transmits signaling multiframe alignment across SBI336S interface generating C1FP character every frame times. When configured switching C1FP character sent every frames.
9.3.1
SBI336S 8B/10B Character Encoding Table shows mapping SBI336S control bytes signals into 8B/10B control characters. linkrate octet location in-band programming channel, octet when contains data carried data. Justification requests master timing carried character there three characters used, nominal, negative timing adjustment request, positive timing adjustment request.
Table SBI336S Character Encoding Code Group Name
K28.5 K23.7-
Curr. RDabcdei fghj
001111 1010 111010 1000
Curr. abcdei fghj
110000 0101
Encoded Signals Description
IC1FP='b1 C1FP frame multi-frame alignment Overhead Bytes (columns 1-60 1-72 except in-band programming channel), byte except during negative justification, byte after byte during positive justification, unused bytes fraction rate links byte, justification request byte, negative justification request byte, positive justification request byte byte, justification request byte, negative justification request* byte, positive justification request* byte, send extra byte request** byte, send less byte request** byte IV5=1, IDATA[0,4] ERDI[1:0] `b00, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b00, IDATA[5]
Common Link Types
Asynchronous T1/E1 Links
1000 001111 1000 101110 1000 110110 1000 110110 1000 001111 1000 101110 1000 001111 1000 101110 1000 110110 1000
Synchronous T1/E1 Links Asynchronous DS3/E3 Links
Fractional Rate Links
Floating Transparent Virtual Tributaries
K27.7+
001001 0111
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Code Group Name
K28.7-
Curr. RDabcdei fghj
001111 1000
Curr. abcdei fghj
Encoded Signals Description
byte IV5=1, IDATA[0,4] ERDI[1:0] `b01, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b01, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b10, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b10, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b11, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b11, IDATA[5]
K28.7+
110000 0111
K29.7-
101110 1000
K29.7+
010001 0111
K30.7-
011110 1000
K30.7+
100001 0111
Note there multiple frame when mode only justification occur frame. Positive negative justification request through required SBI336S interface should limited frame. Note fractional rate links symmetric transmit receive direction over SBI336S. When using clock slave mode with fractional rate link clock master makes single byte adjustments slaves rate once frame.
9.3.2
Serial TelecomBus 8B/10B Character Encoding Table shows mapping TelecomBus control bytes signals into 8B/10B control characters. When TelecomBus control signals conflict each other, 8B/10B control characters generated according sequence table, with characters table taking precedence over those lower table.
Table Serial TelecomBus Character Encoding Code Group Name
K28.5
Curr. RDabcdei fghj
001111 1010
Curr. abcdei fghj
110000 0101
Encoded Signals Description
IC1FP IPL= C1FP frame multi-frame alignment
Multiplex Section Termination (MST) Level
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Code Group Name
K28.5
Curr. RDabcdei fghj
001111 1010
Curr. abcdei fghj
110000 0101
Encoded Signals Description
IC1FP='b1 IPL='b0 C1FP frame multi-frame alignment IPL='b0 High-order path byte position, negative justification event.
High Order Path Termination (HPT) Mode
K28.0-
001111 0100
K28.0+
110000 1011
IPL='b0 High-order path byte position, positive justification event.
K28.6
001111 0110
110000 1001
IC1FP='b1, IPL='b1 High-order path frame alignment (J1).
Order Path Termination (LPT) Mode
K28.4+ K27.7110110 1000 110000 1101 ITAIS='b1 Low-order path AIS. IV5='b1, IDATA[0,4] ERDI[1:0] `b00, IDATA[5] order path frame alignment. ERDI encoded byte. K27.7+ 001001 0111 IV5='b1, IDATA[0,4] ERDI[1:0] `b00, IDATA[5] order path frame alignment. ERDI encoded byte. K28.7001111 1000 IV5='b1, IDATA[0,4] ERDI[1:0] `b01, IDATA[5] order path frame alignment. ERDI encoded byte. K28.7+ 110000 0111 IV5='b1, IDATA[0,4] ERDI[1:0] `b01, IDATA[5] order path frame alignment. ERDI encoded byte. K29.7101110 1000 IV5='b1, IDATA[0,4] ERDI[1:0] `b10, IDATA[5] order path frame alignment. ERDI encoded byte. K29.7+ 010001 0111 IV5='b1, IDATA[0,4] ERDI[1:0] `b10, IDATA[5] order path frame alignment. ERDI encoded byte. K30.7011110 1000 IV5='b1,
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Code Group Name
Curr. RDabcdei fghj
Curr. abcdei fghj
Encoded Signals Description
IDATA[0,4] ERDI[1:0] `b11, IDATA[5] order path frame alignment. ERDI encoded byte.
K30.7+
100001 0111
IV5='b1, IDATA[0,4] ERDI[1:0] `b11, IDATA[5] order path frame alignment. ERDI encoded byte.
K23.7-
111010 1000
000101 0111
ITPL='b0 low-order path payload bytes.
9.3.3
Serial SBI336 TelecomBus Alignment alignment functionality preformed each receiver broken down into parts, character alignment frame alignment. Character alignment finds 8B/10B character boundary arbitrarily aligned incoming data. Frame alignment finds SBI336S TelecomBus frame multi-frame boundaries within Serial link. character frame alignment expected robust enough operation over cabled interconnect.
9.3.4
Character Alignment Block Character alignment locates character boundaries incoming 8B/10B data stream. character alignment algorithm states, in-character-alignment state outof-character-alignment state. states character alignment algorithm shown Figure When character alignment state machine out-of-character-alignment state, maintains current alignment, while searching C1FP character. finds C1FP character will re-align C1FP character move in-character-alignment state. C1FP character found searching 8B/10B C1FP character, K28.5+ K28.5-, simultaneously possible locations. While in-character-alignment state, state machine monitors LCVs. more LCVs detected within character window character alignment state machine transitions out-of-character-alignment state. special characters listed Table Table ignored purposes. Upon return incharacter-alignment state count cleared.
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Figure Character Alignment State Machine
5-in-15 LCVs
out-ofcharacteralignment
incharacteralignment
Found C1FP Character
9.3.5
Frame Alignment Frame alignment locates TelecomBus frame multi-frame boundaries incoming 8B/10B data stream. frame alignment state machine states, in-framealignment state out-of-frame-alignment state. Each SBI336S frame 125uS duration. mode: Encoded over SBI336S frame alignment SBI336S multi-frame alignment which every four SBI336S frames 500uS. When carrying traffic synchronous mode, signaling multi-frame alignment also necessary also encoded over SBI336S alignment. Signaling multi-frame alignment every frames links every frames links, therefore signaling multi-frame alignment covering both multi-frame alignment every SBI336S frames 6ms. Therefore C1FP characters sent every four every frames. TelecomBus mode: Encoded over serial link tributary multi-frame alignment which every frames 500uS. Multi-frame alignment required that downstream device extract data from tributary. multi-frame information preserved only sending C1FP characters every four frames. frame alignment state machine establishes frame alignment over link based frame multi-frame alignments. When frame alignment state machine out-of-frame-alignment state, maintains current alignment, while searching C1FP character. When finds C1FP character state machine transitions in-framealignment state. While in-frame-alignment state state machine monitors out-of-place C1FP characters. Out-of-place C1FP characters identified maintaining frame counter based C1FP character. counter initialized C1FP character when outof-character-alignment state, unaffected in-character-alignment state. consecutive C1FPs have been found that agree with expected location defined frame counter, state will change out-of-frame-alignment state.
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frame alignment state machine also sensitive character alignment. When character alignment state machine out-of-character-alignment state, frame alignment state machine forced out-of-alignment, held that state until character alignment state machine transitions in-character alignment state.
Figure Frame Alignment State Machine
consecutive out-of-place C1FPs out-of-character alignment
out-offramealignment
in-framealignment
Found C1FP (out-of-character alignment)
9.3.6
SBI336S Multi-frame Alignment SBI336S multi-frame alignment communicated across link controlling frequency C1FP character. most frequent transmission C1FP character every four SBI336S frame times. This SBI336S multi-frame used when there synchronous tributaries requiring signaling multi-frame alignment SBI336S bus. When there synchronous tributaries SBI336S C1FP character transmitted every frame times. This signaling multi-frame lowest common multiple frame multi-frame frame multi-frame. SBI336S multi-frame signaling multi-frame alignment based free running multiframe counter that reset with each C1FP character received. Under normal operating conditions each received C1FP character will coincide with free running multi-frame counter. SBI336S multi-frame alignment always required, SBI336S signaling multi-frame alignment optional only required when synchronous tributaries supported with level switching.
Cross switch (DCB)
Each R8TD blocks provides eight-bit data signal each 77.76MHz clock edge. These signals STS-12 frame aligned ingress octets. Likewise, each egress T8TE blocks expects receive STS-12 frame aligned signal each clock edge. Cross switch (DCB) connects these inputs these outputs.
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constitutes Space switch that connects each output some input during each clock period STS-12 frame structure. STS-12 frame structure consists 12*9*90 9720 octets overheads payload). Being granularity space switch, must provide separate switch settings each these 9720 octet times. These 9720 switch settings stored on-chip SRAM. Each thirty-two egress ports must told which each thirty-two ingress ports should read during each 9720 clock periods. Five bits required specify which ingress port should read each output. Thus, require 9720 words five bits each thirty-two egress ports. Thus each clock period requires 32*5 bits. support controlled switchover from switch settings another, require banks 9720 words each. aggregate memory requirement 9720 160b 3,110,400b SRAM. table below illustrates mapping this memory. Each control page table vector bits containing five bits (specifying source port) each egress ports. page will on-line translating ports core switch while other offline update. When configuration ready, appropriate system synchronized frame boundary arrives, pages will swapped.
Table Switching control layout Control Page
Address
Control Page
1078 1079 1080 1081
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Control Page
Control Page
9718 9719
multiplexers that select inputs each egress port straight forward 32-to-1 multiplexers. They require five bits control during each 77.76MHz clock cycle. Their outputs T8TEs. This design permits unicast, multicast, broadcast.
Clock Synthesis Transmit Reference Digital Wrapper (CSTR)
CSTR contains configuration registers TXREF LVDS analog locks.
Fabric Latency
flow octets from ingress LVDS egress LVDS variable latency, depending timing arriving LVDS stream, clock variation egress LVDS drivers. reasonable estimate NSE's latency arrived making assumptions about depths receive transmit FIFOs: assume "C1" timing maintain about samples ingress FIFO; egress FIFO designed centered samples typically delay FIFOs will clock cycles. latency through space switch stage three clock cycles. Data latency through analog blocks around typical latency NSE-20G clock cycles 308ns. With worst case conditions both FIFOs, latency rises clock cycles 463ns.
JTAG Support
NSE-20G provides JTAG support testing device interconnection board.
Microprocessor Interface
Microprocessor Interface Block provides logic required interface normal mode test mode registers within NSE-20G generic microprocessor bus. normal mode registers used during normal operation configure monitor NSE. register accessed shown Register Memory table below. Addresses that shown used must treated Reserved.
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In-band Link Controller (ILC)
order permit centralized control distributed NSE/SBS/SBSLITE fabrics from microprocessor interface (for applications which NSEs located fabric cards, SBSs located multiple line cards), in-band signaling channel provided between over SBI336S interface. Each control SBSs that attached LVDS links. NSE-SBS in-band channel full duplex, NSE-20G active control link. in-band channel carried first columns four rows structure, rows overall in-band channel capacity thus 36*4*64kb/s 9.216Mb/s. Each bytes allocated in-band signaling channel in-band message between points. Four bytes each 36-byte, in-band message reserved end-to-end control information error protection, leaving 8.192Mb/s available data transfer between points. data transferred between points fixed format, effectively providing clear channel packet transfer between attached microprocessors each LVDS link terminating devices. user able send receive packet bytes length. last reserved bytes byte in-band message CRC-16 which detects errors message. This block provides microprocessor interface in-band signaling channel. This in-band channel expected used almost entirely carry switching control changes SBSs. configure device most often requires local microprocessor write memory location consisting 16-bit address 16-bit data. Using this baseline assuming efficient in-band channel bandwidth maximum (32bytes/row rows/frame 8000 frames/sec bytes/write) 256,000 configurations second. Considering that configuring when switching DS0s requires writes indicates that in-band signaling channel bandwidth sets maximum limit over 9000 configurations second. real life these limits will achieved this shows that in-band link should bottleneck. TelecomBus mode this same configuration will require only writes link. Another more efficient communication scheme could used increase this performance. protected architectures likely that full configuration port card will necessary during switchover. This would require entire connection memory reconfigured. Assuming connections overhead bytes also reconfigured, fastest that complete reconfiguration take place 9720 register writes each configuration pages SBS. This equates 9720 writes bytes/write bytes/row rows/frame 8000 frames/second)) milliseconds. also possible that spare card could hold connection configurations port cards protecting locally, even faster switch over.
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9.9.1
In-Band Signaling Channel Fixed Overhead In-Band Link Controller block generates terminates bytes fixed header CRC-16 every byte in-band message (total bytes). byte header provides control status between devices ends LVDS link. CRC-16 calculated over byte (and header bytes) in-band message provides terminating ability detect errors in-band message. format in-band message header bytes shown Figure Figure
Figure In-Band Signaling Channel Message Format
byte Header1 byte Header2 bytes Free Format Information bytes CRC-16
Figure In-Band Signaling Channel Header Format Header1
VALID LINK[1:0] Bit4 PAGE[1:0] Bit3 Bit2 USER[2:0] Bit1
Header2
AUX[7:0] Bit4 Bit3 Bit2 Bit1
Table In-band Message Header Fields Field Name
Valid
SBS/SBSLITE
Message slot contains message(1) empty(0). empty this message will into Message FIFO (other header information processed usual) These bits optional SBI336S devices, intended devices which have multiple redundant links. Each either indicates which Link use, Working(0) Protect(1) when sourced from master device, which link being used, when sourced from slave device. Other algorithms possible indicate Working Protect over these bits SBI336S devices must able revert back this meaning. Transmitted immediately. Each indicates which control page use, page bits, ingress egress MSU. Only transmitted from beginning first message frame
SBS/SBSLITE
Message slot contains message(1) empty(0). empty this message will into Message FIFO (other header information processed usual) These bits optional SBI336S devices, intended devices which have multiple redundant links. Each either indicates which Link use, Working(0) Protect(1) when sourced from master device, which link being used, when sourced from slave device. Other algorithms possible indicate Working Protect over these bits SBI336S devices must able revert back this meaning. Transmitted immediately. Each shows current control page use, page bits, ingress egress MSU. Only transmitted from beginning first message frame.
Link[1:0]#
Page[1:0]#
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Field Name
User[2:0]#
SBS/SBSLITE
User defined register indication reflected external hardware signal outputs. Transmitted immediately. User defined auxiliary register indication SBS. Transmitted immediately.
SBS/SBSLITE
User defined register indication from external hardware inputs SBS. Transmitted immediately. User defined auxiliary register indication NSE. Transmitted immediately.
Aux[7:0]#
Change these bits (received side) will processed received message CRC-16 indicates error. Interrupts generated when errors detected USER LINK bits change state. There inherent flow control provided In-Band Link Controller. attached microprocessor able provide flow control interrupts when in-band message FIFO overflows USER Auxiliary bits header. each message arrives, CRC-16 valid checked; valid message discarded, fails check flagged being error interrupt generated enabled. CRC-16 regardless valid bit, Page Link, User bits passed immediately. FIFO erroneously overflows, interrupt generated.
9.10 Microprocessor Interface
following register shows registers used provide control NSE. first 100h addresses provide access level configuration control registers, Clock synthesis units through CSTR blocks Crossbar (DCB). space switch core NSE. From 100h identical, spaces used control ports individual basis. Each port In-Band Link Controller (ILC), 8B/10B encoder (T8TE) 8B/10B decoder (R8TD). These blocks provide functions specific ports such Line Code Violation counts (for data integrity monitoring) receive transmit in-band link message buffers. Table shows registers. Only port fully described other ports identical, being incrementally distributed from address 100h steps.
Table NSE-20G Register Address
Register
Master Reset Individual Channel Reset Master JTAG In-Band Link Transmit Page In-Band Link Transmit Page Master Interrupt Source Master Interrupt Source Master R8TD Interrupt Source
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Address
01C-01F 027-03F 100-1FF
Register
Master T8TE Interrupt Source Master Clock Monitor, Accumulation Trigger select Master Interrupt Enable Subsystem Interrupt Enable R8TD In-Band Link Transmit User In-Band Link Transmit User In-Band Link Transmit User FREE User Register Correct R8TD_RX_C1 Pulse Monitor Register Unexpected R8TD_RX_C1 Interrupt Register Missing R8TD_RX_C1 Interrupt Register Unexpected R8TD_RX_C1 Interrupt Enable Register Missing R8TD_RX_C1 Interrupt Enable Register Reserved CSTR Control CSTR Interrupt Enable Lock Status CSTR Interrupt Indication Reserved CSTR Control CSTR Configuration Status CSTR Interrupt Status Reserved CONFIGURATION PORT 31-30 REGISTER CONFIGURATION PORT 29-24 REGISTER CONFIGURATION PORT 23-18 REGISTER CONFIGURATION PORT 17-12 REGISTER CONFIGURATION PORT 11-6 REGISTER CONFIGURATION PORT REGISTER CONFIGURATION OUTPUT REGISTER ACCESS MODE REGISTER DELAY (RC1FP) REGISTER FRAME SIZE REGISTER CONFIGURATION REGISTER INTERRUPT REGISTER Reserved Port Register Port (Channel Port Register R8TD Control Status
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Address
118-11F 120-13F 140-15F 160-17F 180-19F 1A0-1BF 1C0-1DF 1E0-1FF 200-21F 220-23F 240-25F 260-27F 280-29F 2A0-2BF 2C0-2DF 2E0-2FF 300-31F 320-33F 340-35F 360-37F 380-39F
Register
Port Register R8TD Interrupt Status Port Register R8TD Count Port Register RXLV Control Port Register Reserved Port Register T8TE Control Status Port Register T8TE Interrupt Status Port Register T8TE Time-slot Configuration Port Register T8TE Time-slot Configuration Port Register T8TE Test Pattern Port Register TXLV PISO Control Port Register Reserved Port Register Transmit Message FIFO Data Port Register Transmit Control Port Register Transmit Status FIFO Synch Port Register Receive Message FIFO DATA Port Register Receive Control Port Register Receive Status FIFO Synch Port Register Interrupt enable Control Port Register Interrupt reason Register Reserved Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel
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Address
3A0-3BF 3C0-3DF 3E0-3FF 400-41F 420-43F 440-45F 460-47F 480-49F 4A0-4BF 4C0-4DF 4E0-4FF 500-7FF
Register
Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Reserved
Reserved Test
Notes Register Memory Map: register accesses, must low. Addresses that shown must treated Reserved. A[11] test register select (TRS) should logic normal mode register access.
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Normal Mode Register Description
Normal mode registers used configure monitor operation NSE. Normal mode registers opposed test mode registers) selected when A[11] low. Notes Normal Mode Register Bits: Writing values into unused register bits effect. However, ensure software compatibility with future, feature-enhanced versions this product, unused register bits must written with logic Reading back unused bits produce either logic logic hence, unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling determine programming state block. Writeable normal mode register bits cleared logic upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect operation unless otherwise noted. registers above 100H, only port ports shown. Register addresses shown example 0100H N*20H, here port number between This done prevent unnecessary duplication otherwise identical register sets.
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Register 000H:NSE Master Reset
29:0
Type
Function
DRESET ARESET Unused
Default
This register allows separate software reset digital analog circuitry NSE. ARESET ARESET allows analog circuitry reset under software control. ARESET logic one, analog circuitry held reset. ARESET must held logic least ensure correct reset CSU. This self-clearing. Therefore, logic zero must written bring reset. Holding reset state places into power, analog stand-by mode. hardware reset clears ARESET bit, thus negating analog software reset. DRESET DRESET allows digital circuitry reset under software control. DRESET logic one, digital circuitry held reset. This self-clearing. Therefore, logic zero must written bring reset. Holding reset state places into power, digital stand-by mode. hardware reset clears DRESET bit, thus negating digital software reset.
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Register 001H:NSE Individual Channel Reset
31:0
Type
Function
RESET[31:0]
Default
This register allows power saving holding individual channels reset. RESET[n] RESET[n] allows channel circuitry reset under software control. RESET[n] logic one, channel circuitry particular channel held reset. RESET[n] does affect reset CSU. This selfclearing. Therefore, logic zero must written bring channel reset. Holding channel reset state places into power, analog stand-by mode. hardware reset software DRESET 000h sets RESET[n] bit.
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Register 002H: Master JTAG
31:28 27:12 11:1
Type
Function
VERSION[3:0] PART_NUMBER[15:0] NSE-
Default
0001 1000011000100000 00001100110
MANUFACTURER_ID[10:0]
Master JTAG registers hold JTAG identification code device. device version number device part number available through these registers. VERSION[3:0] VERSION[3:0] `b0001. PART_NUMBER[15:0] PART_NUMBER[15:0] bits represent part number device. PART_NUMBER[15:0] 8620H NSE-20G. MANUFACTURER_ID[10:0] MANUFACTURER_ID[10:0] bits represent manufacturer's code assigned PMC-Sierra, Inc. inclusion JTAG Boundary Scan Identification Code. more information JTAG Boundary Scan, refer Section 11.2. JTAG identification code.
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Register 003H: In-Band Link Transmit Page
31:0
Type
Function
TX_ILC_PAGE_0[31:0]
Default
TX_ILC_PAGE_0[n] This will Page send over In-Band channel where transmit LVDS links numbered from
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Register 004H: In-Band Link Transmit Page
31:0
Type
Function
TX_ILC_PAGE_1[31:0]
Default
TX_ILC_PAGE_1[n] This will Page send over In-Band channel where transmit LVDS links numbered from
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Register 005H: Master Interrupt Source
31:8
Type
Function
Unused R8C1EXTRAINT R8C1MISSINT CSU2INT CSU1INT R8TDINT T8TEINT ILCINT DCBINT
Default
R8C1EXTRAINT R8C1EXTRAINT logic interrupt unexpected character more receive LVDS link occurred. source R8C1EXTRAINT comes from Register 013h. Unexpected R8TD_RX_C1 Interrupt register (Reg013h) must read clear this interrupt. R8C1MISSINT R8C1MISSINT logic interrupt missing characters more receive LVDS link occurred. source R8C1MISSINT comes from Register 014h. Missing R8TD_RX_C1 Interrupt register (Reg014h) must read clear this interrupt. CSU2INT CSU2INT logic interrupt been generated CSTR Interrupt Indication register (Reg026h) must read clear this interrupt. CSU1INT CSU1INT logic interrupt been generated CSTR Interrupt Indication register (Reg022h) must read clear this interrupt. R8TDINT R8TDINT logic interrupt been generated R8TD blocks. internal R8TD Interrupt register must read clear this interrupt. Which R8TD caused interrupt ascertained reading Master R8TD Interrupt Source register (Reg007h).
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T8TEINT T8TEINT logic interrupt been generated T8TE blocks. internal T8TE Interrupt register must read clear this interrupt. Which T8TE caused interrupt ascertained reading Master T8TE Interrupt Source register (Reg008h). ILCINT ILCINT logic interrupt been generated blocks. relevant Interrupt register must read clear this interrupt. Which caused interrupt ascertained reading Master Interrupt Source register (Reg006h). DCBINT DCBINT logic interrupt been generated block. Interrupt Status Register (Reg04Dh) must read clear this interrupt.
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Register 006H: Master Interrupt Source
31:0
Type
Function
ILCINT[31:0]
Default
ILCINT[n] ILCINT[n] logic interrupt been generated that block. relevant Interrupt register must read clear this interrupt.
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Register 007H: Master R8TD Interrupt Source
31:0
Type
Function
R8TDINT[31:0]
Default
R8TDINT[n] R8TDINT[n] logic interrupt been generated that R8TD block. relevant R8TD Interrupt register must read clear this interrupt.
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Register 008H: Master T8TE Interrupt Source
31:0
Type
Function
T8TEINT[31:0]
Default
T8TEINT[n] T8TEINT[n] logic interrupt been generated that T8TE block. relevant T8TE Interrupt register must read clear this interrupt.
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Register 009H: Master Clock Monitor, Accumulation Trigger
31:2
Type
Function
Unused RC1FPA SYSCLKA
Default
When monitored clock signal makes high transition, corresponding register high. will remain high until this register read, which point bits this register cleared. lack transitions indicated corresponding register reading low. This register should read periodic intervals detect clock failures. Writing this register delimits accumulation intervals R8TD Count registers. Counts accumulated those registers transferred holding registers where they read (Register 102H N*20). counters themselves then cleared begin accumulating events accumulation interval. prevent loss data, accumulation intervals must second shorter. bits this register affected write accesses. SYSCLKA SYSCLK active (SYSCLKA) detects high transitions SYSCLK input. SYSCLKA high rising edge SYSCLK, when this register read. RC1FPA RC1FP active (RC1FPA) detects high transitions RC1FP input. RC1FPA high rising edge RC1FP, when this register read.
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Register 00AH: select
31:2
Type
Function
Unused CMP_SRC CMP_VAL
Default
connection memory page select signal (CMP) controls selection connection memory page NSE. When high, connection memory page selected. When low, connection memory page selected. Changes connection memory page selection synchronized boundary next C1FP multi-frame. This Register controls software override pin. CMP_SRC This dictates whether source from CMP_VAL when from external when `0'. CMP_VAL CMP_VAL used provide signal when CMP_SRC other wise this ignored.
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Register 00BH: Interrupt Enable Register
31:1
Type
Function
Unused INTE
Default
This register allows disable enable interrupts with single write. INTE This bit, when `1', enables INTB NSE. When INTB held high impedance.
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Register 00CH: Subsystem Interrupt Enable Register
31:6
Type
Function
Unused TOPINTE CSUINTE R8TDINTE T8TEINTE ILCINTE DCBINTE
Default
This register allows disable enable Subsystem interrupts with single write. TOPINTE This bit, when `1', enables generation interrupts from Top_level i.e. R8C1EXTRAINT R8C1MISSINT interrupts. When R8C1EXTRAINT R8C1MISSINT interrupts disabled CSUINTE This bit, when `1', enables generation interrupts from CSU1 CSU2 control. When CSU1 CSU2 control interrupts disabled R8TDINTE This bit, when `1', enables generation interrupts from R8TD blocks. When R8TD interrupts disabled T8TEINTE This bit, when `1', enables generation interrupts from T8TE blocks. When T8TE interrupts disabled ILCINTE This bit, when `1', enables generation interrupts from blocks. When interrupts disabled DCBINTE This bit, when `1', enables generation interrupts from block. When interrupts disabled
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Register 00DH: R8TD Register
31:1
Type
Function
Unused
Default
This register monitors reporting R8TD's counter registers. Transfer Progress reflects state counter transfer R8TD. When high, counter transfer been initiated, counters transferred holding registers (i.e. Reg. 102H N*20H R8TD Line Code Violation Count register). When low, value counters available read holding registers. This poll after error counters transfer request, determine counters ready read.
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Register 00EH: In-Band Link Transmit User
31:0
Type
Function
TX_ILC_USER_0[31:0]
Default
TX_ILC_USER_0[n] This will USER sent over In-Band channel where transmit LVDS links numbered from
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Register 00FH: In-Band Link Transmit User
31:0
Type
Function
TX_ILC_USER_1[31:0]
Default
TX_ILC_USER_1[n] This will USER sent over In-Band channel where transmit LVDS links numbered from
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Register 010H: In-Band Link Transmit User
31:0
Type
Function
TX_ILC_USER_2[31:0]
Default
TX_ILC_USER_2[n] This will USER sent over In-Band channel where transmit LVDS links numbered from
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Register 011H: FREE User Register
31:8
Type
Function
Unused FREE[7:0]
Default
FREE[7:0] software register (FREE) holds whatever value written into Reset clears contents this register. This register impact operation NSE.
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Register 012H: Correct R8TD_RX_C1 Pulse Monitor
31:0
Type
Function
R8C1_OK_MON[31:0]
Default
R8C1_OK_MON[31:0] R8C1_OK_MON logic when character received receive LVDS link expected position with respect RC1FP input. This logic when this register read. Section 12.5: Controlling Frame Alignment Receive Port Describes proper this register.
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Register 013H: Unexpected R8TD_RX_C1 Interrupt
31:0
Type
Function
R8C1_EXTRA_INT[31:0]
Default
R8C1_EXTRA_INT[31:0] R8C1_EXTRA_INT logic when character received receive LVDS link unexpected position with respect RC1FP input. These interrupts enabled with R8C1_EXTRA_INTE bits Unexpected R8TD_RX_C1 Interrupt Enable register (Reg015h). These interrupt bits will cleared when read. Section 12.5: Controlling Frame Alignment Receive Port Describes proper this register.
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Register 014H: Missing R8TD_RX_C1 Interrupt
31:0
Type
Function
R8C1_MISS_INT[31:0]
Default
R8C1_MISS_INT[31:0] R8C1_MISS_INT logic when character received receive LVDS link expected position with respect RC1FP input. These interrupts enabled with R8C1_MISS_INTE bits Missing R8TD_RX_C1 Interrupt Enable register (Reg016h). These interrupt bits will cleared when read. Section 12.5: Controlling Frame Alignment Receive Port Describes proper this register.
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Register 015H: Unexpected R8TD_RX_C1 Interrupt Enable
31:0
Type
Function
R8C1_EXTRA_INTE[31:0]*
Default
R8C1_EXTRA_INTE[31:0] R8C1_EXTRA_INTE interrupt enable active high interrupt enable. When R8C1_EXTRA_INTE logic interrupt will asserted INTB output when R8C1_EXTRA_INT interrupt bits register 013H high, TOPINTE register 00CH INTE register 00BH high. When R8C1_EXTRA_INTE logic R8C1_EXTRA_INT interrupt bits will cause interrupt. This channel* basis. *Any unused ports must `0'.
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Register 016H: Missing R8TD_RX_C1 Interrupt Enable
31:0
Type
Function
R8C1_MISS_INTE[31:0]*
Default
R8C1_MISS_INTE[31:0] R8C1_MISS_INTE interrupt enable active high interrupt enable. When R8C1_MISS_INTE logic interrupt will asserted INTB output when R8C1_MISS_INT interrupt bits register 013H high, TOPINTE register 00CH INTE register 00BH high. When R8C1_MISS_INTE logic R8C1_MISS_INT interrupt bits will cause interrupt. This channel* basis. *Any unused ports must `0'.
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Register 020H, 024H: CSTR Control
31-16
Type
Function
Unused Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CSU_ENB CSU_RSTB Unused Unused Reserved
Default
This register provides reset control enable control CSTR blocks through Reserved Reserved bits must indicated default value correct operation NSE. CSU_RSTB CSU_RSTB signal software reset signal that forces CSU1250 into reset. order properly reset CSU, CSU_RSTB should held least also reset master analog reset signal. CSU_ENB active enable control signal (CSU_ENB) used force CSU1250 into power configuration logic normal operation, logic
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Register 021H, 025H: CSTR Interrupt Enable Lock Status
31-2
Type
Function
Unused LOCKV LOCKE
Default
This register configures operation CSTR blocks through LOCKE lock interrupt enable (LOCKE) controls contribution lock state interrupts CSTR device interrupt INTB. When LOCKE high, INTB asserted when lock state changes. Interrupts lock state masked when LOCKE low. LOCKV lock status (LOCKV) indicates whether clock synthesis unit successfully locked with system clock.LOCKV when successfully locked with reference clock. LOCKV high when locked with reference clock.
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Register 022H, 026H: CSTR Interrupt Indication
31-1
Type
Function
Unused LOCKI
Default
LOCKI lock interrupt status (LOCKI) reports acknowledges changes lock state. LOCKI high when achieves lock with reference clock loses lock reference clock. LOCKI cleared read this register. INTB asserted when both LOCKE LOCKI high. LOCKE asserted, LOCKI must cleared before INTB will reasserted.
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Register 040H: Configuration port 31-30 Register
31-10
Type
Function
Unused Port31[4:0] Port30[4:0]
Default
Port31[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port30[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 041H: Configuration port 29-24 Register
31-30 29-25 24-20 19-15 14-10
Type
Function
Unused Port29[4:0] Port28[4:0] Port27[4:0] Port26[4:0] Port25[4:0] Port24[4:0]
Default
Port29[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port28[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port27[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port26[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port25[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port24[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 042H: Configuration port 23-18 Register
31-30 29-25 24-20 19-15 14-10
Type
Function
Unused Port23[4:0] Port22[4:0] Port21[4:0] Port20[4:0] Port19[4:0] Port18[4:0]
Default
Port23[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port22[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port21[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port20[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port19[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port18[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 043H: Configuration port 17-12 Register
31-30 29-25 24-20 19-15 14-10
Type
Function
Unused Port17[4:0] Port16[4:0] Port15[4:0] Port14[4:0] Port13[4:0] Port12[4:0]
Default
Port17[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port16[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port15[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port14[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port13[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port12[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 044H: Configuration port 11-6 Register
31-30 29-25 24-20 19-15 14-10
Type
Function
Unused Port11[4:0] Port10[4:0] Port9[4:0] Port8[4:0] Port7[4:0] Port6[4:0]
Default
Port11[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port10[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port9[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port8[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port7[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port6[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 045H: Configuration port Register
31-30 29-25 24-20 19-15 14-10
Type
Function
Unused Port5[4:0] Port4[4:0] Port3[4:0] Port2[4:0] Port1[4:0] Port0[4:0]
Default
Port5[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port4[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port3[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port2[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port1[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port0[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 046H: Configuration Output Register
31-30 29-0
Type
Function
Unused CFG_O[29:0]
Default
CFG_O[29:0] This field contains configuration data read from offline connection memory page. Configuration data this field read from location specified WORDADDR PORTADDR fields Access Mode register. There SYSCLK cycle latency from when indirect read requested until when correct data appears this register.
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047H: Access Mode Register
28-24 23-21 20-16 15-14 13-0
Type
Function
ACCMDE Unused PORTCFG[4:0] Unused PORTADDR[4:0] Unused WORDADDR [13:0]
Default
Writing this register with register high initiates indirect read from offline connection memory page. WORDADDR selects offline connection memory page read from. There latency SYSCLK cycles from when this register written with high until when valid data appears Configuration Output register. Indirect reads should spaced least SYSCLK cycles apart permit valid data appear Configuration Output register. Writing this register with register initiates indirect write offline connection memory page. WORDADDR selects offline connection memory page write Indirect writes should spaced least SYSCLK cycles apart ensure writes complete successfully. While page copy progress (UPDATEV register `1'), writing this register will cause data updated to/from offline connection memory page. While page swap pending (SWAPV register `1'), writing this register cause unpredictable results data transferred while page swap occurring, causing data updated different connection memory page from intended. indirect access control selects between write read access offline connection memory page. ACCMDE These bits indicate access mode offline connection memory page. PORT transfer mode. WORD transfer mode. port transfer mode, port updated word offline connection memory page.
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PORTCFG: port mapping updated connection memory page. WORDADDR: specifies address offline connection memory page. PORTADDR: port address offline connection memory page. word transfer mode, entire word offline connection memory page updated. PORTCFG: ignored.
WORDADDR: specifies address offline connection memory page. PORTADDR: ignored.
either mode, contents read from offline connection memory page read microprocessor through Configuration Output register. PORTCFG[4:0] This field contains input port mapping particular output port specified PORTADDR. Used only PORT transfer mode. other modes, this field ignored. PORTADDR[4:0] When performing writes offline connection memory page, this field indicates output port updated with mapping PORTCFG. PORTADDR relates output port DCB. This field valid PORT transfer mode during reading from Configuration Output register ignored WORD transfer mode. Valid values 0-31 when performing writes. When performing reads through Configuration Output register, PORTADDR indicates ports being read follows: 000xx ports 001xx ports 11-6 010xx ports 17-12 011xx ports 23-18 100xx ports 29-24 101xx: ports 31-30 least significant bits 110xx: ports
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111xx: ports WORDADDR[13:0] This field indicates address update connection memory page accessed. This field relates time location within SBI/TelecomBus frame. I.e. Location would first byte frame location character. This field ignored page copy mode. Valid values 0-9719.
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Register 048H: delay (RC1DLY) Register
31-6 13-0
Type
Function
Unused RC1DLY[13:0]
Default
RC1DLY[13:0] This value, equaling delay 77.76 clock periods), between RC1FP arrival characters R8TD. This delay will synchronize input R8TD blocks assuming characters have arrived. delay those links dependent system design, backplane propagation delays, cable lengths etc. This value will have arrived empirically. will have upper lower limit which middle value should selected. Refer Operations section more detail some recommended starting values. proper operation NSE, RC1DLY must zeros.
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Register 04AH: Frame Size Register
31-14 13-0
Type
Function
Unused FRMSZ[13:0]
Default
25F7h
This register specifies frame size TelecomBus frame. FRMSZ[13:0] This register specifies size connection memory page various switching modes. Legal values: 1079 (437h): TelecomBus switching. 1079 (437h): column switching. 9719 (25F7h): switching. 9719 (25F7h): switching with CAS.
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Register 04CH: Configuration Register
Type
Function
Unused MF_SWAP[1:0] AUTO SWAP_PE UPDATEE FRAMEE SWAPV UPDATEV
Default
MF_SWAP [1:0] This selects when RC1FP expected synchronizes when page swaps occur. Table below relates MFSWAP vital variables from DCB:
MFSWAP Configuration Page Size
1080 1080 9720 9720
Frame Switching (9720 byte frame)
frame frame frame frame
Frame Interrupt
RC1FP expected every
frame frame frame frame
Switching Mode
frame frame frame frame
TelecomBus column mode mode with
AUTO This enables automatic copy online connection memory page offline connection memory page after connection memory page switched. Toggling AUTO while page copy progress will terminate page copy process. automatic update disabled. automatic update enabled. automatic page copying used, page copy will take place automatically whenever connection memory page swaps. This means that UPDATEV register will asserted immediately following change from SWAPV register bit. When AUTO set, access offline connection memory page restricted from when page swap pending until when page copy complete.
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SWAP_PE This enables propagation interrupt output change state SWAPV. This does have impact SWAPI bit. disables interrupt propagation output. enables interrupt propagation output. UPDATEE This enables propagation interrupt output when UPDATEV changes state from This does have impact UPDATEI disables interrupt propagation output. enables interrupt propagation output. FRAMEE This enables propagation interrupt output when sampled expected RC1FP position. This does have impact FRAMEI bit. disables interrupt propagation output. enables interrupt propagation output. SWAPV SWAPV contains current state page swap. This logic when switch connection memory page (CMP) input been recognized page swap happened. This logic when page swap pending. When page swap pending, writing offline page, initiating page copy changing connection memory page through input CMP_VAL register select register (Reg00Ah) cause corruption memory pages. UPDATEV This updated when active connection memory page copied offline connection memory page. copying completed. copying progress. duration page copy highly dependent MF_SWAP.
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MF_SWAP SYSCLK Clock cycles required "00" "01" "10" "11" 1083 1083 9723 9723
When page copy progress, attempting write offline connection memory page will ignored attempting read from offline connection memory page will return unpredictable results.
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Register 04DH: Interrupt Status Register
31-3
Type
Function
Unused SWAPI UPDATEI FRAMEI
Default
Writing this register initiates copying active connection memory page offline connection memory page. When page swap pending (SWAPV ='1') writing this register cause corruption connection memory pages. SWAPI This reports acknowledges change state SWAPV Configuration register. This cleared when this register read. When enabled SWAPE, output reflects state this bit. UPDATEI offline page copy interrupt status bit, UPDATEI reports acknowledges change state from UPDATEV Configuration register. This signifies that page copy complete. This cleared when read. When enabled UPDATEE bit, output reflects state this bit. FRAMEI frame interrupt status reports sampling expected RC1FP position. When enabled FRAMEE, frequency occurrence FRAMEI dependent MF_SWAP. When enabled FRAMEE bit, output reflects state this bit. MF_SWAP FRAMEI occurs every: frame frame frame frame
This cleared when read. change input should sequenced occur soon possible after occurrence FRAMEI. Changing prior occurrence FRAMEI cause unpredictable behavior cause sampled later than expected.
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Register 100H N*20H, R8TD Control Status
31:16 13:10
Type
Function
Unused Reserved Reserved Unused RXINV Reserved FUOE LCVE OFAE OCAE OFAV OCAV FOFA FOCA
Default
This register provides control reports status R8TD blocks. FOCA force out-of-character-alignment (FOCA) control operation character alignment block R8TD block. transition this forces character alignment block out-of-character-alignment state where
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