XC2C256 CoolRunner-II CPLD DS094 (v1.1) 2002 Advance Product
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XC2C256 CoolRunner-II CPLD
DS094 (v1.1) 2002
Advance Product Specification
Features
Optimized 1.8V systems fast pin-to-pin delays quiescent current Industry's best 0.18 micron CMOS CPLD Optimized architecture effective logic synthesis Multi-voltage operation 1.5V 3.3V Available multiple package options 100-pin VQFP with user 144-pin TQFP with user 132-ball (0.5mm) with user 208-pin PQFP with user 256-ball (1.0mm) with user Advanced system features Fastest system programming 1.8V using IEEE 1532 (JTAG) interface IEEE1149.1 JTAG Boundary Scan Test Optional Schmitt-trigger input (per pin) Unsurpassed power management separate output banks Fast Zero Power(FZP) 100% CMOS product term generation DataGATE enable (DGE) signal control Flexible clocking modes Optional DualEDGE triggered registers Clock divider (divide 2,4,6,8,10,12,14,16) CoolCLOCK Global signal options with macrocell control Multiple global clocks with phase selection macrocell Multiple global output enables Global set/reset Advanced design security Open-drain output option Wired-OR drive Optional bus-hold, 3-state weak pullup selected pins Optional configurable grounds unused I/Os Mixed voltages compatible with 1.5V, 1.8V, 2.5V, 3.3V logic levels SSTL2-1, SSTL3-1, HSTL-1 compatibility pluggable
Description
CoolRunner-II 256-macrocell device designed both high performance power applications. This lends power savings high-end communication equipment high speed battery operated devices. power stand-by dynamic operation, overall system reliability improved This device consists sixteen Function Blocks inter-connected power Advanced Interconnect Matrix (AIM). feeds true complement inputs each Function Block. Function Blocks consist P-term macrocells which contain numerous configuration bits that allow combinational registered modes operation. Additionally, these registers globally reset preset configured flip-flop latch. There also multiple clock signals, both global local product term types, configured macrocell basis. Output configurations include slew rate limit, hold, pull-up, open drain programmable grounds. Schmitt-trigger input available input basis. addition storing macrocell output states, macrocell registers configured "fast input" registers store signals directly from input pins. Clocking available global Function Block basis. Three global clocks available Function Blocks synchronous clock source. Macrocell registers individually configured power zero state. global set/reset control line also available asynchronously reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchonous set/reset output enable signals formed using product terms per-macrocell per-Function Block basis. DualEDGE flip-flop feature also available macrocell basis. This feature allows high performance synchronous operation based lower frequency clocking help reduce total power consumption device. Circuitry also been included divide externally supplied global clock (GCK2) eight different selections. This yields divide even clock frequencies. clock divide (division DualEDGE flip-flop gives resultant CoolCLOCK feature. DataGATE method selectively disable inputs CPLD that interest during certain points time.
Refer CoolRunnerTM-II family data sheet architecture description.
2002 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS094 (v1.1) 2002 Advance Product Specification
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XC2C256 CoolRunner-II CPLD mapping signal DataGATE function, lower power achieved reduction signal switching. Another feature that eases voltage translation output banking. output banks available CoolRunner-II 256-macrocell device that permits easy interfacing 3.3V, 2.5V, 1.8V, 1.5V devices. CoolRunner-II 256-macrocell CPLD compatible with standard LVTTL LVCMOS18, LVCMOS25, LVCMOS33 (see Table This device also 1.5V compatible with Schmitt-trigger inputs.
Supported Standards
CoolRunner-II macrocell features both LVCMOS LVTTL implementations. Table standard voltages. LVTTL standard general purpose EIA/JEDEC standard 3.3V applications that LVTTL input buffer Push-Pull output buffer. LVCMOS standard used 3.3V, 2.5V, 1.8V applications. CoolRunner-II CPLDs also 1.5V compatible with Schmitt-trigger inputs. Table Standards XC2C256 Output VCCIO Input VCCIO Board Input Termination VREF Voltage 0.75 1.25 0.75 1.25
Fast Zero Power Design Technology
Xilinx CoolRunner-II CPLDs fabricated 0.18 micron process technology which derived from leading edge FPGA product development. CoolRunner-II CPLDs employ Fast Zero Power(FZP), design technique that makes CMOS technology both fabrication design methodology. design technology employs cascade CMOS gates implement products instead traditional sense amplifier methodology. this technology, Xilinx CoolRunner-II CPLDs achieve both high-performance power operation. Types LVTTL LVCMOS33 LVCMOS25 LVCMOS18 1.5V HSTL-1 SSTL2-1 SSTL3-1
(mA)
30DS094_01_030102
Frequency (MHz)
Figure Frequency Table Frequency (LVCMOS 1.8V 25°C)(1) Frequency (MHz) Typical -7.5 (mA) Typical (mA)
Notes: 16-bit up/down, resettable binary counter (one counter function block).
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DS094 (v1.1) 2002 Advance Product Specification
XC2C256 CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol VCCIO VJTAG VAUX TSTG TSOL Description Supply voltage relative ground Supply voltage output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative ground(1) Voltage applied 3-state output(1) Value -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 +150 +260 +150 Units
Storage Temperature (ambient) Maximum Soldering temperature (10s 1/16in. 1.5mm) Junction Temperature
Notes: Maximum undershoot below must limited either 0.5V whichever easiest achieve. During transitions, device pins undershoot -2.0v overshoot +4.5V, provided this over undershoot lasts less than with forcing current being limited
Recommended Operating Conditions
Symbol VCCIO Parameter Supply voltage internal logic input buffers Commercial +70°C Industrial -40°C +85°C Units
Supply voltage output drivers 3.3V operation Supply voltage output drivers 2.5V operation Supply voltage output drivers 1.8V operation Supply voltage output drivers 1.5V operation
VAUX
JTAG programming
Electrical Characteristics (Over Recommended Operating Conditions)
Symbol ICCSB ICCSB CJTAG CCLK Parameter Standby current (-6, -7.5) Standby current (-5) Dynamic current (-6, -7.5) Dynamic current (-5) JTAG input capacitance Global clock input capacitance capacitance Test Conditions 1.9V, VCCIO 3.6V 1.9V, VCCIO 3.6V Min. Max. Units
DS094 (v1.1) 2002 Advance Product Specification
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XC2C256 CoolRunner-II CPLD
LVCMOS 3.3V Voltage Specifications
Symbol VCCIO CJTAG CCLK Parameter Input source voltage High level input voltage level input voltage High level output voltage VCCIO -0.1 VCCIO level output voltage VCCIO VCCIO Input leakage current High-Z leakage JTAG input capacitance Global clock input capacitance capacitance VCCIO 3.9V VCCIO 3.9V Test Conditions Min. -0.3 VCCIO 0.4V VCCIO 0.2V Max. VCCIO 0.3V Units
LVCMOS 2.5V Voltage Specifications
Symbol VCCIO CJTAG CCLK Parameter Input source voltage High level input voltage level input voltage High level output voltage VCCIO 2.3V -0.1 VCCIO 2.3V level output voltage VCCIO 2.3V 0.1mA, VCCIO 2.3V Input leakage current High-Z leakage JTAG input capacitance Global clock input capacitance capacitance VCCIO 3.9V VCCIO 3.9V Test Conditions Min. -0.3 VCCIO 0.4V VCCIO 0.2V Max. Units
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DS094 (v1.1) 2002 Advance Product Specification
XC2C256 CoolRunner-II CPLD
LVCMOS 1.8V Voltage Specifications
Symbol VCCIO CJTAG CCLK Parameter Input source voltage High level input voltage level input voltage High level output voltage VCCIO 1.7V -0.1 VCCIO 1.7V level output voltage VCCIO 1.7V VCCIO 1.7V Input leakage current High-Z leakage JTAG input capacitance Global clock input capacitance capacitance VCCIO 3.9V VCCIO 3.9V Test Conditions Min. VCCIO -0.3 VCCIO 0.45 VCCIO Max. VCCIO 0.45 Units
1.5V Voltage Specifications(1)
Symbol VCCIO CJTAG CCLK Parameter Input source voltage High level input voltage level input voltage High level output voltage VCCIO 1.4V -0.1 VCCIO 1.4V level output voltage VCCIO 1.4V VCCIO 1.4V Input leakage current High-Z leakage JTAG input capacitance Global clock input capacitance capacitance VCCIO 3.9V VCCIO 3.9V Test Conditions Min. VCCIO -0.3 VCCIO 0.45 VCCIO Max. Units
Notes: Hysteresis used 1.5V inputs.
DS094 (v1.1) 2002 Advance Product Specification
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XC2C256 CoolRunner-II CPLD
Electrical Characteristics Over Recommended Operating Conditions
Symbol TPD1 TPD2 TSUF TSU1 TSU2 FTOGGLE(1) FSYSTEM1(2) FSYSTEM2(2) FEXT1(3) FEXT2(3) TPSUF TPSU1 TPSU2 TPHF TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TSUEC THEC TPCW TDGSU TDGHO TDGR TDGW TCDRSU TCDRHO TCONFIG Parameter Propagation delay single p-term Propagation delay array Fast input register p-term clock setup time Setup time fast (single p-term) Setup time array) Fast input register hold time P-term hold time Clock output Internal toggle rate Maximum system frequency Maximum system frequency Maximum external frequency Maximum external frequency Fast input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time array) Fast input register p-term clock hold time P-term clock hold P-term clock output Global output enable/disable P-term output enable/disable Macrocell driven output enable/disable P-term set/reset output valid Global set/reset output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High P-term pulse width High Set-up before DataGATE latch assertion Hold DataGATE latch assertion DataGATE recovery data DataGATE high pulse width CDRST setup time before falling edge GCLK2 Hold time CDRST after falling edge GCLK2 Configuration time Min. Max. Min. Max. Min. Max. Unit
Notes: FTOGGLE (1/2*TCW) maximum frequency dual edge triggered flip-flop with output enabled. FSYSTEM1 (1/TCYCLE) internal operating frequency device fully populated with 16-bit resettable binary counter through p-term macrocell while FSYSTEM2 through array (one counter function block). FEXT1 (1/TSU2+TCO) maximum external frequency using p-term while FEXT2 through array.
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DS094 (v1.1) 2002 Advance Product Specification
XC2C256 CoolRunner-II CPLD
Internal Timing Parameters
Symbol
Buffer Delays
Max. Min. Max. Min.
Max. Units
Parameter(1) Input buffer delay Fast data register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay Output buffer enable/disable delay Control term delay Single P-term delay adder Multiple P-term delay adder Input output valid Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock output valid Set/reset output valid Clock doubler delay Feedback delay Macrocell global delay Standard input adder Hysteresis input adder Output adder Output slew rate adder Standard input adder Hysteresis input adder Output adder Output slew rate adder
Min.
TFIN TGCK TGSR TGTS TOUT
P-term Delays
TLOGI1 TLOGI2 TPDI TSUI TECSU TECHO TCOI TAOI TCDBL TOEM TIN15 THYS15 TOUT15 TSLEW15 TIN18 THYS18 TOUT18 TSLEW
Macrocell Delay
Feedback Delays
Standard Time Adder Delays 1.5V
Standard Time Adder Delays 1.8V CMOS
DS094 (v1.1) 2002 Advance Product Specification
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XC2C256 CoolRunner-II CPLD
Internal Timing Parameters (Continued)
Symbol TIN25 THYS25 TOUT25 TSLEW25 TIN33 THYS33 TOUT33 TSLEW33 SSTL2-1 Parameter(1) Standard input adder Hysteresis input adder Output adder Output slew rate adder Standard input adder Hysteresis input adder Output adder Output slew rate adder Input adder TIN, TFIN, TGCK, TGSR,TGTS Output adder TOUT SSTL3-1 Input adder TIN, TFIN, TGCK, TGSR,TGTS Output adder TOUT HSTL-1 Input adder TIN, TFIN, TGCK, TGSR,TGTS Output adder TOUT
Notes: input signal rise/fall.
Max. Min.
Max. Min.
Min.
Max.
Units
Standard Time Adder Delays 2.5V CMOS
Standard Time Adder Delays 3.3V CMOS/TTL
Standard Time Adder Delays HSTL, SSTL
Switching Characteristics
1.8V, 25oC
TPD_PAL (ns)
Number Outputs Switching
DS092_09_121501
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DS094 (v1.1) 2002 Advance Product Specification
XC2C256 CoolRunner-II CPLD
Descriptions
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
1(GSR) 2(GTS2) 2(GTS3) 2(GTS0) 2(GTS1)
DS094 (v1.1) 2002 Advance Product Specification
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XC2C256 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
5(GCK1) 5(GCK0) (CDRST) 6(GCK2) 6(DGE)
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DS094 (v1.1) 2002 Advance Product Specification
XC2C256 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
DS094 (v1.1) 2002 Advance Product Specification
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XC2C256 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
Notes: global output enable, global reset/set, global clock, CDRST clock divide reset, DataGATE enable.
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DS094 (v1.1) 2002 Advance Product Specification
XC2C256 CoolRunner-II CPLD
XC2C256 JTAG, Power/Ground, Connect Pins Total User
Type VAUX (JTAG supply voltage) Power internal (VCC) Power Bank (VCCIO1) Power Bank (VCCIO2) Ground VQ100 CP132 K12, G14, A14, N12, J14, H14, E14, B14, TQ144 109, 127, 108, 123, PQ208 105, 133, 157, 172, 181, 104, 129, 130, 141, 156, 177, 190, FT256 K13, D12, J11, K11, L10, F10, F11, G10, H10, J10, K10, L11, M10, T11, T12, T13, P11, T14, J16, K12, D16, G12, C15, D14,
connects
Total user
DS094 (v1.1) 2002 Advance Product Specification
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XC2C256 CoolRunner-II CPLD
Ordering Information
Pin/Ball Spacing 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm (C/Watt) (C/Watt) 43.1 43.1 43.1 65.0 65.0 65.0 37.2 37.2 37.2 36.9 36.9 36.9 34.6 34.6 34.6 43.1 65.0 37.2 36.9 34.6 10.9 10.9 10.9 15.0 15.0 15.0 15.0 10.9 15.0 Package Dimensions 14mm 14mm 14mm 14mm 14mm 14mm 20mm 20mm 20mm 20mm 20mm 20mm 28mm 28mm 28mm 28mm 28mm 28mm 17mm 17mm 17mm 17mm 17mm 17mm 14mm 14mm 20mm 20mm 28mm 28mm 17mm 17mm Commercial Industrial
Part Number XC2C256-5VQ100 XC2C256-6VQ100 XC2C256-7VQ100 XC2C256-5CP132 XC2C256-6CP132 XC2C256-7CP132 XC2C256-5TQ144 XC2C256-6TQ144 XC2C256-7TQ144 XC2C256-5PQ208 XC2C256-6PQ208 XC2C256-7PQ208 XC2C256-5FT256 XC2C256-6FT256 XC2C256-7FT256 XC2C256-7VQ100 XC2C256-7CP132 XC2C256-7TQ144 XC2C256-7PQ208 XC2C256-7FT256
Package Type Very Thin Quad Flat Pack Very Thin Quad Flat Pack Very Thin Quad Flat Pack Chip Scale Package Chip Scale Package Chip Scale Package Thin Quad Flat Pack Thin Quad Flat Pack Thin Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin Fine Pitch Thin Fine Pitch Thin Very Thin Quad Flat Pack Chip Scale Package Thin Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin
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DS094 (v1.1) 2002 Advance Product Specification
XC2C256 CoolRunner-II CPLD
DS094 (v1.1) 2002 Advance Product Specification
I/O(2) I/O(5) VCCIO1
I/O(1) I/O(1) I/O(1) I/O(1) VAUX VCCIO1 I/O(2) I/O(2) I/O(4)
VCCIO2
VCCIO2
I/O(3)
VQ100 View
VCCIO1
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset Data Gate
Figure VQ100 Very Thin Quad Flat Pack
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XC2C256 CoolRunner-II CPLD
VCCIO1
I/O(5) I/O(2)
VCCIO1
I/O(4)
I/O(2)
I/O(2)
VCCIO1
CP132 Bottom View
VCCIO1
VAUX
I/O(1)
I/O(1)
VCCIO2
I/O(1)
I/O(1)
I/O(3)
VCCIO2
VCCIO2
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
Figure CP132 Chip Scale Package
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DS094 (v1.1) 2002 Advance Product Specification
XC2C256 CoolRunner-II CPLD
I/O(1) I/O(1) I/O(1) I/O(1) VAUX VCCIO1 I/O(2) I/O(2) I/O(4)
I/O(3) VCCIO2 VCCIO2 VCCIO2
TQ144 View
VCCIO1 VCCIO1
I/O(2) I/O(5)
Figure TQ144 Thin Quad Flat Pack
DS094 (v1.1) 2002 Advance Product Specification
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VCCIO1
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
XC2C256 CoolRunner-II CPLD
I/O(1) I/O(1) I/O(1) I/O(1) VAUX VCCIO2 VCCIO1 I/O(2) I/O(2) I/O(4)
I/O(3) VCCIO2 VCCIO2 VCCIO2 VCCIO2
PQ208 View
I/O(2) I/O(5) VCCIO1 VCCIO1 VCCIO1
VCCIO2 VCCIO1 VCCIO1
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
Figure PQ208 Quad Flat Package
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DS094 (v1.1) 2002 Advance Product Specification
XC2C256 CoolRunner-II CPLD
I/O(2) I/O(4) I/O(5)
I/O(3)
I/O(1)
I/O(1)
I/O(1)
I/O(1)
VCCIO2 VCCIO2 VCCIO2 VCCIO2
VAUX
VCCIO2
VCCIO2
VCCIO2
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1 VCCIO1 VCCIO1 VCCIO1
I/O(2)
I/O(2)
FT256 Bottom View
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
Figure FT256 Fine Pitch Thin
Revision History
following table shows revision history this document. Date 05/09/02 05/13/02 Version Initial Xilinx release. Updated Electrical Characteristics added parameters. Revision
DS094 (v1.1) 2002 Advance Product Specification
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