User's Manual 14.07.99 K8/EIS Klose-2969 manual_cover.f

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User's Manual
User's Manual
14.07.99
K8/EIS Klose-2969
manual_cover.fm
061.0/2.5 26.11.97
Robert Bosch GmbH Automotive Equipment Division Development Integrated Circuits (MOS)
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User's Manual
Copyright Notice Proprietary Information
Copyright 1998, 1999 Robert Bosch GmbH. rights reserved. This software manual owned Robert Bosch GmbH, used only authorized license agreement controlling such use. part this publication reproduced, transmitted, translated, form means, electronic, mechanical, manual, optical, otherwise, without prior written permission Robert Bosch GmbH, expressly provided license agreement.
Disclaimer
ROBERT BOSCH GMBH, MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. ROBERT BOSCH GMBH, RESERVES RIGHT MAKE CHANGES WITHOUT FURTHER NOTICE PRODUCTS DESCRIBED HEREIN. ROBERT BOSCH GMBH DOES ASSUME LIABILITY ARISING APPLICATION PRODUCT CIRCUIT DESCRIBED HEREIN.
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User's Manual
A_CAN
About this Document
1.1. Change Control 1.1.1. Current Status 1.1.2. Change History 1.2. Conventions 1.3. References 1.4. Terms Abbrevations
Product Description
2.1. Scope 2.2. Overview 2.3. Block Diagram 2.4. Register 2.5. Address 2.6. Reset Description 2.7. Operating Modes 2.7.1. Software Initialization 2.7.2. Configuration Timing 2.7.3. Disable Automatic Retransmission 2.7.4. Test Mode 2.7.4.1.Loop Back Mode 2.7.4.2.Silent Mode 2.7.4.3.Loop Back combined with Silent Mode 2.7.4.4.Software control CAN_TX
Module Interface
3.1. Customer Interface 3.2. Generic Interface
manualTOC.fm
Registers
4.1. Control Register 4.2. Status Register 4.3. Receive Error Counter 4.4. Transmit Error Counter 4.5. Timing Register 4.6. Timing Register 4.7. Interrupt Flag Register 4.8. Interrupt Enable Register 4.9. Receive Flag Register 4.10. Transmit Flag Register
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4.11. Test Register
Message Buffers Identifier Mask
5.1. Mask Register 5.2. Mask Register 5.3. Mask Register 5.4. Mask Register 5.5. Control Register 5.6. Configuration Register 5.7. Identifier Registers 5.8. Identifier Registers 5.9. Identifier Registers 5.10. Identifier Registers 5.11. Data Registers
Message Handler
6.1. Reception 6.1.1. Data Frame 6.1.2. FIFO Buffer 6.1.3. Remote Frame 6.2. Transmission 6.3. Handling Interrupts
Core
7.1. Shift Register 7.2. Protocol Controller 7.2.1. Stream Processor 7.2.2. Cyclic Redundancy Checker 7.2.3. Error Management Logic 7.2.4. Timing Logic
manualTOC.fm
Application
8.1. Timing 8.1.1. Definition Time Segments 8.1.2. Hard Synchronisation Resynchronisation 8.1.3. Calculation Time 8.2. Examples 8.2.1. Example Timing high Baudrate 8.2.2. Example Timing Baudrate 8.3. Handling Receive Buffers 8.4. Handling Transmit Buffers
Timings
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9.1. Electrical Interface 9.2. Timing Considerations 9.2.1. Read Write Timings 9.2.2. Interrupt Timing
Appendix
10.1. List Figures 10.2. List Tables
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About this Document
Change Control 1.1.1 Current Status Revision 1.1.2 Change History Issue Draft Draft Draft Revision Date 16.12.98 16.02.99 20.04.99 14.07.99 Horst Horst Horst Horst Change First Draft Extended Identifier Mode added, signal names modified Revised version
Conventions following conventions used within this User's Manual. Helvetica bold Names bits signals States bits signals
Helvetica italic
References This document refers following documents. Author(s) FV/SLN1 K8/EIS1 K8/EIS1 Title Specification Revision A_CAN Module Integration Guide VHDL Reference User's Manual
manual_about.fm
Terms Abbrevations This document uses following terms abbrevations. Term Meaning Controller Area Network Stream Processor Timing Logic Cyclic Redundancy Check Register Data Length Code Error Management Logic Finite State Machine Time Triggered 6/54 manual_about.fm
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Product Description
Scope This document describes A_CAN module features from point programmer wants module application. information neccessary integrate A_CAN module into user-defined ASIC located "Module Integration Guide". Overview A_CAN module that integrated stand-alone device part ASIC. described VHDL level, prepared synthesis. A_CAN performs communication according Protocol Version Part bitrate programmed values 1MBit/s depending used technology. connection physical layer additional transceiver hardware required. A_CAN consists Protocol Controller with Rx/Tx Shift Register, three Message Buffers, progammable Identifier Mask, Message Handler. external connected 8-bit non-multiplex Motorola HC08 compatible module interface. functions concerning handling messages like acceptance filtering, transfer messages between Shift Register Message Buffers, well handling transmission requests generation module interrupt implemented Message Handler. 8-bit module interface easily replaced customized module interface adapted needs user. A_CAN implements following features:
Supports Protocol Version Part Bitrates MBit/s Disable Automatic Retransmission mode Three Message Buffers configurable receive transmit buffer Programmable FIFO mode programmable identifier mask Maskable interrupt Programmable loop-back mode self-test operation 8-bit non-multiplex Motorola HC08 compatible module interface
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A_CAN Block Diagram
User's Manual
design consists following functional blocks (see figure Core Protocol Controller Rx/Tx Shift Register. Message Buffers Mask Three Message Buffers Identifier Mask. Registers registers used control configure module. Message Handler State Machine that controls data transfer between Rx/Tx Shift Register Core Message Buffers well generation Interrupts programmed Control Configuration Registers. Module Interface 8-Bit non-multiplex Motorola HC08 compatible module interface. easily replaced user-defined module interface.
CAN_TX CAN_RX
A_CAN Core Message Handler
IRQ_B
Message Buffers Mask
manual_product_description.fm
Registers
Module Interface
K8/EIS Klose-2969
WE_B
RE_B
CS_B
ADDR(5:0)
RESET_B
SCLK
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Figure Block Diagram
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DATA(7:0)
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A_CAN Register
User's Manual
A_CAN module allocates address space bytes. module selected activating signal CS_B. registers organized 8-bit registers. brief description registers chapter chapter
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Message Buffer
Control Reserved Status Reserved Timing Timing Interrupt Flag Interrupt Enable Receive Flag Transmit Flag Mask0 Mask1 Mask2 Mask3 Control Configuration Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Reserved Reserved
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x032 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
Control Configuration Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Reserved Reserved Control Configuration Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Reserved Test
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Read access only Write access only Test Mode enabled Write access only Configuration Change Enable Init Figure A_CAN Register
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Message Buffer
Message Buffer
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A_CAN Address Register Control Status Timing Timing Interrupt Flag Interrupt Enable Receive Flag Transmit Flag Mask Mask Mask Mask Control Configuration Identifier Identifier Identifier
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Address 0x00 0x02 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x20
Access read/write read/write read read read/write read/write read read/write read read read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write
Description Control Register Status Register, only writable Receive Error Counter Transmit Error Counter Timing Register Timing Register Interrupt Flag Register Interrupt Enable Register Receive Flag Register Transmit Flag Register Mask Register Msk(28:21) Mask Register Msk(20:13) Mask Register Msk(12:5) Mask Register Msk(4:0), MXtd, MDir Message Buffer Control Register Message Buffer Configuration Register Identifier ID(28:21) Identifier ID(20:13) Identifier ID(12:5) Identifier ID(4:0) Message Buffer Data Byte first data byte received/transmitted Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Control Register
Identifier Data0 Data1 Data2 Data3 Data4
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Data5 Data6 Data7 Control
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Register Configuration Identifier Identifier Identifier Identifier Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Control Configuration Identifier Identifier Identifier Identifier Data0
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Address 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3F
Access read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write
Description Message Buffer Configuration Register Identifier ID(28:21) Identifier ID(20:13) Identifier ID(12:5) Identifier ID(4:0) Message Buffer Data Byte first data byte received/transmitted Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Control Register Message Buffer Configuration Register Identifier ID(28:21) Identifier ID(20:13) Identifier ID(12:5) Identifier ID(4:0) Message Buffer Data Byte first data byte received/transmitted Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Message Buffer Data Byte Test Register
Data1 Data2 Data3 Data4 Data5
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Data6 Data7 Test
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Table A_CAN Address
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A_CAN Reset Description
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After hardware reset, registers module hold following values: Register Control Register Status Register Receive Error Counter Transmit Error Counter Timing Register Timing Register Interrupt Flag Register Interrupt Enable Register Receive Flag Register Transmit Flag Register Mask Register Mask Register Mask Register Mask Register Control Register Configuration Register Identifier Identifier Identifier Identifier Data Data Data Data Data Data Data Data Control Register Configuration Register Identifier Identifier Identifier Identifier Data Data Data Data Data Data Data Data
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Address 0x00 0x02 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 12/54
Reset Value 0x01 0x00 0x00 0x00 0x00 0x23 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 14.07.99
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Register Control Register Configuration Register Identifier Identifier Identifier Identifier Data Data Data Data Data Data Data Data
Address 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D
Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 r000 0000*
Test Register 0x3F actual value CAN_RX
Additionally busoff state reset output CAN_TX recessive (HIGH). value 0x01 (Init `1') Control Register enables software initialisation.
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A_CAN Operating Modes 2.7.1 Software Initialization
User's Manual
software initialization started setting Init Control Register, either software hardware reset, going busoff. While Init set, message transfer from stopped, status output CAN_TX recessive (HIGH). counters unchanged. Setting Init does change configuration register. initialize Controller, Timing Register each message buffer. message buffer needed, sufficient it's MsgVal valid. Otherwise, whole message buffer initialized. Resetting Init only) finishes software initialisation. Afterwards Stream Processor (see section page synchronizes itself data transfer waiting occurrence sequence consecutive recessive bits Idle) before take part activities starts message transfer. initialization message buffers independent Init done fly, message buffers should configured particular identifiers valid before starts message transfer. change configuration message buffer during normal operation, start setting MsgVal respective Message Buffer Control Register valid. When configuration completed, MsgVal valid again. Note: busoff recovery sequence (see Specification Rev. 2.0) cannot shortened setting resetting Init. device goes busoff, will Init accord, stopping activities. Once Init been cleared CPU, device will then wait occurrences Idle (129 consecutive recessive bits) before resuming normal operations. busoff recovery sequence, Error Management Counters will reset. During waiting time after resetting Init, each time sequence recessive bits been monitored, Bit0Error code written Status Register, enabling readily check whether stuck dominant continously disturbed monitor proceeding busoff recovery sequence.
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2.7.2 Configuration Timing After setting bits Init Control Register, timing configured writing Timing Registers. While Timing Register controls (Re)Synchronisation Jump Width Baud Rate Prescaler, Timing Register used define position Sample Point inside Time. detailed description program timing section page
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2.7.3 Disable Automatic Retransmission According Specification (see ISO11898, 6.3.3 Recovery Management), A_CAN provides means automatic retransmission frames that have lost arbitration that have been disturbed errors during transmission. frame transmission service will confirmed user before transmission successfully completed. default, this means automatic retransmission enabled. disabled enable A_CAN work within Time Triggered (TTC) environment. automatic retransmission disabled programming Control Register one. this operation mode programmer consider different behaviour bits TxRqst NewDat Control Registers Message Buffers: When transmission starts TxRqst respective Message Buffer reset, while NewDat remains set. When transmission completed successfully NewDat reset. When transmission failed (lost arbitration error) NewDat remains set. restart transmission TxRqst back one.
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A_CAN 2.7.4 Test Mode
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Test Mode entered setting Test Control Register one. Test Mode bits Tx1, Tx0, LBack Silent Test Register writable. monitors state CAN_RX therefore only readable. 2.7.4.1 Loop Back Mode Core Loop Back Mode programming Test Register LBack one. Loop Back Mode, Core treats transmitted messages received messages stores them they pass acceptance filtering) into Receive Buffer. Figure shows connection signals CAN_TX CAN_RX Core Loop Back Mode.
CAN_TX CAN_RX
Core
Figure Core Loop Back Mode This mode provided self-test functions. independent from external stimulation, Core ignores acknowledge errors dominant sampled acknowledge slot data remote frame) Loop Back Mode. this mode Core performs internal feedback from output input. actual value CAN_RX input disregarded Core. transmitted messages monitored CAN_TX pin. 2.7.4.2 Silent Mode Core Silent Mode programming Test Register Silent one. Silent Mode, A_CAN able receive valid data frames valid remote frames, sends only recessive bits cannot start transmission. Core required send dominant (ACK bit, overload flag, active error flag), rerouted internally that Core monitors this dominant bit, although remain recessive state. Silent Mode used analyze traffic without affecting transmission dominant bits (Acknowledge Bits, Error Frames). Figure shows connection signals CAN_TX CAN_RX Core Silent Mode.
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CAN_TX CAN_RX
Core
Figure Core Silent Mode
2.7.4.3 Loop Back combined with Silent Mode also possible combine Loop Back Mode Silent Mode programming bits LBack Silent same time. This mode used "Hot Selftest", meaning A_CAN tested Loop Back Mode without affecting running system connected pins CAN_TX CAN_RX. this mode CAN_RX disconnected from Core CAN_TX held recessive. Figure shows connection signals CAN_TX CAN_RX Core case combination Loop Back Mode with Silent Mode.
CAN_TX CAN_RX
manual_product_description.fm
Core
K8/EIS Klose-2969
Figure Core Loop Back combined with Silent Mode
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2.7.4.4 Software control CAN_TX output mode CAN_TX selected programming Test Register bits described section 4.11 page programming bits only considered when bits LBack Silent zero. Otherwise CAN_TX behaves described subsections 2.7.4.1 Loop Back Mode, 2.7.4.2 Silent Mode 2.7.4.3 Loop Back combined with Silent Mode.
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Module Interface
module interface A_CAN consist parts (see figure Generic Interface which part A_CAN module Customer Interface which adapted customers requirements.
SCLK
RESET_B RE_B
Customer Interface
CAN_RESET
Generic Interface
RD_INT_FLAGS wr_reg1
CAN_WR_B WE_B CS_B ADDR(5:0)
reg1_din
Buffers
CAN_SELECT
Address Decode
reg1
Data Control
CAN_ADDR CAN_DATA_IN
wr_regn regn_din regn
DATA(7:0) CAN_DATA_OUT IRQ_B
Drivers
CAN_INT
Figure Structure module interface Customer Interface
manual_interface.fm
purpose Customer Interface adapt timings module-external signals timing requirements module buffer drive external signals. Customer Interface delivered with module 8-bit non-multiplex interface designed connection Motorola HC08 controller. description interface timing section page
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A_CAN Generic Interface
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Generic Interface connects module-internal registers. Generic Interface operate modes, connection 8-bit Customer Interfaces, connection 16-bit Customer Interfaces. mode selected generic DB_W. Each 8-bit module registers connected Generic Interface write control line wr_regx, eight data input lines regx_din eight data output lines regx. clear Interrupt Flag Register read access there exists extra control signal RD_INT_FLAGS.
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Registers
registers located this block used control/configure Core Message Handler. Note: Reserved bits (res) read '0'. Control Register Module Address 0x00
Test
Init
Test
Test Mode Enable
zero
Test Mode. Normal Operation.
Disable Automatic Retransmission
zero
Automatic Retransmission disabled. Automatic Retransmission disturbed messages enabled.
Configuration Change Enable
zero
write access Timing Registers (while Init one). write access Timing Registers.
Module Interrupt Enable
zero
Init
Enabled Interrupts will IRQ_B LOW. IRQ_B remains until Interrupt Register read. Disabled Module Interrupt IRQ_B always HIGH.
Initialization
manual_registers.fm
zero
Initialization started. Normal Operation.
Status Register Module Address 0x02
BOff
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EWarn
EPass
BOff
Busoff Status
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zero
module busoff state. module busoff.
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A_CAN EWarn Warning Status
User's Manual
zero
EPass
least error counters reached error warning limit Both error counters below error warning limit
Error Passive
zero
Core error passive state defined Specification. Core error active.
Last Error Code This field holds code which indicates type last error occur bus. message been transferred (reception transmission) without error, this field will cleared `0'. code unused written check updates.
Error Stuff Error More than equal bits sequence have occurred part received message where this allowed. Form Error fixed format part received frame wrong format. AckError message this Core transmitted acknowledged another node. Bit1Error During transmission message (with exception arbitration field), device wanted send recessive level (bit logical value `1'), monitored value dominant. Bit0Error During transmission message acknowledge bit, active error flag, overload flag), device wanted send dominant level (data identifier logical value `0'), monitored value recessive. During busoff recovery this status each time sequence recessive bits been monitored. This enables monitor proceeding busoff recovery sequence (indicating stuck dominant continously disturbed). CRCError check incorrect message received, received incoming message does match with calculated received data.
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Error Interrupt generated change bits BOff EWarn. change EPass will never generate Error Interrupt. Status Interrupt generated change Last Error Code LEC. Note: generation interrupt corresponding enable bits Interrupt Enable Register Control Register must set.
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A_CAN Receive Error Counter Module Address 0x04
User's Manual
REC6-0
Receive Error Passive
zero
REC6-0
Receive Error Counter reached error passive level defined Specification. Receive Error Counter below error passive level.
Receive Error Counter Actual state Receive Error Counter. Values between 127.
Transmit Error Counter Module Address 0x05
TEC7-0
TEC7-0
Transmit Error Counter Actual state Transmit Error Counter. Values between 255.
Timing Register Module Address 0x06
manual_registers.fm
(Re)Synchronisation Jump Width Valid programmed values 0-3. actual interpretation hardware this value such that more than value programmed here used.
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Baud Rate Prescaler value which oscillator frequency divided generating time quanta. time built from multiple this quanta. Valid values Baud Rate Prescaler 0-63. actual interpretation hardware this value such that more than value programmed here used.
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A_CAN Timing Register Module Address 0x07
User's Manual
TSeg2
TSeg1
TSeg1
time segment before sample point, valid values TSeg1 actual interpretation hardware this value such that more than value programmed here used. time segment after sample point, valid values TSeg2 actual interpretation hardware this value such that more than value programmed here used.
TSeg2
Note: With SCLK reset values Timing 0x00 Timing 0x23 configure module bitrate kBit/s. registers only writable bits Init Control Register set. Interrupt Flag Register Module Address 0x08
Error
Status
RxOk
TxOk
Error
Error Interrupt
zero
Status
manual_registers.fm
Error Interrupt Error Interrupt
Status Interrupt
zero
RxOk
Status Interrupt Status Interrupt
Received Message Successfully
zero
TxOk
message been successfully received (independent result acceptance filtering). message been successfully received.
Transmitted Message Successfully
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zero
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Since this last read CPU, message been successfully (error free acknowledged least other node) transmitted. Since this read CPU, message been successfully transmitted. This never reset Core.
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A_CAN Message Buffer Interrupt
User's Manual
zero
Successful transmission reception Message Buffer interrupt from Message Buffer
Message Buffer Interrupt
zero
Successful transmission reception Message Buffer interrupt from Message Buffer
Message Buffer Interrupt
zero
Successful transmission reception Message Buffer interrupt from Message Buffer
Note: MB1, MB2, will always together with TxOk with RxOk message matched respective Message Buffer. read access Interrupt Flag Register will reset flags zero. These flags will never reset Message Handler. Interrupt Enable Register Module Address 0x09
RxIE
TxIE
MB3IE
MB2IE
MB1IE
Error Interrupt Enable
zero
Enabled change bits BOff EWarn Status Register will generate interrupt Disabled Error Interrupt will generated.
Status Change Interrupt Enable
zero
manual_registers.fm
Enabled interrupt will generated when message transfer successfully completed error detected. Disabled Status Change Interrupt will generated.
RxIE
Receive Interrupt Enable
zero
TxIE
interrupt generated after successful reception frame interrupt generated after successful reception frame.
Transmit Interrupt Enable
zero
K8/EIS Klose-2969
interrupt generated after successful transmission frame interrupt generated after successful transmission frame.
MB3IE
Message Buffer Interrupt Enable
zero
Message Buffer Interrupt enabled Interrupt from Message Buffer disabled
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A_CAN MB2IE
User's Manual Message Buffer Interrupt Enable
zero
MB1IE
Message Buffer Interrupt enabled Interrupt from Message Buffer disabled
Message Buffer Interrupt Enable
zero
Message Buffer Interrupt enabled Interrupt from Message Buffer disabled
Note: generation interrupt signal IRQ_B disabled setting Control Register. Receive Flag Register Module Address 0x0A
MsgLst3
NewDat3
MsgLst2
NewDat2
MsgLst1
NewDat1
NewDat1,2,3
Data Flag Message Handler written data into data portion Message Buffer flag been CPU. data been written into data portion Message Buffer Message Handler since last time this flag cleared CPU. Message Lost Flag Message Handler stored message into this Message Buffer when NewDat still set, A_CAN lost message. message lost since last time this reset CPU.
zero
MsgLst1,2,3
zero
Note: These flags copies corresponding bits from Message Buffer Control Registers.
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A_CAN 4.10 Transmit Flag Register Module Address 0x0B
User's Manual
TxRqst3
RmtPnd2
TxRqst2
RmtPnd1
TxRqst1
RmtPnd3
TxRqst1,2,3
Transmit Request Flag transmission this message buffer requested done. This message buffer waiting transmission. Remote Pending Flag transmission this Message Buffer requested remote node done. There waiting remote request this Message Buffer.
zero
RmtPnd1,2,3
zero
Note: These flags copies corresponding bits from Message Buffer Control Registers. 4.11 Test Register Module Address 0x3F
LBack
Silent
Tx1-0
Monitors actual value CAN_RX Control CAN_TX (only when Silent LBack zero)
manual_registers.fm
LBack
Reset value, CAN_TX controlled Core. Sample Point monitored CAN_TX pin. CAN_TX drives dominant (`0') value. CAN_TX drives recessive (`1') value.
Loop Back Mode
zero
Silent
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Loop Back Mode enabled. Loop Back Mode disabled.
Silent Mode
zero
module Silent Mode Normal operation.
Write access Test Register enabled setting Test Control Register.
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Message Buffers Identifier Mask
This block consists Identifier Mask three individual configurable Message Buffers. Each Message Buffer composed registers Control, Configuration, Identifier0 Identifier3 Data0 Data7. three Message Buffers have same properties. Conflicts resolved fixed priority with having highest priority having lowest priority. user program configurations from three Receive Buffers three Transmit Buffers combination between. direction Message Buffer Configuration Register used distinguish between Receive Transmit Buffers. transmission requested Receive Buffer (TxRqst '1'), Remote Frame will sent (see section 6.1.3 page 35). Note: Reserved bits (res) read except Mask3 where they read '1'. When using Standard Frames identifiers stored into bits ID28 ID18 Identifier Registers this case only these bits together with mask bits Msk28 Msk18 considered acceptance filtering.
Message Buffers Identifier Mask Identifier Mask
Mask0 Mask3
Message Buffer (MB1)
Control
Configuration
Identifier0 Identifier3
Data0 Data7
Message Buffer (MB2)
manual_message_buffers.fm
Control
Configuration
Identifier0 Identifier3
Data0 Data7
Message Buffer (MB3)
Control
Configuration
Identifier0 Identifier3
Data0 Data7
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Figure Message Buffer Identifier Mask
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A_CAN Mask Register Module Address 0x0C
User's Manual
Msk28
Msk27
Msk26
Msk25
Msk24
Msk23
Msk22
Msk21
Msk28-21 Identifier Mask
zero
corresponding identifier used acceptance filtering. corresponding identifier message buffer cannot inhibit match acceptance filtering.
Mask Register Module Address 0x0D
Msk20
Msk19
Msk18
Msk17
Msk16
Msk15
Msk14
Msk13
Msk20-13 Identifier Mask
zero
corresponding identifier used acceptance filtering. corresponding identifier message buffer cannot inhibit match acceptance filtering.
Mask Register Module Address 0x0E
manual_message_buffers.fm
Msk12
Msk11
Msk10
Msk9
Msk8
Msk7
Msk6
Msk5
Msk12-5
Identifier Mask
zero
corresponding identifier used acceptance filtering. corresponding identifier message buffer cannot inhibit match acceptance filtering.
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A_CAN Mask Register Module Address 0x0F
User's Manual
Msk4
Msk3
Msk2
Msk1
Msk0
MXtd
Msk4-0
Identifier Mask
zero
MXtd
corresponding identifier used acceptance filtering. corresponding identifier message buffer cannot inhibit match acceptance filtering.
Mask Extended Identifier
zero
extended identifier (IDE) used acceptance filtering. extended identifier (IDE) effect acceptance filtering
Note: Identifier Mask used Remote Frames Hold ='0'. Writing Mask Register during running acceptance filtering produce unexpected results. Control Register Module Address: MB1= 0x10, 0x20, 0x30
RmtPnd
MsgVal
TxRqst
Hold
MsgLst
NewDat
MsgVal
Message Valid
This indicate that message buffer configured should considered Message Handler. hardware reset forces MsgVal `0'. This must reset wants write Identifier Configuration Register Message Buffer use.
manual_message_buffers.fm
zero
TxRqst
message buffer configured considered Message Handler. message buffer ignored Message Handler.
Transmit Request
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This indicate that message buffer should transmitted. TxRqst also Message Handler after reception remote frame Hold '0'. This will cleared Message Handler when message been successfully transmitted, NewDat been set. TxRqst while MsgVal '1', data section Message Buffer locked write accesses.
zero
transmission this message buffer requested done. This message buffer waiting transmission.
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Note: different behaviour TxRqst NewDat mode described section 2.7.3 page
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A_CAN RmtPnd Remote Pending
User's Manual
zero
Hold
transmission this Message Buffer requested remote node done. There waiting remote request this Message Buffer.
Hold Data
Hold used acceptance filtering, configure FIFO buffer control reaction received Remote Frames (see section 6.1).
zero
MsgLst
Data data field this Message Buffer overwritten. Remote Remote Frame stored. Data data written data field this Message Buffer Remote Automatic response enabled.
Message Lost
zero
NewDat
Message Handler stored message into this Message Buffer when NewDat still set, A_CAN lost message. message lost since last time this reset CPU.
Data
will this indicate that updated Message Buffer. This will ensure that message actually being transmitted during time Message Buffer updated CPU, Message Handler will reset TxRqst bit. this TxRqst only reset after actual data been successfully transferred. This Message Handler indicate that written data into Message Buffer.
zero
Message Handler written data into data portion Message Buffer. data been written into data portion Message Buffer Message Handler since last time this flag cleared CPU.
Note: When Message Handler writes data into message buffer, only data bytes defined valid. Unused data bytes will overwritten non-specified values.
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Configuration Register Module Address: 0x11, 0x21, 0x31
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DLC3-0
Extended Identifier
zero
extended Identifier bit) will used this Message Object. standard Identifier bit) will used this Message Object.
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A_CAN Message Direction
User's Manual
zero
Direction transmit: TxRqst, respective Message Object transmitted. reception Remote Frame with matching identifier, TxRqst this Message Object Hold zero). Direction receive: TxRqst, Remote Frame with identifier this Message Object transmitted. reception Data Frame with matching identifier, that message stored this Message Object.
DLC3-0
Data Length Code Valid values 0-8.
Note: This register only writable when MsgVal zero. Data Length Code message buffer must defined same corresponding objects with same identifier other nodes. When Message Handler stores data frame, will write value given received message. masked out, actual value received frame will stored. Identifier Registers Module Address: 0x12, 0x22, 0x32
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID28-ID21 Message Identifier Identifier Registers Module Address: 0x13, 0x23, 0x33
manual_message_buffers.fm
ID20
ID19
ID18
ID17
ID16
ID15
ID14
ID13
ID20-ID13 Message Identifier Identifier Registers Module Address: 0x14, 0x24, 0x34
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ID12
ID11
ID10
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ID12-ID5
Message Identifier
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A_CAN 5.10 Identifier Registers
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Module Address: 0x15, 0x25, 0x35
ID4-ID0
Message Identifier
Note: Identifier Registers only writable when MsgVal zero. 5.11 Data Registers Module Address: 0x16 0x1D, 0x26 0x2D, 0x36 0x3D
Data
Data 0-Data
Data Bytes Byte Data first data byte shifted into shift register Core during reception, byte Data last. Byte Data first data byte shifted shift register Core during transmission, byte Data last.
Reception Transmission
Note: While TxRqst valid Message Buffer, Data Registers writable. When Message Handler writes data into message buffer, only data bytes defined valid. Unused data bytes will overwritten non-specified values.
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Message Handler
Message Handler controls data transfer between shift register Core, Message Buffers. Message Handler controls following functions:
Data Transfer from Core shift register Receive Buffer Data Transfer from Transmit Buffer Core shift register Control acceptance filtering Control FIFO Buffer Handling transmission requests Handling interrupts.
Reception After reception complete message (Identifier DATA) Message Handler starts comparison arbitration field received message (Identifier IDE) against arbitration field valid Message Buffers. Message Buffers programmable acceptance mask (Mask0 Mask3) acceptance filtering. This enables classes messages received setting some bits identifier don't care. mask registers Mask0 Mask3 used mean don't care, i.e. corresponding arbitration field Receive Buffer cannot inhibit match acceptance filtering. match occurs Message Handler proceeds depending type frame received. Data Frames Remote Frames handled following (see also figure page figure page 46): 6.1.1 Data Frame After reception Data Frame Message Handler starts scanning Message Buffers from looking Message Buffer with:
manual_message_handler.fm
MsgVal (Direction receive Matching Identifier (Identifier Identifier Mask) NewDat Hold
When Message Buffer found that fulfils above conditions, Data Frame stored into this buffer, NewDat Message Handler stops. matching buffer found, Message Handler proceeds following way:
Inverted scan direction from MsgVal (Direction receive Matching Identifier (Identifier Identifier Mask)
matching Message Buffer found, Message Handler checks Hold Control Register this Message Buffer. Hold messsage stored into this Message Buffer. Hold Message Handler stops. both cases MsgLst Control Register this Message Buffer. Hold used "freeze" Receive Buffer inhibit update during read access loss message tolerated. 34/54 manual_message_handler.fm
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Note: Hold only considered Message Handler when NewDat When Message Handler stores message from Core shift register into selected Receive Buffer, only data bytes, whole Identifier Data Length Code stored into this Receive Buffer. Also Message Buffer Configuration Register updated. This implemented keep data bytes connected with identifier even some identifier bits masked out. 6.1.2 FIFO Buffer Hold Control Register Message Buffers used concatenate three Message Buffers form FIFO Buffer. FIFO Buffer identifiers Message Buffers belonging FIFO Buffer have programmed matching values. implicit priority Message Objects, Message Object with lowest number will first Message Object FIFO Buffer. Hold Message Buffers FIFO Buffer, except last, have programmed one. Hold last Message Buffer FIFO Buffer zero. Reception Messages Received messages with identifiers matching FIFO Buffer stored into Message Buffer this FIFO Buffer starting with Message Buffer with lowest message number. When message stored into Message Buffer FIFO Buffer NewDat this Message Buffer set. setting NewDat while Hold Message Buffer locked further write accesses Message Handler until written NewDat back zero. Messages stored into FIFO Buffer until last Message Buffer this FIFO Buffer reached. none preceding Message Objects released writing NewDat zero, further messages this FIFO Buffer will written into last Message Buffer FIFO Buffer (Hold '0') therefore overwrite previous messages. Reading FIFO Buffer assure correct function FIFO Buffer, should read Message Buffers starting Message Buffer with lowest message number. After read Message Buffer write NewDat back zero release Message Buffer. addition check MsgLst last Message Buffer FIFO Buffer detect overflow FIFO Buffer. 6.1.3 Remote Frame After reception Remote Frame Message Handler starts scanning Message Buffers from looking Message Buffer with:
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MsgVal (Direction transmit) Matching Identifier (Identifier, Mask only considered Hold '1')
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matching Message Buffer found, Message Handler proceeds depending actual value Hold Control Register this Message Buffer. Hold bits TxRqst RmtPnd Control Register this Message Buffer request transmission Data Frame. other Message Buffer changed. this case mask used acceptance filtering. Hold Remote Frame stored into Message Buffer bits NewDat 35/54 14.07.99
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User's Manual
RmtPnd set. NewDat still MsgLst signal loss message. this case identifier mask used acceptance filtering. Hold user decide whether wants automatic response Remote Frames wants answer Remote Frame. request Data Frame from remote node TxRqst Control Register Message Buffer with direction receive (Dir '0') one. Transmission queue Message Buffer transmission, bits TxRqst optionally Newdat. NewDat reset when transmission starts. long TxRqst (while MsgVal `1'), data section Message Buffer locked write accesses. After successful transmission NewDat still reset corresponding TxRqst will reset (see figure page figure page 48). more than Message Buffer pending transmission request (TxRqst '1') transmission requests serviced according priority Message Buffers, starting from MB3. shift register Core cell ready loading, Transmit Buffer loaded into Core shift register Message Handler transmission started. module lost arbitration error occured during transmission, message will retransmitted soon free again. meanwhile transmission Message Buffer with higher priority been requested, Message Buffers will transmitted order their priority. Note: different behaviour mode described section 2.7.3 page Handling Interrupts generation module interrupt signal IRQ_B controlled Message Handler. module interrupt enable Control Register. Each interrupt source controls flag Interrupt Flag Register. flags enabled/disabled corresponding enable bits Interrupt Enable Register. enabled interrupt flags or'ed together generate module interrupt. function interrupt flags affected Interrupt Enable Register Control Register. actual value Interrupt Flag Register indicates cause interrupt. When interrupt pending, register will hold value `00h'. read access Interrupt Flag Register will reset flags zero. interrupt line remains active until Interrupt Flag Register read until interrupt sources disabled resetting corresponding enable bits Interrupt Enable Register until global interrupt enable Control Register reset.
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Error Interrupt (Error '1') generated change bits BOff EWarn Status Register. change EPass will never generate Error Interrupt. Status Interrupt (Status '1') generated when Core updated (not necessarily changed) Last Error Code Status Register. update (reset) LEC, write access Status Register never generate reset interrupt.
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User's Manual
Receive Interrupt (RxOk '1') generated Core after successful reception message. This flag independent result acceptance filtering. Transmit Interrupt (TxOk '1') generated after succesful transmission message (error free acknowledged least other node). Message Buffer interrupt flags MB1, when labeled Message Buffers addressed Message Handler. combination with flags RxOk, TxOk bits NewDat, RmtPnd, Hold from Control Register corresponding Message Buffer following events signalled: Reception RxOk NewDat '0': Message Handler stored Data Frame into this Message Buffer. RxOk NewDat '1': Message Handler stored Remote Frame into this Message Buffer. RxOk RmtPnd '1': Remote Frame requested transmission this Message Buffer. Transmission TxOk '1': Successful transmission Data Frame TxOk '0': Successful transmission Remote Frame MsgLst Control Register respecitve Message Buffer set, Hold previous message been overwritten before read Message Buffer.
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Core
Core cell consists Protocol Controller block Shift Register block, shown figure registers except shift register external Core cell (see chapter Registers chapter Message Handler). cell interface designed flexible simple possible with respect integration cell into different environments.
(SCANPATH_ENABLE, _CLK, _INPUT) RESET INIT BIT_TIMING SILENT FEEDBACK TX_REQUEST
Shift Register
TPhase1
transmit
SEND_IDENTIFIER SEND_CONTROL SEND_DATA LOAD_SHIFT_REG Arbitration Control RECEIVED_IDENTIFIER RECEIVED_CONTROL
TPhase2
Data0
TRANSMIT
control
Protocol Controller
_DATA RECEIVE _DATA
Data7
RECEIVED_DATA
RPhase2 RPhase1
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receive
STATUS SYNC_MODE, SAMPLE_POINT TRANSMITTER LOAD_ENABLE
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ID_STABLE TX_COMPLETE STORE_MESSAGE (SCANPATH_OUTPUT)
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Figure Block Diagram Core
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following signals link Core rest module Common System Signals RESET Interface RECEIVE_DATA TRANSMIT_DATA INIT BIT_TIMING STATUS REC, SYNC_MODE SAMPLE_POINT SILENT FEEDBACK Message Handler Interface SEND_IDENTIFIER SEND_CONTROL SEND_DATA LOAD_SHIFT_REGISTER LOAD_ENABLE TX_REQUEST TRANSMITTER TX_COMPLETE RECEIVED_IDENTIFIER RECEIVED_CONTROL RECEIVED_DATA ID_STABLE STORE_MESSAGE Scanpath Interface (optional)
manual_can_core.fm
System Clock Asynchronous Reset Receive Input Transmit Output Internal Initialization Timing Configuration (BRP, SJW, TSEG1, TSEG2) Status Information Error Counters Synchronization Mode Sample Point time Silent Mode Test Mode, concurrently receiving transmissions Identifier transmitted Control Bits transmitted Data Bytes transmitted Load Control Shift Register Load Enable Shift Register Transmission Request Transmitter Flag Transmission successful completed Received Identifier Received Control Bits Received Data Bytes Acceptance Filtering start Received Message valid Enable Scanpath Mode Clock Scanpath Input Scanpath Output Scanpath
Connection Configuration/Status/Test Registers
SCANPATH_ENABLE SCANPATH_CLK SCANPATH_INPUT SCANPATH_OUTPUT
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A_CAN Shift Register
User's Manual
After successful reception message, Shift Register holds complete Message consisting identifier, control field data field. transmit message, Message Handler load Shift Register with message then TX_REQUEST. Shift Register divided into sections enable Message Handler start scanning Message matching identifier, while data field still shifted into Shift Register. reception message subdivided into following three phases: RPhase RPhase Identifier control bits shifted into Arbitration Control section Shift Register. data bytes shifted into Data section Shift Register. Message Handler loads identifier section from Shift Register starts arbitration. match occured Data Frame, Shift Register loaded into respective Message Buffer. match occured Remote Frame, TxRqst flag respective Message Buffer Hold `0') Remote Frame stored into Message Buffer Hold `1')
RPhase
transmission message subdivided into following three phases: TPhase TPhase TPhase Message Handler evaluates TxRqst flags loads Message Buffer with highest priority TxRqst into Shift Register. Arbitration Control section shifted out. Data section shifted out.
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A_CAN Protocol Controller
User's Manual
Protocol Controller implements functionality required perform communication system according Specification Revision Part consists following components: 7.2.1 Stream Processor Stream Processor (BSP) sequencer controlling sequential data stream between Tx/Rx Shift Register, Register, line. also controls gives status information Message Handler such that processes reception, arbitration, transmission, error signalling performed according protocol. 7.2.2 Cyclic Redundancy Checker This block generates Cyclic Redundancy Check (CRC) code transmitted after data bytes checks code incoming messages. This done dividing data stream code generator polynomial. 7.2.3 Error Management Logic Error Management Logic (EML) responsible fault confinement device. counters, Receive Error Counter (REC) Transmit Error Counter (TEC), incremented decremented commands from Stream Processor. According values error counters, controller into states error active, error passive busoff. Protocol Controller error active, both error counters below error passive limit 128. error passive, least error counters equals exceeds 128. goes busoff, Transmit Error Counter equals exceeds busoff limit 256. device remains this state, until busoff recovery sequence finished (see Specification Rev. 2.0). Additionally, there EWarn Status Register, which set, least error counters equals exceeds error warning limit EWarn reset, both error counters less than error warning limit. 7.2.4 Timing Logic
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Timing Logic (BTL) monitors busline input CAN_RX handles busline related timing according protocol. synchronises recessive dominant busline transition Start Frame (Hard Synchronisation) further recessive dominant busline transition, controller itself does transmit dominant (Resynchronisation). also provides programmable time segments compensate propagation delay time phase shifts define position Sample Point time. programming depends baudrate, module clock frequency external physical delay times.
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Application
Timing According Specification, time subdivided four segments:
Synchronisation Segment, SYNC_SEG Propagation Time Segment, PROB_SEG Phase Buffer Segment1, PB1, PHASE_SEG1 Phase Buffer Segment2, PB2, PHASE_SEG2
Each segment multiple Time Quantum length these segments programmable, with exception Synchronisation Segment, which always long. this application, Synchronisation Segment represented tSync, Phase Buffer Segment2 represented tTSeg2, while tTSeg1 summation Propagation Time Segment Phase Buffer Segment1.
time tSync
tTSeg1
tTSeg2
tSync
time quantum Figure Timing
Sample Point
Transmit Point
8.1.1 Definition Time Segments
manual_can_application.fm
time determined module clock period tSCLK, Baud Rate Prescaler, number time quanta bit: time tSync-Seg tTSeg1 tTSeg2 tSync-Seg tTSeg1 tTSeg2 TSeg1 TSeg2 tSCLK
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Time Segments TSeg1, TSeg2, Baud Rate Prescaler programmed numerical values from Timing Register.
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8.1.2 Hard Synchronisation Resynchronisation compensate phase shifts between clock oscillators different controllers, controller synchronize edge from recessive dominant level, edge lies between Sample Point next Synchronisation Segment, other edge, itself does send dominant level. Hard Synchronisation enabled Start Frame), time restarted Synchronisation Segment, otherwise, Resynchronisation Jump Width defines maximum number time quanta time shortened lengthened Resynchronisation. Resynchronisation Jump Width programmable field Timing Register range actual value tSJW tSJW
8.1.3 Calculation Time programming time regard Specification Rev. depends desired baudrate, A_CAN module clock frequency SCLK external physical delay times driver, line input comparator. delay times summarised Propagation Time Segment, actual value tProp tProp times maximum physical delay, input comparator delay, output driver delay rounded nearest multiple
fulfil requirements specification, following conditions must tTSeg2 Information Processing Time tTSeg2 tSJW tTSeg1 tTSeg1 tSJW tProp Note: order achieve correct operation according protocol total time should least i.e. TSeg1 TSeg2 programmed Timing Register) operate with baudrate MBit/s, frequency SCLK least MHz. maximum tolerance SCLK depends Phase Buffer Segment1 PB1, Phase Buffer Segment2 PB2, Resynchronisation Jump Width SJW:
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time time
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A_CAN Examples
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8.2.1 Example Timing high Baudrate this example, frequency SCLK MHz, bitrate MBit/s. delay driver delay receiver circuit delay line (40m) tProp tSJW tTSeg1 tTSeg2 tSync-Seg time tolerance SCLK 1000 0.39 tSCLK
tProp tSJW Information Processing Time tSync-Seg tTSeg1 tTSeg2
time 0.1µ 0.2µ
8.2.2 Example Timing Baudrate this example, frequency SCLK MHz, bitrate KBit/s. delay driver delay receiver circuit delay line (40m) tProp tSJW tTSeg1
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1.58
tSCLK
tProp tSJW Information Processing Time tSync-Seg tTSeg1 tTSeg2
tTSeg2 tSync-Seg time tolerance SCLK
time
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A_CAN Handling Receive Buffers
User's Manual
Power
reset values
Identifier application specific (value transmitter) MBxIE application specific Initialisation TxRqst RmtPnd Hold MsgLst NewDat MsgVal
Hold
NewDat Process Message process message
process message NewDat
NewDat
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MsgLst
exception handling MsgLst
request update
TxRqst
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Figure handling valid Receive Buffer
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REMOTE
DATA idle
TxRqst=1
received frame with matching identifier this message object
NewDat load identifier control into buffer
NewDat
send remote frame
MsgLst
Hold
transmission successful?
TxRqst RmtPnd
store message NewDat TxRqst RmtPnd
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MBxIE
MBxIE
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Figure Controller handling Receive Buffer
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A_CAN Handling Transmit Buffers
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Power
reset values
Identifier application specific application specific MBxIE application specific Initialisation TxRqst RmtPnd Hold MsgLst NewDat MsgVal
TxRqst=1
discard unsent message
write data bytes
Update Data Field
TxRqst
NewDat
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want send TxRqst
update message
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Figure handling Transmit Buffer with Hold
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DATA
REMOTE free
TxRqst=1
received remote frame with matching identifier
NewDat load message into shift register
Hold (mask used?)
send message
TxRqst RmtPnd
NewDat
transmission successful?
MsgLst
NewDat=1
TxRqst
store message NewDat TxRqst RmtPnd
RmtPnd
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MBxIE
MBxIE
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Figure Controller handling valid Transmit Buffer with automatic retransmission
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DATA
REMOTE free
TxRqst=1
received remote frame with matching identifier
TxRqst load message into shift register
Hold (mask used?)
send message
TxRqst RmtPnd
NewDat
transmission successful?
MsgLst
NewDat RmtPnd
store message NewDat TxRqst RmtPnd
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MBxIE
MBxIE
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Figure Controller handling valid Transmit Buffer mode
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Timings
minimum clock frequency SCLK required operated A_CAN module with bitrate MBit/s MHz. maximum clock frequency dependent synthesis constraints technology which used synthesis. Electrical Interface Signal SCLK RESET_B RE_B WE_B CS_B ADDR(7:0) DATA(7:0) IRQ_B CAN_RX CAN_TX Direction INOUT Module Clock Asynchronous Module Reset, active External Read, active External Write, active Module Select, module selected Address Data Bus, three state bidirectional data signals Module Interrupt, level sensitive, active Receive Data Input Transmit Data Output Function
Table List Module Pins
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A_CAN Timing Considerations 9.2.1 Read Write Timings
User's Manual
following figures show Read Write timings 8-bit non-multiplex module interface.
tcyc SCLK ADDR(5:0) CS_B tdsr DATA(7:0) tddrp tddrp RE_B tdhrp tdhr tdhcs tdhad
Figure Read access A_CAN module.
tcyc SCLK ADDR(5:0)
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tdhcs tdhad
CS_B tddwp tddwp WE_B tdsw tddw DATA(7:0) tdhw tdhwp
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Figure Write access A_CAN module.
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timings listed table below valid with module clock SCLK
Characteristic Cycle Time SCLK valid External Address SCLK valid Chip-Select External Address Hold Time Chip-Select Hold Time Read Data Setup Time Read Data Hold Time Valid Address Read Enable Read Enable Pulse Width Read Enable Hold Time Valid Address Write Enable Write Enable Pulse Width Write Enable Hold Time Write Data Delay Time Write Data Setup Time Write Data Hold Time Table Module Interface timings
Symbol tcyc tdhad tdhcs tdsr tdhr tddrp tdhrp tddwp tdhwp tddw tdsw tdhw
Unit
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A_CAN 9.2.2 Interrupt Timing
User's Manual
Figure shows timing modules interrupt IRQ_B.
SCLK
IRQ_B
Enabled Interrupt Flag while
Read Status Register write
Figure Timing interrupt output signal IRQ_B.
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Appendix
10.1 List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Block Diagram A_CAN A_CAN Register Core Loop Back Mode Core Silent Mode Core Loop Back combined with Silent Mode Structure module interface Message Buffer Identifier Mask Block Diagram Core Timing handling valid Receive Buffer Controller handling Receive Buffer handling Transmit Buffer with Hold Controller handling valid Transmit Buffer with automatic retransmission Controller handling valid Transmit Buffer mode Read access A_CAN module. Write access A_CAN module. Timing interrupt output signal IRQ_B.
10.2 List Tables Table Table Table
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A_CAN Address List Module Pins Module Interface timings
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User's Manual 14.07.99 K8/EIS Klose-2969 manual_cover.f

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