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S/UNI-2488 Telecom Standard Product Datasheet Releas
Proprietary Confidential Released Issue June 2002
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
SATURN USER NETWORK INTERFACE 2488 M/BITS
Datasheet
S/UNI-2488
PM5381
S/UNI-2488 Telecom Standard Product Datasheet Releas
2002 PMC-Sierra, Inc.
Disclaimer
Patents
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
U.S. Patent Numbers: 5,606,563; 5,640,398; 5,835,602; 5,883,545; 6,052,073; 6,054,884; 6,150,965; 6,188,692; 6,301,318 Canadian Patent Numbers: 2,149,076; 2,159,763; 2,161,921; 2,194,919; 2,226,610; 2,227,097 U.K. Patent Number 2,290,438 Other relevant patent grants also exist.
technology discussed protected more following patent grants:
Grant
S/UNI SATURN registered trademarks PMC-Sierra, Inc. POS-PHY Level PMC-Sierra trademarks PMC-Sierra, Inc.
Trademarks
event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage.
None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement.
PMC-2000489 (R4)
information proprietary confidential PMC-Sierra, Inc., customers' internal use. event, cannot reproduce part this document, form, without express written consent PMC-Sierra, Inc.
Copyright
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S/UNI-2488 Telecom Standard Product Datasheet Releas
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Site: http://www.pmc-sierra.com
Tel: +1(604) 415-6000 Fax: +1(604) 415-6200
PMC-Sierra 8555 Baxter Place Burnaby, Canada
Contacting PMC-Sierra
S/UNI-2488 Telecom Standard Product Datasheet Releas
Issue
Added typical jitter specs. Added jitter transfer graphs.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Changed 2.97V 3.14V. Modified FRlvds specs. Modified thermal resistance values. Modified junction-to-top thermal resistance. Upated Patent list. Changed "POS" "POS-PHY' numerous places more accurately reference interface rather than Packet Over SONET. register 0x0080, A2A2EN, Z0DEF, J0Z0INCEN descriptions were corrected refer TRMP Aux4 Configuration register instead TRMP Aux1 Configuration register. features list, change SONET/SDH signal defect/fail byte instead byte. Change "erred" "errored" "erroneous" throughout document. TTOH RTOH overhead descriptions modified state bytes including undefined ones included.
Removed Ambient Temperature under Bias.
Removed note about single-ended PECL from "Notes Description".
Updated REFCLK_P/N description.
Modified TX2488_MODE[2:0] register configuration descriptions register 0x0020.
Updated jitter tolerance graph.
Modified register descriptions ARSTB, TXLV_ENB, APISO_ENB registers 0x0865, 0x086D, 0x0875, 0x087D.
Modified register descriptions A_RSTB, RX_ENB, DRU_ENB registers 0x0843, 0x084B, 0x0853, 0x085B.
Removed references TSTSI register 0x0004. Replaced TSTSI with PRGM.
Modified INTE[4:1] register desriptions registers 0x0005, 0x0006, 0x0007. Changed TPRGM PRGM.
Modified block diagrams Section Replaced STSI block with Frame Counter block.
Corrected RRMP framing algorithm description paragraph Section 10.3 Receive Regenerator Multiplexer Processor (RRMP).
June, 2002
Document issued production release Revision device. Removed reference FIFO_CLOCK LINE_LOOP_BACK register description register 0x0013.
Issue
Issue Date
Details Change
Detailed Revision History
S/UNI-2488 Telecom Standard Product Datasheet Releas
Corrected RVAL description. Corrected description.
Issue
April 2002
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Modified C0_CRU/C1_CRU C0_CSU/C1_CSU description state that external capacitors required configurations.
Document issued Revision device. Filled Loopback description Operations Section. Updated mechanical diagram. Added 2.488Gb/s output jitter specs. Added registers 0x0900 0x90F. Changed device code JTAG register Added Timing SONET Overhead signals. Added typical timing. Reduced ECL/PECL output levels match 2.5G transmitter. Added statement recommend setting CSU_MODE[2] register register 0x0021 logic optimal non-loop-timed intrinsic jitter performance.
register 0x780 must logic improve output propagation time meet timing specification.
Modified INVCNT description state must logic SONET compliant behaviour.
Changed ILLPTR register Unused. register RHPP Indirect Register
Added RHPP's status bits (NEWPTR, ILLJREQ, PAISV, PLOPV, NDF, INVNDF, DISCOPA) indicate they only valid master timeslots.
Modified RPAISINS_EN register description register 0x0902 indicate PAIS asserted detection LAIS, PAIS, using this register bit.
Changed default state TRAIN, DOOLV, ROOLV register 0x0013 `X'.
Updated functional timing diagrams APSI APSO links Section 14.1, Incoming Serial TelecomBus, 14.2, Outgoing Serial TelecomBus.
Updated limit maximum allowable skew between links Section 14.1, Incoming Serial TelecomBus.
Modified description remove erroneous info regarding early deassertion bytes available FIFO).
Modified device register 0x0000 JTAG description.
Added pull-up resistance input pads with pull-ups kOhm).
Change TRSTB description "TRSTB must asserted some point after power before device registers accessed."
Issue
Issue Date
Details Change
S/UNI-2488 Telecom Standard Product Datasheet Releas
Removed DC-offset self narrowbanding modes.
Added jitter requirement APSIFPCLK.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Added comments about lock-up conditions. Added comment register 0038H logic Removed registers 0x20E 0x2F from register map. Removed TSLDEL register bit. Removed statement about input pins. Modified microprocessor timing diagrams include WCIMODE feature. Modified statement regarding control circuitry SONET wander transfer, holdover, stability. Included reset start-up procedure overcome potential pmon counter lock-up condition RHPPs SDQs. Enhanced desription K.28.0 character serial TeleCombus mapping Sections 13.1.10 13.1.11. Added statement Section 13.2 that states that consequential action asserting RDI-P supported. Updated signal description state that only valid OC48c
Added typical jitter numbers RCLK TCLK descriptions.
Updated analog power supply filtering.
Highlighted need assert SARC's PAISPTREN enable AIS-P consequential actions.
Added Section 13.17 describe using SARC.
Added Z0DEF register must logic
TXPHY's INBANDADDR register renamed Reserved0 added comment that default value logic must cleared logic proper operation.
Corrected CRU_CLOCK description register 0x010 reference register 0x010 instead 0x00.
Removed CSU_CLOCK register register 0x0010. unused since permanently reset bypassed.
Modified FSBEN register THPP Control Register (indirect register identify which timeslots valid.
Updated internal resistance values descriptions CRU2488 CSU2488 that selected CRU_MODE CSU_MODE register bits.
Changed recommended external capacitor value 10nF external capacitor value 100nF.
G1[7:0] register bits THPP Transmit Mask register reference SRCG1 register enabling rather than SRCREI SRCRDI bits.
Added minimum RSTB pulse width timing section.
Issue
Issue Date
Details Change
S/UNI-2488 Telecom Standard Product Datasheet Releas
Included SVCA indirect register access description Section 13.19.
Normal mode registers updated with final EngDocs. Updated functional descriptions. Register Memory updated Added JTAG Test Port section.
Added Boundary Scan Cells section. Added UL3/PL3 associated info Operations Functional Timing sections. Added operations PRGM, indirect register access, PMON servicing, interrupt servicing. Modified analog interfacing information register descriptions. Also revised Characteristics section AVDH, VDDO, QAVD typical values read +/-5% Vvddo, Vqavd values read 3.14 min/3.47
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
March 2000
Document Created.
Description tables updat
Diagram insert
Definition table
June 2001
Document issued Revision device.
Enhanced Diag_NDFREQ register description state that this should asserted cleared whenever corresponding SVCA timeslots reconfigured.
Commented that SVCA's PJPMON NJPMON counters values only valid master timeslots.
mode operation.
Issue
Issue Date
Details Change
S/UNI-2488 Telecom Standard Product Datasheet Releas
Trademarks Contacting PMC-Sierra Table Contents List Tables Features SONET Section Line Regenerator Multiplexer Section Receive AProcessor Transmit AProcessor Transmit Processor.
Applications References Application Examples Block Diagram Description Diagram. Serial Line Side Interface Signals Clocks Alarms (7). Receive Section/Line/Path Overhead Extraction Signals Transmit Section/Line/Path Overhead Insertion Signals System Side UTOPIA POS-PHY Signals (84). Serial Data Interface (20) Microprocessor Interface Signals (37).
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Description
Receive Processor.
SONET Path High Order Path
General
Definitions.
List Figures.
Detailed Revision History
Patents
Disclaimer
Copyright.
Legal Information
Table Contents
S/UNI-2488 Telecom Standard Product Datasheet Releas
JTAG Test Access Port (TAP) Signals (5). Analog Miscellaneous Signals (10)
9.11.2 Connects Functional Description. 10.2 SONET/SDH Receive Line Interface (SRLI) 10.4 Receive Tail Trace Processor (RTTP) 10.5.1 Pointer Interpreter. 10.5.3 Error Monitoring. 10.6.1 Elastic Store. 10.6.2 Pointer Generator 10.7 Receive Cell Frame Processor (RCFP). 10.7.1 ACell Delineation 10.7.2 ADescrambler 10.7.3 ACell Filter 10.7.4 APerformance Monitor. 10.7.5 Overhead Removal 10.7.6 Descrambler. 10.7.8 Byte Destuffing.
10.8 Receive Scalable Data Queue (RXSDQ) 10.8.1 Receive AFIFO 10.8.2 Receive FIFO.
10.9 Receive Interface (RXPHY).
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
10.7.9 Check. 10.7.10 .POS Performance Monitor
10.7.7 PPP/HDLC Frame Delineation
10.6 SONET/SDH Virtual Container Aligner (SVCA).
10.5.2 Concatenation Pointer Interpreter State Machine
10.5 Receive High Order Path Processor (RHPP)
10.3 Receive Regenerator Multiplexer Processor (RRMP).
10.1 Receive Line Interface
9.12 Summary
9.11.1 Digital Ground.
9.11 Digital Power Ground.
9.10 Analog Power Ground (105).
S/UNI-2488 Telecom Standard Product Datasheet Releas
10.9.1 Receive UTOPIA Level Interface. 10.9.2 Receive POS-PHY Level 10.10 Transmit Line Interface 10.12 Transmit Regenerator Multiplexer Processor (TRMP) 10.13 Transmit Tail Trace Processor (TTTP). 10.15 Transmit Cell Frame Processor (TCFP) 10.14 Transmit High Order Path Processor (THPP) 10.15.1 AIdle/Unassigned Cell Generator
10.17 Transmit Interfaces (RXPHY TXPHY) 10.17.1 Transmit UTOPIA Level Interface
10.18 SONET/SDH Error Rate Monitor (SBER) 10.19 SONET/SDH Alarm Reporting Controller (SARC). 10.20 SONET/SDH Inband Error Report Processor (SIRP). 10.21 Serial Data Interface. 10.21.1 Output Serial Data Interface (T8TE, APISO, TXLV) 10.21.2 Input Serial Data Interface (RXLV, DRU, R8TD)
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
10.17.2 Transmit POS-PHY Level Interface
10.16.2 Transmit FIFO
10.16.1 .Transmit AFIFO
10.16 Transmit Scalable Data Queue (TXSDQ).
10.15.7 Data Scrambling
10.15.6 Byte Stuffing
10.15.5 Generator
10.15.4 .POS PPP/HDLC Frame Generator
10.15.3 .AHCS Generator
10.15.2 AScrambler
10.11 SONET/SDH Transmit Line Interface (STLI)
S/UNI-2488 Telecom Standard Product Datasheet Releas
12.1 Master Test Test Configuration Registers.
Operation. 13.1.1 LVDS Overview 13.1.2 LVDS Receiver (RXLV). 13.1.3 Data Recovery Unit (DRU) 13.1.4 Receive 8B/10B TelecomBus Decoder (R8TD). 13.1.5 Transmit 8B/10B TelecomBus Encoder (T8TE) 13.1.6 Parallel Serial Converter (APISO). 13.1.8 Character Alignment 13.1.10 .Character Decode 13.1.11 Character Encode 13.1.12 Serial TelecomBus Modes 13.2 Cross Connect Mode Operation 13.3 SONET/SDH Frame Mappings Overhead Byte Usage 13.1.7 LVDS Transmitter (TXLV) 13.1.9 Frame Alignment
13.4 ACell Data Structure 13.5 POS/HDLC Data Structure 13.5.1 Limitation When Using Externally Generated STS-48c Mode 13.5.2 Limitations From Small Packets
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
13.3.1 AMapping 13.3.2 Packet Over SONET Mapping. 13.3.3 Transport Path Overhead Bytes
13.1 Serial TelecomBus (LVDS) Operation
12.3 Boundary Scan Cells
12.2 JTAG Test Port.
Test Features Description
Normal Mode Register Description
10.23 Microprocessor Interface
10.22 JTAG Test Access Port Interface
10.21.4 .Clock Synthesis Unit (CSU)
10.21.3 LVDS Transmit Reference (TXREF)
S/UNI-2488 Telecom Standard Product Datasheet Releas
13.6 TXSDQ RXSDQ "Block" Sub-Units 13.7 TXSDQ Buffer Available Operation 13.9 Setting AMode Operation over Utopia POS-PHY 13.11 Setting Transparent Mode Operation Over POS-PHY 13.12.1 TPAHOLD 13.8 RXSDQ TXSDQ Data Available Burst-Size Operation
13.13 System Interface Error Recovery 13.13.1 Utopia Level Transmit Interface Misalignment Recovery 13.13.2 Utopia Level Receive Interface Misalignment Recovery
POS-PHY Level Receive (RFCLK) Error Recovery. 13.14 Using SONET/SDH Inband Error Report Processor (SIRP) 13.15 Using PRBS Generator Monitor (PRGM) 13.15.1 Synchronization
13.16 Using SONET/SDH Error Rate Alarm Monitor (SBER) 13.17 Using SONET/SDH Alarm Reporting Controller (SARC) 13.17.1 SARC Indirect Register Access 13.17.2 STS-48c Operation 13.17.3 Sub-STS-48c Operation
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
13.18 Interrupt Service Routine 13.19 Accessing Indirect Registers 13.20 Using Performance Monitoring Features.
13.15.2 Error Detection Accumulation
POS-PHY Level Transmit (TFCLK) Error Recovery
13.13.4 Utopia Level Receive Clock (RFCLK) Error Recover
13.13.3 .Utopia Level Transmit Clock (TFCLK) Error Recovery
13.12.2 TPAHOLD
13.12 Transmit DTPA Behavior
13.10 Setting Packet Mode Operation Over POS-PHY
S/UNI-2488 Telecom Standard Product Datasheet Releas
13.21 Loopback Operation 13.22 Required Reset Sequence 13.23 JTAG Support
14.4.1 Transmit Interface 14.4.2 Receive Interface 14.5 Overhead Extraction Insertion 14.5.1 Transport Overhead Extraction 14.5.2 Transport Overhead Insertion. 14.5.3 Path Overhead Extraction 14.5.4 Path Overhead Insertion. 14.6 SONET Alarm Indication Signal. Power Information 16.2 Power Sequencing. Absolute Maximum Ratings 16.1 Power Requirements 16.3 Power Supply Filtering. D.C. Characteristics A.C. Timing Characteristics
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
18.1 Microprocessor Interface Timing Characteristics 18.2 Reset Pulse Width Timing Characteristics.
14.4 Packet over SONET (POS-PHY) Level System Interface.
14.3.2 Receive Interface
14.3.1 Transmit Interface
14.3 AUTOPIA Level 3System Interface.
14.2 Outgoing Serial TelecomBus
14.1 Incoming Serial TelecomBus
Functional Timing
13.26 Termination Scheme
Output Levels.
13.24 Interfacing PECL Devices.
13.23.3 .Instructions
13.23.2 States
13.23.1 .TAP Controller
S/UNI-2488 Telecom Standard Product Datasheet Releas
18.3 Receive System Interface Timing Characteristics 18.4 Transmit System Interface Timing Characteristics 18.5 SONET/SDH Overhead Interface Timing Characteristics
18.8 JTAG Port Interface Timing Characteristics. Thermal Information
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Mechanical Information
Ordering Information
18.7 OC-48 Interface Timing Characteristics.
18.6 Port Interface Timing Characteristics
S/UNI-2488 Telecom Standard Product Datasheet Releas
Register 0003H: S/UNI-2488 Clock Monitors Register 0005H: S/UNI-2488 Master Interrupt Status Register 0007H: S/UNI-2488 Master Interrupt Status Register 0009H: S/UNI-2488 Master Interrupt Status Register 000BH: Software General Purpose (FREE[12:0]) Register Register 000DH: Reserved Register 000FH: S/UNI-2488 Identification Register Register 0011H: Rx2488 Analog Interrupt Control Register 0012H: Rx2488 Analog Control Register 0013H: Rx2488 Analog Clock Training Configuration Status. Register 0014H: Rx2488 Analog PRBS Control Register 0015H: Rx2488 Reserved Register 0020H: Tx2488 Analog Control/Status Register 0021H: TX2488 Control Register 0022H: TX2488 Pattern Register Register 0031H: SRLI Clock Configuration Register 0039H: STLI Clock Configuration. Register 0040H: RRMP Configuration Register 0050H: RRMP Aux2 Configuration Register 0060H: RRMP Aux3 Configuration Register 0070H: RRMP Aux4 Configuration. Register 0041H: RRMP Status Register 0042H: RRMP Interrupt Enable.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Register 0038H: STLI Clock Configuration
Register 0030H: SRLI Clock Configuration
Register 0010H: Rx2488 Analog Interrupt Status.
Register 000EH: S/UNI-2488 Diagnostics
Register 000CH: Input TelecomBus Synchronization Delay
Register 000AH: S/UNI-2488 Master Interrupt Status
Register 0008H: S/UNI-2488 Master Interrupt Status
Register 0006H: S/UNI-2488 Master Interrupt Status
Register 0004H: S/UNI-2488 Master Interrupt Status
Register 0002H: S/UNI-2488 Transmit Control Register
Register 0001H: S/UNI-2488 Master Reset, Configuration, Loopback
Register 0000H: S/UNI-2488 Identity Global Performance Monitor Update.
List Registers
S/UNI-2488 Telecom Standard Product Datasheet Releas
Register 0043H: RRMP Interrupt Status. Register 0044H: RRMP Receive Register 0046H: RRMP Enable Register 0056H: RRMP Aux2 Enable Register 0066H: RRMP Aux3 Enable Register 0076H: RRMP Aux4 Enable Register 0048H: RRMP Line Error Counter (LSB). Register 0049H: RRMP Line Error Counter (MSB). Register 004AH: RRMP Line Error Counter (LSB) Register 0080H: TRMP Configuration Register 0082H: TRMP Error Insertion Register 0083H: TRMP Transmit Register 0084H: TRMP Transmit Register 0085H: TRMP Transmit D1D3 D4D12 Register 0086H: TRMP Transmit Register 0087H: TRMP Transmit Register 0089H: TRMP Transmit Mask. Register 00A0H: TRMP Aux2 Configuration Register 00C0H: TRMP Aux3 Configuration Register 00E0H: TRMP Aux4 Configuration. Register 00A1H: TRMP Register Insertion Register 00C1H: TRMP Register Insertion Register 00E1H: TRMP Register Insertion Register 00A2H: TRMP Aux2 Error Insertion Register 00C2H: TRMP Aux3 Error Insertion Register 00E2H: TRMP Aux4 Error Insertion Register 0088H: TRMP Transmit Register 008A: TRMP Transmit Mask Register 0045H: RRMP Receive SSM.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Register 00A8H: TRMP Transmit Register 00C8H: TRMP Transmit Register 00E8H: TRMP Transmit Register 0100H: SBER Configuration. Register 0101H: SBER Status Register 0102H: SBER Interrupt Enable.
Register 0103H: SBER Interrupt Status.
Register 00A7H: TRMP Transmit Register 00C7H: TRMP Transmit Register 00E7H: TRMP Transmit
Register 00A3H: TRMP Aux2 Transmit Register 00C3H: TRMP Aux3 Transmit Register 00E3H: TRMP Aux4 Transmit
Register 0081H: TRMP Register Insertion.
Register 004BH: RRMP Line Error Counter (MSB)
Register 0047H: RRMP Section Error Counter.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Register 0104H: SBER BERM Accumulation Period (LSB). Register 0105H: SBER BERM Accumulation Period (MSB). Register 0107H: SBER BERM Saturation Threshold (MSB) Register 0109H: SBER BERM Declaring Threshold (MSB). Register 010BH: SBER BERM Clearing Threshold (MSB) Register 010DH: SBER BERM Accumulation Period (MSB). Register 010FH: SBER BERM Saturation Threshold (MSB). Register 0111H: SBER BERM Declaring Threshold (MSB) Register 0113H: SBER BERM Clearing Threshold (MSB) Register 0131H: RTTP SECTION Indirect Data Register 0132H: RTTP SECTION Trace Unstable Status. Register 0133H: RTTP SECTION Trace Unstable Interrupt Enable Register 0134H: RTTP SECTION Trace Unstable Interrupt Status Register 0135H: RTTP SECTION Trace Mismatch Status. Register 0136H: RTTP SECTION Trace Mismatch Interrupt Enable Register 0137H: RTTP SECTION Trace Mismatch Interrupt Status Indirect Register 00H: RTTP SECTION Trace Configuration Indirect Register 7FH: RTTP SECTION Captured Trace. Indirect Register FFH: RTTP SECTION Expected Trace. Register 0139H: TTTP SECTION Indirect Data Register 0106H: SBER BERM Saturation Threshold (LSB) Register 0108H: SBER BERM Declaring Threshold (LSB). Register 010AH: SBER BERM Clearing Threshold (LSB) Register 010CH: SBER BERM Accumulation Period (LSB). Register 010EH: SBER BERM Saturation Threshold (LSB). Register 0110H: SBER BERM Declaring Threshold (LSB) Register 0112H: SBER BERM Clearing Threshold (LSB) Register 0130H: RTTP SECTION Indirect Address
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Indirect Register 00H: TTTP SECTION Trace Configuration Indirect Register 7FH: TTTP SECTION Trace Register 0200H: RHPP STS-1/STM-0 through Indirect Address Register 0280H: RHPP STS-1/STM-0 through Indirect Address Register 0300H: RHPP STS-1/STM-0 through Indirect Address Register 0380H: RHPP STS-1/STM-0 through Indirect Address.
Register 0138H: TTTP SECTION Indirect Address
Indirect Register BFH: RTTP SECTION Accepted Trace
S/UNI-2488 Telecom Standard Product Datasheet Releas
Indirect Register 02H: RHPP Pointer Value ERDI. Indirect Register 04H: RHPP Expected Indirect Register 06H: RHPP Path Error Counter Indirect Register 08H: RHPP Path Negative Justification Event Counter Register 0202H, 0282H, 0302H 0382H: RHPP Payload Configuration Register 0204H, 0284, 0304, 0384: RHPP Path Interrupt Status. Register 0205H, 0285, 0305, 0385: RHPP Pointer Concatenation Processing Disable. Register 0208H, 0210H, 0218H, 0220H, 0228H, 0230H, 0238H, 0240H, 0248H, 0250H, 0258H, 0260H Register 0288H, 0290H, 0298H, 02A0H, 02A8H, 02B0H, 02B8H, 02C0H, 02C8H, 02D0H, 02D8H, 02E0H Register 0308H, 0310H, 0318H, 0320H, 0328H, 0330H, 0338H, 0340H, 0348H, 0350H, 0358H, 0360H Register 0388H, 0390H, 0398H, 03A0H, 03A8H, 03B0H, 03B8H, 03C0H, 03C8H, 03D0H, 03D8H, 03E0H: RHPP STS-1/STM-0 (Where Pointer Interpreter Status Register 0209H, 0211H, 0219H, 0221H, 0229H, 0231H, 0239H, 0241H, 0249H, 0251H, 0259H, 0261H Register 0289H, 0291H, 0299H, 02A1H, 02A9H, 02B1H, 02B9H, 02C1H, 02C9H, 02D1H, 02D9H, 02E1H Register 0309H, 0311H, 0319H, 0321H, 0329H, 0331H, 0339H, 0341H, 0349H, 0351H, 0359H, 0361H Register 0389H, 0391H, 0399H, 03A1H, 03A9H, 03B1H, 03B9H, 03C1H, 03C9H, 03D1H, 03D9H, 03E1H: RHPP STS-1/STM-0 (where Pointer Interpreter Interrupt Enable Register 020AH, 0212H, 021AH, 0222H, 022AH, 0232H, 023AH, 0242H, 024AH, 0252H, 025AH, 0262H Register 028AH, 0292H, 029AH, 02A2H, 02AAH, 02B2H, 02BAH, 02C2H, 02CAH, 02D2H, 02DAH, 02E2H Register 030AH, 0312H, 031AH, 0322H, 032AH, 0332H, 033AH, 0342H, 034AH, 0352H, 035AH, 0362H Register 038AH, 0392H, 039AH, 03A2H, 03AAH, 03B2H, 03BAH, 03C2H, 03CAH, 03D2H, 03DAH, 03E2H: RHPP STS-1/STM-0 (where Pointer Interpreter Interrupt Status
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Register 0203H, 0283, 0303, 0383: RHPP Counters Update
Indirect Register 09H: RHPP Path Positive Justification Event Counter
Indirect Register 07H: RHPP Path Error Counter.
Indirect Register 05H: RHPP Pointer Interpreter Status.
Indirect Register 03H: RHPP Captured Accepted
Indirect Register 01H: RHPP Error Monitor Configuration.
Indirect Register 00H: RHPP Pointer Interpreter Configuration.
Register 0201H: RHPP STS-1/STM-0 through Indirect Data Register 0281H: RHPP STS-1/STM-0 through Indirect Data Register 0301H: RHPP STS-1/STM-0 through Indirect Data Register 0381H: RHPP STS-1/STM-0 through Indirect Data
S/UNI-2488 Telecom Standard Product Datasheet Releas
Register 0402: THPP Payload Configuration Indirect Register 01H: THPP Source Pointer Control Register Indirect Register 05H: THPP Transmit Indirect Register 06H: THPP Transmit Mask (TG1H4POH). Indirect Register 07H: THPP Transmit (TF2Z3POH)
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Indirect Register 08H: THPP Transmit Overhead (TZ4Z5POH) Register 0600H, 0620H, 0640H, 0660H: SVCA Indirect Address Register 0601H, 0621H, 0641H, 0661H: SVCA Indirect Data. Register 0602H, 0622H, 0642H, 0662H: SVCA Payload Configuration Register
Indirect Register 04H: THPP Fixed Stuff Byte Mask (TFSB)
Indirect Register 00H: THPP Control Register
Register 0401H: THPP STS-1/STM-0 through Indirect Data Register 0481H: THPP STS-1/STM-0 through Indirect Data Register 0501H: THPP STS-1/STM-0 through Indirect Data Register 0581H: THPP STS-1/STM-0 through Indirect Data
Register 0400H: THPP STS-1/STM-0 through Indirect Address Register 0480H: THPP STS-1/STM-0 through Indirect Address Register 0500H: THPP STS-1/STM-0 through Indirect Address Register 0580H: THPP STS-1/STM-0 through Indirect Address.
Register 020DH, 0215H, 021DH, 0225H, 022DH, 0235H, 023DH, 0245H, 024DH, 0255H, 025DH, 0265H Register 028DH, 0295H, 029DH, 02A5H, 02ADH, 02B5H, 02BDH, 02C5H, 02CDH, 02D5H, 02DDH, 02E5H Register 030DH, 0315H, 031DH, 0325H, 032DH, 0335H, 033DH, 0345H, 034DH, 0355H, 035DH, 0365H Register 038DH, 0395H, 039DH, 03A5H, 03ADH, 03B5H, 03BDH, 03C5H, 03CDH, 03D5H, 03DDH, 03E5H: RHPP STS-1/STM-0 (where Error Monitor Interrupt Status
Register 020CH, 0214H, 021CH, 0224H, 022CH, 0234H, 023CH, 0244H, 024CH, 0254H, 025CH, 0264H Register 028CH, 0294H, 029CH, 02A4H, 02ACH, 02B4H, 02BCH, 02C4H, 02CCH, 02D4H, 02DCH, 02E4H Register 030CH, 0314H, 031CH, 0324H, 032CH, 0334H, 033CH, 0344H, 034CH, 0354H, 035CH, 0364H Register 038CH, 0394H, 039CH, 03A4H, 03ACH, 03B4H, 03BCH, 03C4H, 03CCH, 03D4H, 03DCH, 03E4H: RHPP STS-1/STM-0 (where Error Monitor Interrupt Enable
Register 020BH, 0213H, 021BH, 0223H, 022BH, 0233H, 023BH, 0243H, 024BH, 0253H, 025BH, 0263H Register 028BH, 0293H, 029BH, 02A3H, 02ABH, 0283H, 02BBH, 02C3H, 02CBH, 02D3H, 02DBH, 02E3H Register 030BH, 0313H, 031BH, 0323H, 032BH, 0333H, 033BH, 0343H, 034BH, 0353H, 035BH, 0363H Register 038BH, 0393H, 039BH, 03A3H, 03ABH, 03B3H, 03BBH, 03C3H, 03CBH, 03D3H, 03DBH, 03E3H: RHPP STS-1/STM-0 (where Error Monitor Status.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Register 0704H: RTTP PATH Trace Unstable Interrupt Status. Register 0705H: RTTP PATH Trace Mismatch Status Register 0706H: RTTP PATH Trace Mismatch Interrupt Enable. Register 0707H: RTTP PATH Trace Mismatch Interrupt Status. Indirect Register 00H: RTTP PATH Trace Configuration Indirect Register 7FH: RTTP PATH Captured Trace Indirect Register BFH: RTTP PATH Accepted Trace. Indirect Register FFH: RTTP PATH Expected Trace Register 0709H: TTTP PATH Indirect Data Indirect Register 7FH: TTTP PATH Trace Register 0708H: TTTP PATH Indirect Address Indirect Register 00H: TTTP PATH Trace Configuration. Register 0720H: SARC Path Register Enable Register 0722H: SARC Section Configuration Register 0723H: SARC Section SALM Enable
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Register 0724H: SARC Section RLAISINS Enable Register 0725H: SARC Section TLRDIINS Enable
Register 0703H: RTTP PATH Trace Unstable Interrupt Enable.
Register 0702H: RTTP PATH Trace Unstable Status
Register 0701H: RTTP PATH Indirect Data.
Register 0700H: RTTP PATH Indirect Address
Indirect Register 02H: SVCA Diagnostic/Configuration
Indirect Register 01H: SVCA Negative Justifications Performance Monitor.
Indirect Register 00H: SVCA Positive Justifications Performance Monitor
Register 060BH, 062BH, 064BH, 066BH: SVCA Performance Monitor Trigger
Register 060AH, 062AH, 064AH, 066AH: SVCA MISC Register
Register 0609H, 0629H, 0649H, 0669H: SVCA Reserved.
Register 0608H, 0628H, 0648H, 0668H: SVCA FIFO Interrupt Enable
Register 0607H, 0627H, 0647H, 0667H: SVCA Pointer Justification Interrupt Enable.
Register 0606H, 0626H, 0646H, 0666H: SVCA FIFO Underflow Interrupt Status
Register 0605H, 0625H, 0645H, 0665H: SVCA FIFO Overflow Interrupt Status
Register 0604H, 0624H, 0644H, 0664H: SVCA Negative Justification Interrupt Status.
Register 0603H, 0623H, 0643H, 0663H: SVCA Positive Justification Interrupt Status.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Register 0728H: SARC Path Configuration Register 0729H: SARC Path RALM Enable Register 0730H: SARC Pointer Status Register 0732H: SARC Pointer Interrupt Status. Register 0734H: SARC Pointer Interrupt Enable Register 0740H: RCFP Configuration. Register 0742H: RCFP Interrupt Indication Status Register 0744H: RCFP Maximum Packet Length Register 0746H: RCFP Idle Cell Header Mask. Register 0748H: RCFP Receive Byte/Idle Cell Counter Register 0749H: RCFP Receive Byte/Idle Cell Counter (MSB). Register 074AH: RCFP Packet/Cell Counter (LSB) Register 074BH: RCFP Receive Packet/ACell Counter (MSB). Register 074CH: RCFP Receive Erroneous FCS/HCS Counter Register 074DH: RCFP Receive Aborted Packet Counter Register 074EH: RCFP Receive Minimum Length Packet Error Counter Register 074FH: RCFP Receive Maximum Length Packet Error Counter Register 0750H: TCFP Configuration Register 0752H: TCFP Idle/Unassigned ACell Header Register 0754H: TCFP Transmit Cell/Packet Counter (LSB) Register 072A: SARC Path RPAISINS Enable. Register 0731H: SARC Pointer Interrupt Enable. Register 0733H: SARC Pointer Status. Register 0735H: SARC Pointer Interrupt Status Register 0741H: RCFP Interrupt Enable Status Register 0743H: RCFP Minimum Packet Length Register 0745H: RCFP Count Threshold Register 0747H: RCFP Receive Byte/Idle Cell Counter (LSB).
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Register 0755H: TCFP Transmit Cell/Packet Counter (MSB) Register 0756H: TCFP Transmit Byte Counter (LSB) Register 0757H: TCFP Transmit Byte Counter Register 0758H: TCFP Transmit Byte Counter (MSB) Register 0759H: TCFP Aborted Packet Counter
Register 0753H: TCFP Diagnostics
Register 0751H: TCFP Interrupt Indication.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Register 0760H: RXSDQ FIFO Reset. Register 0761H: RXSDQ FIFO Interrupt Enable Register 0768H: RXSDQ FIFO Indirect Address Register 076AH: RXSDQ FIFO Indirect Data Available Threshold Register 076CH: RXSDQ FIFO Cells Packets Accepted Aggregate Count (LSB). Register 0763H: RXSDQ FIFO Overflow Port Interrupt Indication
Register 076EH: RXSDQ FIFO Cells Packets Dropped Aggregate Count Register 0771H: TXSDQ FIFO Interrupt Enable. Register 0773H: TXSDQ FIFO Overflow Port Interrupt Indication Register 0774H: TXSDQ FIFO Error Port Interrupt Indication Register 0775H: TXSDQ FIFO Error Port Interrupt Indication Register 0778H: TXSDQ FIFO Indirect Address Register 0779H: TXSDQ FIFO Indirect Configuration Register 077BH: TXSDQ FIFO Indirect Cells Packets Count Register 077CH: TXSDQ FIFO Cells Packets Accepted Aggregate Count (LSB). Register 077AH: TXSDQ FIFO Indirect Data Buffer Available Thresholds
Register 077EH: TXSDQ FIFO Cells Packets Dropped Aggregate Count. Register 0781H: RXPHY Interrupt Status Register 0783H: RXPHY Indirect Burst Size Register 0785H: RXPHY Calendar Indirect Address Data
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Register 0786H: RXPHY Data Type Field Register 0788H: TXPHY Configuration.
Register 0789H: TXPHY Interrupt Status Register 078AH: TXPHY Interrupt Enable Register 078BH: TXPHY Data Type Field
Register 0784H: RXPHY Calendar Length
Register 0782H: RXPHY Interrupt Enable
Register 0780H: RXPHY Configuration
Register 077DH: TXSDQ FIFO Cells Packets Accepted Aggregate Count (MSB).
Register 0770H: TXSDQ FIFO Reset
Register 076DH: RXSDQ FIFO Cells Packets Accepted Aggregate Count (MSB).
Register 076BH: RXSDQ FIFO Indirect Cells Packets Count
Register 0769H: RXSDQ FIFO Indirect Configuration.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Register 0790H: SIRP Configuration Timeslot Register 079CH: SIRP Configuration. Register 0800H: PRGM Indirect Address Register 0810H: PRGM Indirect Address Register 0820H: PRGM Indirect Address Register 0830H: PRGM Indirect Address
Register 0809H: PRGM Monitor Synchronization Interrupt Status Register 0819H: PRGM Monitor Synchronization Interrupt Status Register 0829H: PRGM Monitor Synchronization Interrupt Status Register 0839H: PRGM Monitor Synchronization Interrupt Status Register 080AH: PRGM Monitor Synchronization Interrupt Enable Register 081AH: PRGM Monitor Synchronization Interrupt Enable Register 082AH: PRGM Monitor Synchronization Interrupt Enable Register 083AH: PRGM Monitor Synchronization Interrupt Enable Register 080BH: PRGM Monitor Synchronization Status Register 081BH: PRGM Monitor Synchronization Status Register 082BH: PRGM Monitor Synchronization Status Register 083BH: PRGM Monitor Synchronization Status. Register 080CH: PRGM Performance Counters Transfer Trigger Register 081CH: PRGM Performance Counters Transfer Trigger Register 082CH: PRGM Performance Counters Transfer Trigger Register 083CH: PRGM Performance Counters Transfer Trigger Indirect Register 00H: PRGM Monitor Timeslot Configuration Page. Indirect Register 01H: PRGM Monitor PRBS[22:7] Accumulator Page. Indirect Register 02H: PRGM Monitor PRBS[6:0] Accumulator Page.
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Register 0805H: PRGM Monitor Byte Error Interrupt Enable Register 0815H: PRGM Monitor Byte Error Interrupt Enable Register 0825H: PRGM Monitor Byte Error Interrupt Enable Register 0835H: PRGM Monitor Byte Error Interrupt Enable.
Register 0804H: PRGM Monitor Byte Error Interrupt Status Register 0814H: PRGM Monitor Byte Error Interrupt Status Register 0824H: PRGM Monitor Byte Error Interrupt Status Register 0834H: PRGM Monitor Byte Error Interrupt Status.
Register 0803H: PRGM Monitor Payload Configuration Register Register 0813H: PRGM Aux2 Monitor Payload Configuration Register 0823H: PRGM Aux3 Monitor Payload Configuration Register 0833H: PRGM Aux2 Monitor Payload Configuration
Register 0802H: PRGM Generator Payload Configuration Register 0812H: PRGM Generator Payload Configuration Register 0822H: PRGM Generator Payload Configuration Register 0832H: PRGM Generator Payload Configuration.
Register 0801H: PRGM Indirect Data Register 0811H: PRGM Indirect Data Register 0821H: PRGM Indirect Data Register 0831H: PRGM Indirect Data
S/UNI-2488 Telecom Standard Product Datasheet Releas
Indirect Register 04H: PRGM Monitor Error Count Page Indirect Register 08H: PRGM Generator Timeslot Configuration Page Indirect Register PRGM Generator PRBS[22:7] Accumulator Page. Register 0840H: R8TD APS1 Control Status Register 0848H: R8TD APS2 Control Status Register 0850H: R8TD APS3 Control Status Register 0858H: R8TD APS4 Control Status
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Register 0865H: T8TE APS1 Analog Control Register 086DH: T8TE APS2 Analog Control Register 0875H: T8TE APS3 Analog Control Register 087DH: T8TE APS4 Analog Control Register 0866H: T8TE APS1 Register 086EH: T8TE APS2 Register 0876H: T8TE APS3 Register 087EH: T8TE APS4
Register 0864H: T8TE APS1 Test Pattern Register 086CH: T8TE APS2 Test Pattern Register 0874H: T8TE APS3 Test Pattern Register 087CH: T8TE APS4 Test Pattern
Register 0863H: T8TE APS1 TelecomBus Mode Register 086BH: T8TE APS2 TelecomBus Mode Register 0873H: T8TE APS3 TelecomBus Mode Register 087BH: T8TE APS4 TelecomBus Mode
Register 0862H: T8TE APS1 TelecomBus Mode Register 086AH: T8TE APS2 TelecomBus Mode Register 0872H: T8TE APS3 TelecomBus Mode Register 087AH: T8TE APS4 TelecomBus Mode
Register 0861H: T8TE APS1 Interrupt Status Register 0869H: T8TE APS2 Interrupt Status Register 0871H: T8TE APS3 Interrupt Status Register 0879H: T8TE APS4 Interrupt Status.
Register 0860H: T8TE APS1 Control Status Register 0868H: T8TE APS2 Control Status Register 0870H: T8TE APS3 Control Status Register 0878H: T8TE APS4 Control Status.
Register 0845H: R8TD APS1 Analog Control Register 084DH: R8TD APS2 Analog Control Register 0855H: R8TD APS3 Analog Control Register 085DH: R8TD APS4 Analog Control
Register 0844H: R8TD APS1 Analog Control Register 084CH: R8TD APS2 Analog Control Register 0854H: R8TD APS3 Analog Control Register 085CH: R8TD APS4 Analog Control
Register 0843H: R8TD APS1 Analog Control Register 084BH: R8TD APS2 Analog Control Register 0853H: R8TD APS3 Analog Control Register 085BH: R8TD APS4 Analog Control
Register 0842H: R8TD APS1 Line Code Violation Count Register 084AH: R8TD APS2 Line Code Violation Count Register 0852H: R8TD APS3 Line Code Violation Count Register 085AH: R8TD APS4 Line Code Violation Count
Register 0841H: R8TD APS1 Interrupt Status Register 0849H: R8TD APS2 Interrupt Status Register 0851H: R8TD APS3 Interrupt Status Register 0859H: R8TD APS4 Interrupt Status
Indirect Register 0AH: PRGM Generator PRBS[6:0] Accumulator Page
S/UNI-2488 Telecom Standard Product Datasheet Releas
Register 0880H: RXDLL Configuration Register 0881H: RXDLL Vernier Control Register 0882H: RXDLL Delay Status/DLL Reset.
Register 0885H: TXDLL Vernier Control. Register 0887H: TXDLL Control Status Register 0889H: CSTR Interrupt Enable Lock Status. Register 0900H: FIFO Interrupt Enable. Register 0902H: S/UNI-2488 Miscellaneous Defect Configuration Register 090EH 090F: S/UNI-2488 Reserved Register 2001H: S/UNI-2488 Test Mode Address Force Enable Register 2002H: S/UNI-2488Test Mode Address Force Value Register 2003H: S/UNI-2488 Reserved Test Register
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Register 2000H: S/UNI-2488 Master Test
Register 0903H 090D: S/UNI-2488 Reserved
Register 0901H: FIFO Interrupt Status.
Register 088AH: CSTR Lock Interrupt Indication
Register 0888H: CSTR Control.
Register 0886H: TXDLL Delay Status/DLL Reset
Register 0884H: TXDLL Configuration
Register 0883H: RXDLL Control Status.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Figure Connection Example Architecture. Figure Loopback Modes Figure Working. Figure Protect Figure Typical STS-48c (STM-16c) Jitter Tolerance Figure STS-48c (STM-16-16c) RTOH Figure Pointer Interpretation State Diagram Figure Concatenation Pointer Interpretation State Diagram. Figure Cell Delineation State Diagram. Figure PPP/HDLC Over SONET Frame Format. Figure Decoder. Figure Jitter transfer frequency region Figure Generator Figure Output Cell (OUT_CELL). Figure Bidirectional Cell (IO_CELL). Figure Generic LVDS Link Block Diagram. Figure Packet Over SONET Mapping. Figure Byte AData Structure Figure Byte Packet Data Structure Figure Layout Output Enable Bidirectional Cells Figure AMapping. Figure Jitter transfer results Figure STS-48c (STM-16-16c) TTOH. Figure Input Observation Cell (IN_CELL) Figure Pointer Generation State Diagram
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Figure TPAHOLD Figure TPAHOLD Figure Boundary Scan Architecture Figure Controller Finite State Machine Figure PECL Levels (100K Characteristics)
Figure Normal Operation
Figure STS-48 (STM-16-16c) Packet Over SONET (POS-PHY Level Router Application
Figure STS-48 (STM-16-16c) A(UTOPIA Level Switch Port Application
List Figures
S/UNI-2488 Telecom Standard Product Datasheet Releas
Figure S/UNI-2488 Termination Scheme Figure S/UNI-2488 Termination Scheme Figure S/UNI-2488 Termination Scheme
Figure Transmit UTOPIA Level System Interface Timing Single Figure Transmit POS-PHY Level System Interface Timing Figure RTOH Output Timing Figure TTOH TTOHEN Input Timing Figure RPOH Output Timing. Figure RALM ROHFP Output Timing. Figure Backwards Compatible OC48 Analog Power Supply Filters Figure Interface LVDS Analog Power Supply Filters. Figure Intel Microprocessor Interface Read Timing. Figure Intel Microprocessor Interface Write Timing Figure Reset pulse width Figure Receive System Interface Timing Diagram Figure Transmit System Interface Timing Figure SONET/SDH Receive Overhead Interface Timing Figure SONET/SDH Transmit Overhead Interface Timing Figure JTAG Port Interface Timing
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Figure Port Interface Timing
Figure Optimal OC48 Analog Power Supply Filters.
Figure TPOH Input Timing
Figure TTOH TOHFP Input Timing
Figure RTOH ROHFP Output Timing
Figure Receive POS-PHY Level System Interface Timing
Figure Receive UTOPIA Level System Interface Timing Single
Figure Outgoing Serial TelecomBus Timing.
Figure Incoming Serial TelecomBus Timing.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Table Insertion Priority Table Path Overhead Byte Source Priority. Table Register Memory Map. Table TX2488 Mode Control. Table Functionality CRC_SEL[1:0] Register Bits. Table Mode Selection Table SIRP Maintenance. Table TelecomBus Mode Table Test Mode Register Memory Map. Table Instruction Register (Length bits). Table Identification Register Table Boundary Scan Register Table Serial TelecomBus 8B/10B Control Character Decoding Table Serial TelecomBus 8B/10B Control Character Encoding Table SVCA STS-1 Transport Overhead Modification Table BERM Configuration SONET STS-48c Table Absolute Maximum Ratings Table Power Requirements .Error! Bookmark defined. Table Optimal OC48 Analog Power-Supply Filtering Recommendations Table Backwards Compatible OC48 Analog Power-Supply Filtering Recommendations. Table Characteristics
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Table S/UNI-2488 PECL Amplitude Specifications
Table BERM Configuration STM-16c.
Table SIRP Priority Schemes
Table SIRP Settings
Table Selection Number Flag Bytes
Table Mode Control.
Table Mode Control.
Table Byte Stuffing.
Table Bytes Definition
Table Byte Destuffing.
Table Expected Defect Based Range Values
Table PLM-P, UNEQ-P PDI-P Defects Declaration.
List Tables
S/UNI-2488 Telecom Standard Product Datasheet Releas
Table Microprocessor Interface Read Access Timing (Figure Table Microprocessor Interface Write Access Timing (Figure 54). Table Receive System Interface Timing (Figure Table SONET/SDH Overhead Interface Timing (Figure Figure Table OC-48 Interface Timing. Table Ordering Information Table Device Compact Model Table Thermal Resistance Flow
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Table Device Compact Model
Table Heat Sink Requirements
Table Outside Plant Thermal Information
Table JTAG Port Interface Timing (Figure 61).
Table Port Interface Timing (Figure 60).
Table Transmit System Interface Timing (Figure
Table Reset Pulse Width Timing (Figure
S/UNI-2488 Telecom Standard Product Datasheet Releas
ASSP ABER CMOS ERDI FEBE FIFO HDLC LFSR LVDS LVTTL
Automatic Protection Switching Asynchronous Transfer Mode Error Rate Byte Interleaved Parity Current Mode Logic Complementary Metal Oxide Semiconductor Cyclic Redundancy Check Clock Recovery Unit Clock Synthesis Unit Data Communication Channel Data Recovery Unit Emitter-Coupled Logic Electrostatic Discharge Frame Check Sequence Far-End Block Error First-In First-Out Generic Flow Control Enhanced Remote Defect Indication
Header Check Sequence High-level Data Link Controller Jitter Attenuator Loss Cell Delineation Loss
PECL
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Loss Pointer Loss Signal
Voltage Differential Signaling Low-Voltage Transistor-Transistor Logic
Connect, indicates unused Data Flag Network-Network Interface Optical Data Link Frame Pseudo-ECL
Linear Feedback Shift Register
Application Specific Standard Product
APISO
Parallel Serial Converter
Alarm Indication Signal
following table defines abbreviations S/UNI-2488.
Definitions
S/UNI-2488 Telecom Standard Product Datasheet Releas
PISO PRBS PRGM PSLM RCFP RDI-L RHPP RRMP RTTP RXPHY RXSDQ SARC SBER SIPO SIRP SONET STLI STSI SVCA TCFP THPP TRMP TTTP
Parallel-In-Serial-Out (Parallel Serial Converter) Phase-Locked Loop Packet Over SONET Point-to-Point Protocol Pseudo-Random Sequence SONET/SDH PRBS Generator/Monitor Block Path Signal Label Path Signal Label Mismatch Line Remote Defect Indication Receive High Order Path Processor Receive Regenerator Multiplexer Processor Receive Tail Trace Processor Receive Interface Receive Scalable Data Queue FIFO Remote Defect Indication SONET/SDH Error Rate Monitor Signal Detect Synchronous Digital Hierarchy Signal Fail SONET/SDH Alarm Reporting Controller
SONET/SDH Virtual Container Aligner Transmit Cell Frame Processor STS-48c (STM-16c) channel Transmit High Order Path Processor Trace Identifier Mismatch
TXPHY
TXSDQ
VCXO
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Trace Identifier Unstable Transport Overhead Transmit Tail Trace Processor Transmit Interface Transmit Scalable Data Queue FIFO
Transmit Regenerator Multiplexer Processor
Unit Interval User-Network Interface Virtual Connection Indicator Voltage Controlled Crystal (Xtal) Oscillator
Space Timeslot Interchange
SONET/SDH Transmit Line Interface
Synchronous Payload Envelopes
Synchronous Optical Network
SONET/SDH Inband Error Report Processor
Serial-In Parallel-Out (Serial Parallel Converter)
Receive Cell Frame Processor Block STS-48c (STM-16c) channel
S/UNI-2488 Telecom Standard Product Datasheet Releas
Virtual Path Indicator Wide Area Network Exclusive logic operator
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S/UNI-2488 Telecom Standard Product Datasheet Releas
Single chip Aand User-Network Interface operating 2488.32 Mbit/s.
Provides support automatic protection switching 4-bit LVDS 777.76 port. Provides standard signal IEEE 1149.1 JTAG test port boundary scan board test purposes. Provides generic 16-bit microprocessor interface configuration, control, status monitoring. power 1.8V CMOS core logic with 3.3V CMOS/TTL compatible digital inputs digital outputs. PECL inputs outputs 3.3V compatible. UBGA package.
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Frames SONET/SDH receive stream inserts framing bytes (A1, section trace byte (J0) into transmit stream; descrambles received stream scrambles transmit stream.
SONET Section Line Regenerator Multiplexer Section
Wide operating temperature range (-40°C +85°C).
Supports line loopback from line side receive stream transmit stream diagnostic loopback from line side transmit stream line side receive stream interface.
Provides SATURN POS-PHY Level 32-bit System Interface (clocked MHz) Packet over SONET (POS), Aapplications.
Provides UTOPIA Level 32-bit wide System Interface (clocked MHz) with parity support Aapplications.
Provides termination SONET Section, Line Path overhead Regenerator Section, Multiplexer Section High Order Path overhead.
Complies with Bellcore GR-253-CORE jitter tolerance, jitter transfer intrinsic jitter criteria.
Processes bit-serial 2488.32 Mbit/s STS-48 (STM-16-16c) data streams with on-chip clock data recovery clock synthesis.
Implements Point-to-Point Protocol (PPP) over SONET/SDH specification according 2615(1619)/1662 Working Group Internet Engineering Task Force (IETF).
Implements AForum User Network Interface Specification Aphysical layer Broadband ISDN according CCITT Recommendation I.432.
General
Features
S/UNI-2488 Telecom Standard Product Datasheet Releas
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Extracts inserts entire SONET/SDH path overhead from dedicated pins. path overhead bytes sourced from internal registers from serial path overhead input stream. Path overhead insertion also disabled. Extracts received path payload label (C2) byte into internal register detects payload label unstable (PLU), payload label mismatch (PLM), payload unequipped (UNEQ) payload defect indication (PDI). Inserts path payload label (C2) byte from internal register transmit stream.
Detects loss pointer (LOP), path alarm indication signal (PAIS) path (normal enhanced) remote defect indication (RDI) receive stream. Optionally inserts path alarm indication signal (PAIS) path remote defect indication (RDI) transmit stream.
Interprets received payload pointer (H1, extracts STS-48c/STM-16c synchronous payload envelope path overhead.
SONET Path High Order Path
Supports Automatic Protection Switching (APS) mate protection port.
Provides automatic DROP line insertion following detection various received alarms (LOS, LOF, LAIS, STIM, STIU).
Provides automatic transmit line insertion following detection various received alarms (LOS, LOF, LAIS, STIM, STIU).
Configurable force Line transmit stream.
Detects loss signal (LOS), frame (OOF), loss frame (LOF), line remote defect indication (RDI-L), line alarm indication signal (AIS-L), protection switching byte failure alarms receive stream.
Extracts byte (Bellcore compatible) byte (ITU compatible) section trace (J0) message using internal register bank receive stream. Detects unstable message mismatch message with expected message. Provides access accepted message microprocessor port. Inserts byte byte section trace (J0) message using internal register bank transmit stream.
Extracts filters synchronization status message (S1) byte into internal register receive stream. Inserts synchronization status message (S1) byte into transmit stream.
Extracts filters automatic protection switch (APS) channel (K1, bytes into internal registers. Inserts channel into transmit stream.
Extracts optionally inserts dedicated pins SONET/SDH transport overhead STS-48c/STM-16c frame.
Detects signal degrade (SD) signal fail (SF) threshold crossing alarms based received errors.
Calculates compares interleaved parity (BIP) error detection codes (B1, receive stream. Calculates inserts transmit stream. Accumulates near errors (B1, errors (M1) inserts line remote error indications (REI) into byte based received errors.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Supports packet based link layer protocols using byte synchronous HDLC framing. Performs self-synchronous data de-scrambling received STS-48c/STM16c-16c payloads using x43+1 polynomial. Performs frame check sequence (FCS) validation CRC-CCITT CRC-32 polynomials. Detects packet abort sequence. Checks minimum maximum packet lengths. Optionally deletes short packets marks those exceeding maximum length erroneous. Permits stripping POS-PHY output data stream.
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Performs control escape de-stuffing byte de-stuffing stream.
Performs flag sequence detection terminates received frames.
Receive Processor
Provides UTOPIA Level POS-PHY Level 32-bit wide datapath interfaces (clocked MHz) with parity support read extracted cells from internal cell FIFO buffer.
Counts number received cells, idle cells, erroneous cells dropped cells.
Detects cell delineation (OCD) loss cell delineation (LCD) alarms.
Performs header check sequence (HCS) error detection, idle/unassigned cell filtering.
Provides Acell payload de-scrambling.
Extracts Acells from received STS-48c/STM-16c channel payloads using Acell delineation.
Receive AProcessor
Provides automatic transmit path path Enhanced insertion following detection various received alarms (LAIS, LOP, LOPCON, PAIS, PAISCON, PTIM, PTIU, PLM, PLU, UNEQ, PDI).
Counts received path remote error indications (REI's) performance monitoring purposes. Optionally inserts path count into path status byte (G1) based block BIP-8 errors detected receive path. Reporting BIP-8 errors block basis independent accumulation BIP-8 errors.
Detects received path BIP-8 counts received path BIP-8 errors performance monitoring purposes. BIP-8 errors selectable treated basis block basis. Optionally calculates inserts path BIP-8 error detection codes transmit stream.
Extracts byte byte path trace (J1) message using internal register bank receive stream. Detects unstable message mismatch message with expected message. Provides access captured, accepted expected message microprocessor port. Inserts byte byte path trace (J1) message using internal register bank transmit stream.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Provides idle/unassigned cell insertion. Counts number transmitted cells.
Optionally provides generation/insertion, Acell payload scrambling. Provides UTOPIA Level POS-PHY Level 32-bit wide datapath interfaces (clocked MHz) with parity support writing cells into internal cell FIFO.
Performs flag sequence insertion.
Performs byte stuffing transparency processing.
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Provides SATURN® POS-PHY Level 3compliant 32-bit wide datapath (clocked MHz) with parity support internal 192x16-byte FIFO buffer.
Aborts packets under direction host when FIFO underflows.
Optionally performs frame check sequence generation using CRC-CCITT CRC-32 polynomials.
Encapsulates packets within POS/HDLC frame.
Performs self-synchronous data scrambling using 1+X43 polynomial.
Supports packet based link layer protocol using byte synchronous synchronous framing like PPP, HDLC Frame Relay.
Transmit Processor
Transmit AProcessor
Provides SATURN POS-PHY Level 3compliant 32-bit datapath interface (clocked MHz) with parity support read packet data from internal 192x16-byte FIFO buffer.
S/UNI-2488 Telecom Standard Product Datasheet Releas
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SONET/SDH ATM/POS Test Equipment
Uplink cards
SONET/SDH Add/Drop Multiplexers with data processing capabilities
Aand Multi-service Switches, routers, switch/routers
Applications
S/UNI-2488 Telecom Standard Product Datasheet Releas
Bell Communications Research GR-436-CORE "Digital Network Synchronization Plan", Issue Revision June 1996. ANSI T1.105-1995, "Synchronous Optical Network (SONET) Basic Description including Multiplex Structure, Rates, Formats", 1995. ANSI T1.107 1995, "Digital Hierarchy Formats Specifications".
Recommendation I.432, "ISDN User Network Interfaces", 1993.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Recommendation I.432, "ISDN User Network Interfaces", March AForum AF-PHY-0136.000, "UTOPIA Level November, 1999.
IETF Network Working Group RFC-1619, "Point Point Protocol (PPP) over SONET/SDH Specification", 1994.
ITU, Recommendation G.783 "Characteristics Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks", 1996.
Recommendation G781, "Structure Recommendations Equipment Synchronous Design Hierarchy (SDH)", January 1994.
ITU, Recommendation G.707 "Network Node Interface Synchronous Digital Hierarchy", 1996.
ITU-T Recommendation G.703 "Physical/Electrical Characteristics Hierarchical Digital Interfaces", 1991.
417-1-1, "Generic Functional Requirements Synchronous Digital Hierarchy (SDH) Equipment", January, 1996.
Electronic Industries Alliance 1999. Integrated Circuit Thermal Test Method Environmental Conditions -Junction-to-Board: JESD51-8. October 1999.
Electronic Industries Association. Methodology Thermal Measurement Component Packages (Single Semiconductor Device): EIA/JESD51. December 1995.
ANSI T1.627 1993, "Broadband ISDN ALayer Functionality Specification".
ANSI T1.107a 1990, "Digital Hierarchy Supplement Formats Specifications (DS3 Format Applications)".
Bell Communications Research GR-253-CORE "SONET Transport Systems: Common Generic Criteria", Issue Revision January 1999.
References
S/UNI-2488 Telecom Standard Product Datasheet Releas
IETF Network Working Group RFC-1661, "The Point Point Protocol (PPP)", July, 1994. IETF Network Working Group RFC-1662, "PPP HDLC like framing", July 1994.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Telcordia Technologies. Network Equipment-Building System (NEBS) Requirements: Physical Protection: Telcordia Technologies Generic Requirements GR-63-CORE. Issue October 1995.
SEMI (Semiconductor Equipment Materials International). SEMI G30-88 Test Method Junction-to-Case Thermal Resistance Measurements Ceramic Packages. 1988.
OIF-SPI3-01.0 "System Packet Interface Level (SPI-3): OC48 System Interface Physical Link Layer Devices", June 2000.
IETF Network Working Group RFC-2615, "Point Point Protocol (PPP) over SONET/SDH", June 1999.
S/UNI-2488 Telecom Standard Product Datasheet Releas
TxClk TxEnb TxClav TxSOC TxPrty TxData[31:0]
PM7325 S/UNI-ATLAS3200 ALayer Device
TFCLK TENB TSOC TPRTY TDAT[31:0] RXD_P/_N RFCLK RENB RSOC RPRTY RDAT[31:0] TXD_P/_N POSL3_UL3B Optical Transceiver
RxEnb
RxClk
PM5381 S/UNI-2488
Figure STS-48 (STM-16-16c) A(UTOPIA Level Switch Port Application
typical STS-48 (STM-16-16c) Aapplication, S/UNI-2488 performs clock data recovery receive direction clock synthesis transmit direction line interface. system side, S/UNI-2488 interfaces directly with Alayer processors switching adaptation functions using UTOPIA Level compliant 32-bit (clocked MHz) synchronous FIFO style interface. application with UTOPIA Level system side interface shown Figure initial configuration ongoing control monitoring S/UNI2488 normally provided generic microprocessor interface.
RxClav
RxSOC RxPrty
RxData[31:0]
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
PM5381 S/UNI-2488® device applicable equipment implementing Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI), ANetwork-Network Interfaces (NNI), well Packet over SONET (POS) interfaces. interface support several packet based protocols including Point-to-Point Protocol (PPP). S/UNI-2488 find application either switch-to-switch links, router router links, switch router links switch-to-terminal links public private wide area networks (WAN). S/UNI-2488 provides comprehensive feature well compatibility with synchronization requirements. S/UNI-2488 performs mapping either Acells frames into SONET/SDH STS-48 (STM-16-16c) synchronous payload envelope (SPE) processes applicable SONET/SDH section, line path overheads.
Application Examples
S/UNI-2488 Telecom Standard Product Datasheet Releas
Link Layer Device
TFCLK TENB DTPA TSOP TPRTY TDAT[31:0] TMOD[1:0] TEOP TERR
TEOP TERR
TMOD[1:0]
TDAT[31:0]
TPRTY
RXD_P/_N TXD_P/_N
TSOP
DTPA
TENB
TFCLK
PM5381 S/UNI-2488
RFCLK RENB RSOP RPRTY RDAT[31:0] RMOD[1:0]
RFCLK RENB RSOP RPRTY RDAT[31:0] RMOD[1:0] REOP RERR RVAL
POSL3_UL3B
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
REOP
RERR RVAL
Figure STS-48 (STM-16-16c) Packet Over SONET (POS-PHY Level Router Application
Optical Transceiver
typical Packet over SONET application (i.e. using protocol) S/UNI-2488 performs clock data recovery receive direction clock synthesis transmit direction line interface. system side, S/UNI-2488 interfaces directly with data link layer processor using SATURN POS-PHY Level 332-bit (clocked MHz) synchronous FIFO interface over which packets transferred. initial configuration ongoing control monitoring S/UNI-2488 normally provided generic microprocessor interface.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
single-ended 77.76MHz APSIFPCLK generated directly from common 155.52MHz PECL Differential Reference Clock. This clocks common frame pulse generator. This these signals intended generated. Note that APSOFP used, this diagnostic port only. APSOFP should connected APSIFP.
S/UNI-2488 supports Automatic Protection Switching. mode allows S/UNI-2488 switch over second S/UNI-2488 middle data-path transmit receive over second optical connection. example below configuration (one working, plus protection), with normal "working" device switching over "protect" device response interruption working chip's line side. illustrates connections between chips.
S/UNI-2488 Telecom Standard Product Datasheet Releas
Figure Connection Example Architecture
Optical Tranceiver
Optical Tranceiver
APSO_P[1.4] APSO_N[1.4] APSI_P[1.4] APSI_N[1.4] APSOFP APSIFP
APSI_P[1.4] APSI_N[1.4]
Differential PECL Single-Ended CMOS Frequency Divider
APSIFPCLK
PROTECT DEVICE
APSO_P[1.4]
APSO_N[1.4] APSOFP APSIFP
9720 Pulse Generator
APSIFPCLK
REFCLK_P REFCLK_N
REFCLK_P REFCLK_N
155.52 PECL Differential Reference Clock
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
UL3/PL3 System Interface
WORKING DEVICE
ATM/Link Layer Device
2488 Gbps Line Interface
2488 Gbps Line Interface
S/UNI-2488 Telecom Standard Product Datasheet Releas
ROHCLK ROHFP RTOH
RPOH RPOHEN
APSI_P/_N[4:1]
R8TD
RXD_P/_N
Figure Normal Operation
Block Diagram
T8TE
C0_CRU C1_CRU C0_CSU C1_CSU RES_RESK ATP_2488[1:0] ATP_1250[1:0]
Analog TxLVRef
APISO TXLV
TOHCLK TOHFP
TTOH TTOHEN
TPOHRDY
TPOH TPOHEN
APSO_P/_N[4:1]
APSIFPCLK
D[15:0] [13:0]
APSOFP
TRSTB
RSTB
INTB
Microprocessor Interface
TTTP
TTTP
PGMTCLK
STLI
TRMP
REFCLK+/-
TXD_P/_N
Line
TCLK
RCLK
Line
PGMRCLK
SRLI RHPP
RRMP
SVCA
Cntr
RCFP
RXSDQ FIFO
RXPHY
RPRTY RDAT[31:0] RFCLK
REOP RERR
SARC SONET/SDH Alarm Reporting Controller
RMOD[1:0]
SALM
RALM
POSL3_UL3B
TENB
TCA/DTPA
SIRP
TSOC/TSOP
PRGM THPP
Cntr
TCFP
TXSDQ FIFO
TXPHY
TPRTY TDAT[31:0]
TFCLK TEOP
TERR TMOD[1:0]
JTAG
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
SBER
RTTP
RTTP
RXLV
APSIFP
RENB
RCA/RVAL RSOC/RSOP
S/UNI-2488 Telecom Standard Product Datasheet Releas
ROHCLK ROHFP RTOH
RPOH RPOHEN
APSI_P/_N[4:1]
R8TD
Cntr
SERIAL DIAGNOSTIC LOOPBACK (SDLE=1) PARALLEL DIAGNOSTIC LOOPBACK (PDLE=1)
LINE LOOPBACK (SLLE=1)
RCLK
TCLK
TXD_P/_N REFCLK+/-
Figure Loopback Modes
T8TE
C0_CRU C1_CRU C0_CSU C1_CSU RES_RESK ATP_2488[1:0] ATP_1250[1:0]
Analog TxLVRef
APISO TXLV
TOHCLK TOHFP
TTOH TTOHEN
TPOHRDY
TPOH TPOHEN
APSO_P/_N[4:1]
APSIFPCLK
D[15:0] [13:0]
APSOFP
TRSTB
RSTB
INTB
Microprocessor Interface
TTTP
TTTP
PGMTCLK
STLI
THPP
TRMP
Line
RXD_P/_N
Line
PGMRCLK
SRLI RHPP SVCA
RRMP
RCFP
RXSDQ FIFO
RXPHY
RPRTY RDAT[31:0]
RFCLK
REOP RERR
SARC SONET/SDH Alarm Reporting Controller
RMOD[1:0]
SALM
RALM
POSL3_UL3B
TENB
TCA/DTPA
SIRP
TSOC/TSOP
PRGM
Cntr
TCFP
TXSDQ FIFO
TXPHY
TPRTY TDAT[31:0]
TFCLK TEOP
TERR TMOD[1:0]
JTAG
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
SBER
RTTP
RTTP
RXLV
APSIFP
RENB RCA/RVAL RSOC/RSOP
S/UNI-2488 Telecom Standard Product Datasheet Releas
ROHCLK ROHFP RTOH
RPOH RPOHEN
from protect mate
APSI_P/_N[4:1]
R8TD
Cntr
APSMUX_RCFP=1
RXD_P/_N RCLK
Failover
PGMTCLK
Figure Working
C0_CRU C1_CRU C0_CSU C1_CSU RES_RESK ATP_2488[1:0] ATP_1250[1:0]
TTTP Analog TxLVRef
TOHCLK TOHFP
TTOH TTOHEN
TPOHRDY
TPOH TPOHEN
D[15:0] [13:0]
APSO_P/_N[4:1]
APSIFPCLK
APSOFP
protect mate
TRSTB
RSTB
INTB
TXLV
Microprocessor Interface
APISO
TTTP
T8TE
STLI
THPP
TRMP
REFCLK+/-
TXD_P/_N
Line
TCLK
Line
PGMRCLK
SRLI RHPP SVCA
RRMP
RCFP
RXSDQ FIFO
RXPHY
RPRTY RDAT[31:0]
RFCLK
REOP RERR
RMOD[1:0]
SARC SONET/SDH Alarm Reporting Controller
SALM
RALM
POSL3_UL3B
TENB
TCA/DTPA
SIRP
TSOC/TSOP
PRGM
Cntr
TCFP
TXSDQ FIFO
TXPHY
TPRTY TDAT[31:0]
TFCLK TEOP
TERR TMOD[1:0]
JTAG
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
SBER
RTTP
RTTP
RXLV
APSIFP
RENB
RCA/RVAL RSOC/RSOP
S/UNI-2488 Telecom Standard Product Datasheet Releas
from working mate
ROHCLK ROHFP RTOH
RPOH RPOHEN
APSI_P/_N[4:1]
R8TD
Cntr
Failover APSMUX_TRMP=1 APSMUX_T8TE=1
RXD_P/_N RCLK
PGMTCLK
C0_CRU C1_CRU
TTTP Analog TxLVRef
Figure Protect
TOHCLK TOHFP
TTOH TTOHEN
TPOHRDY
TPOH TPOHEN
D[15:0] [13:0]
APSO_P/_N[4:1]
APSIFPCLK
APSOFP
working mate
TRSTB
RSTB
INTB
TXLV
Microprocessor Interface
C0_CSU C1_CSU RES_RESK ATP_2488[1:0] ATP_1250[1:0]
APISO
TTTP
T8TE
STLI
THPP
TRMP
REFCLK+/-
TXD_P/_N
Line
TCLK
Line
PGMRCLK
SRLI RHPP SVCA
RRMP
RCFP
RXSDQ FIFO
RXPHY
RPRTY RDAT[31:0]
RFCLK
REOP RERR
RMOD[1:0]
SARC SONET/SDH Alarm Reporting Controller
SALM
RALM
POSL3_UL3B
TENB
TCA/DTPA
SIRP
PRGM
Cntr
TSOC/TSOP
TCFP
TXSDQ FIFO
TXPHY
TPRTY TDAT[31:0]
TFCLK TEOP
TERR TMOD[1:0]
JTAG
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
SBER
RTTP
RTTP
RXLV
APSIFP
RENB RCA/RVAL RSOC/RSOP
S/UNI-2488 Telecom Standard Product Datasheet Releas
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
When used implement AUNI NNI, Acells written internal cell FIFO (programmable FIFO depth) using 32-bit wide UTOPIA Level (clocked MHz) datapath interface. Idle/unassigned cells automatically inserted when internal FIFO contains less than complete cell. S/UNI-2488 provides generation header check sequence scrambles payload Acells. Each these transmit Acell processing functions enabled bypassed.
S/UNI-2488 transmits SONET/SDH streams using serial interface. S/UNI-2488 synthesizes transmit clock from 155.52MHz frequency reference performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, creates section, line, path interleaved parity codes (B1, required allow performance monitoring end. Line path remote error indications (M1, also inserted. S/UNI-2488 generates payload pointer (H1, inserts synchronous payload envelope that carries frames. S/UNI-2488 also supports insertion large variety errors into transmit stream, such framing pattern errors, interleaved parity errors, illegal pointers, which useful system diagnostics tester applications.
When used implement packet transmission over SONET/SDH link, S/UNI-2488 extracts Packet over SONET (POS) frames from SONET/SDH synchronous payload envelope. Frames verified correct construction size. control escape characters removed. frame check sequence optionally verified correctness extracted packets placed receive 192x16-byte FIFO (programmable FIFO depth packets byte block aligned). received packets read from FIFO through 32-bit POS-PHY Level (clocked MHz) system side interface. Valid packet erroneous packet counts provided performance monitoring. S/UNI-2488 Packet over SONET implementation flexible enough support several link layer protocols, including HDLC, Frame Relay.
When used implement AUNI NNI, S/UNI-2488 frames Apayload using cell delineation. Idle/unassigned cells optionally dropped. Cells also dropped upon detection header check sequence error. Acell payloads descrambled written 48-cell FIFO buffer (programmable FIFO depth). received cells read from FIFO using 32-bit wide UTOPIA Level (clocked MHz) datapath interface. Counts received Acell headers that erroneous accumulated independently performance monitoring purposes.
S/UNI-2488 receives SONET/SDH streams using serial interface, recovers clock data processes section, line, path overhead. S/UNI-2488 performs framing (A1, A2), de-scrambling, detects alarm conditions, monitors section, line, path interleaved parity (B1, B3), accumulating error counts each level performance monitoring purposes. Line path remote error indications (M1, also accumulated. S/UNI2488 interprets received payload pointers (H1, extracts synchronous payload envelope which carries received Acells frames.
PM5381 S/UNI-2488 SATURN User Network Interface monolithic integrated circuit that implements SONET/SDH processing, Amapping Packet over SONET mapping functions STS-48 (STM-16-16c) 2488.32 Mbit/s rate.
Description
S/UNI-2488 Telecom Standard Product Datasheet Releas
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
S/UNI-2488 implemented power, +1.8 Volt, CMOS technology. LVTTL/CMOS compatible digital inputs LVTTL/CMOS compatible digital outputs. High speed inputs outputs support 3.3V compatible pseudo-ECL (PECL). S/UNI-2488 packaged UBGA package.
line rate clocks required directly S/UNI-2488 synthesizes transmit clock recovers receive clock using 155.52 reference clock. S/UNI-2488 outputs differential PECL line data (TXD_P/ TXD_N).The S/UNI-2488 configured, controlled monitored generic 16-bit microprocessor interface. S/UNI-2488 also provides standard signal IEEE 1149.1 JTAG test port boundary scan board test purposes.
When used implement Packet over SONET/SDH link, S/UNI-2488 inserts frames into SONET/SDH synchronous payload envelope. Packets transmitted written into 192x16-byte FIFO (programmable FIFO depth packets byte block aligned) through 32-bit SATURN POS-PHY Level 3(clocked MHz) system side interface. frames built inserting flags, control escape characters fields. Either CRC-CCITT CRC-32 computed added frame. Several counters provided performance monitoring.
S/UNI-2488 Telecom Standard Product Datasheet Releas
vddi
VSST
VSST VSST
VSST VSST VSST
VSST VSST VSST VSST
VSST
VSST VSST 3_ul VSST VSST VSST VSST
VSST
VSST
VSST
VSST
VSST
VSST
VSST
vddi VSST
vddi AVDH AVDH AVDH
vddi
vddi
rdat[
rdat[ rdat[ vddi
rdat[ rdat[ rdat[ rdat[ ca_r ohcl vddi VSST VSST VSST VSST VSST VSST VSST VSST VSST VSST VSST VSST vddi vddi VSST VSST rdat[ oc_rs
pohen VSST VSST vddi VSST VSST VSST VSST
VSST VSST VSST VSST
VSST
VSST VSST
VSST tohcl vddi vddi crucl AVDL QAVD AVDL QAVD AVDL c0_cs AVDL c1_cs AVDH AVDH AVDH AVDH c0_cr c1_cr p_2488[ p_2488[ rxd_p
ohen pohr
tpohen
S/UNI 2488 Left Quadrants Upper Lower
VSST
VSST
vddi
tca_dt oc_t
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Diagram
vddi
S/UNI-2488 Telecom Standard Product Datasheet Releas
vddi
vddi
vddi
xd_n
AVDH AVDH
AVDH
AVDH AVDH AVDH
AVDH AVDH AVDH
QAVD QAVD
vddi vddi vddi vddi
S/UNI 2488 Right Quadrants Upper Lower
xd_n
xd_p
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
AVDL AVDL AVDL AVDL
VSST
vddi
vddi
VSST VSST VSST vddi vddi vddi vddi apsf ipcl apsf vddi vddi AVDH AVDH o_n[ o_p[ o_n[ o_p[ o_n[ o_p[ AVDH o_n[ o_p[ aps_p[ aps_n[ aps_p[ aps_n[ AVDL aps_p[ aps_n[ aps_p[ aps_n[ u_avdh AVDH AVDL AVDL AVDH p_1250[ AVDL AVDL AVDH p_1250[ AVDL AVDH AVDL AVDH AVDL
VSST
VSST
VSST
S/UNI-2488 Telecom Standard Product Datasheet Releas
NaREFCLK_P REFCLK_N
Type
Differential PECL compatible Input
Input
AH24
TXD_P TXD_N
Differential, compatible Output
AK12 AK13
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Please refer Operation section discussion PECL interfacing issues. receive signal detect input (SD) indicates presence valid receive signal power from Optical Physical Medium Dependent Device. logic high indicates presence valid data. logic indicates loss signal. Unless detection disabled, deassertion will cause 2488 into training mode where locks REFCLK_P/REFCLK_N. Please refer Operation section discussion interfacing issues transmit differential data CML-compatible outputs (TXD_P/ TXD_N) contain 2488.32 Mbit/s transmit stream. TXD_P/ TXD_N outputs driven using synthesized clock from CSU. Please refer Operation section discussion voltage swing levels.
RXD_P RXD_N
Differential PECLcompatible Input
AK16A
receive differential data PECL-compatible inputs (RXD_P/ RXD_N) contain 2488.32 Mbit/s serial receive stream. receive inputs internally terminated with differential 100-W termination. receive clock recovered from RXD_P/ RXD_N stream.
Note: jitter REFCLK_P REFCLK_N about will also appear transmit data output. Please refer Operation section discussion PECL interfacing issues.
practice, jitter REFCLK_P REFCLK_N inputs must less than psec 12KHz 20MHz band order S/UNI2488 comply with Bellcore GR-253 intrinsic jitter specs transmit data outputs.
AK10
differential reference clock inputs (REFCLK_P REFCLK_N) provides 155.52 reference clock both clock recovery clock synthesis circuits. PECL inputs internally terminated with differential 100-W termination.
Function
Serial Line Side Interface Signals
Description
S/UNI-2488 Telecom Standard Product Datasheet Releas
NaPGMRCLK
Type
Output
RCLK
Output
AG23
TCLK
Output
AJ24
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
PGMTCLK
Output
AH23
programmable transmit clock (PGMTCLK) signal provides timing reference transmit line interface. PGMTCLK divided version reference clock. When PGMTCLKSEL register low, PGMTCLK nominal 19.44 MHz, duty cycle clock. When PGMTCLKSEL register high, PGMTCLK nominal KHz, duty cycle clock. PGMTCLK output disabled held programming PGMTCLKEN STLI Clock Configuration register. transmit clock (TCLK) signal provides timing reference transmit interface. This driven digital intended used clock source. external required smooth this clock desired used clock source. Jitter this clock typically about 450ps. TCLK nominal 77.76MHz duty cycle clock. TCLK output disabled held programming TCLKEN STLI Clock Configuration register.
SALM updated rising edge RCLK.
RCLK nominal 77.76 duty cycle clock. RCLK output disabled held programming RCLKEN SRLI Clock Configuration register.
receive clock (RCLK) signal provides timing reference receive interface. This driven digital intended used clock source. external required smooth this clock desired used clock source. Jitter this clock typically about 450ps.
PGMRCLK output disabled held programming PGMRCLKEN SRLI Clock Configuration register.
PGMRCLK divided version recovered clock. When PGMRCLKSEL register low, PGMRCLK nominal 19.44 MHz, duty cycle clock. When PGMRCLKSEL register high, PGMRCLK nominal KHz, duty cycle clock.
AK25
programmable receive clock (PGMRCLK) signal provides timing reference receive line interface.
Function
Clocks Alarms
S/UNI-2488 Telecom Standard Product Datasheet Releas
high while framing block frame. frame condition declared when four consecutive erroneous framing patterns bytes) have been detected. while framing block frame. updated rising edge RCLK.
CSUCLKO
Output
AG22
CSUCLKI
Input
AK24
CRUCLKO
Output
AJ23
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
RALM updated falling edge ROHCLK. Please refer individual alarm interrupt descriptions Functional Description Section more details each alarm. JAT-CSU output clock (CSUCLKO) used test purposes only. must left no-connect (NC) during normal mode operation. JAT-CSU input clock (CSUCLKI) used test purposes only. must tied during normal mode operation. output clock (CRUCLKO) used test purposes only. must left no-connect (NC) during normal mode operation.
RALM
Output
AK28
Receive Alarm (RALM) signal output alarms receive path. Each alarm represents logical SALM, LOP-P, AIS-P, RDI-P, ERDI-P, LOPC-P, PAISC-P, UNEQ-P, PSLU, PSLM, PDI-P, TIU-P, TIM-P status path. selection alarms reported controlled S/UNI-2488 SARC Path RALM Enable registers. Receive Alarms only extracted from first STS-12 slice this manner.
SALM updated rising edge RCLK.
Section Alarms only extracted from first STS-12 slice this manner.
SALM
Output
AG26
section alarm (SALM) signal high when frame (OOF), loss signal (LOS), loss frame (LOF), line alarm indication signal (LAIS), line remote defect indication (LRDI), section trace identifier mismatch (TIM-S), section trace identifier unstable (TIU-S), signal fail (SF) signal degrade (SD) alarm detected. Each alarm indication independently enabled using bits S/UNI-2488 SARC Section SALM Enable registers. SALM when none enabled alarms active.
Output
AH27
active high frame (OOF) signal indicates when frame condition declared framing block.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
NaROHCLK
Type
Output
ROHFP sampled rising edge ROHCLK.
RTOH
Output
RPOH
Output
RPOHEN
Output
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
receive transport overhead (RTOH) signal contains received transport overhead bytes (A1, D1-D3, H1-H3, D4-D12, Z1/S1, Z2/M1, undefined transport overhead) extracted from first STS-12 (RRMP only) incoming stream. RTOH updated falling edge ROHCLK. receive path overhead (RPOH) signal contains received path overhead bytes (J1, extracted from STS-48c/STM16c SONET/SDH path overhead. Path overhead only extracted from first STS-12 slice this manner. RPOHEN signal high indicate valid path overhead bytes RPOH. RPOH updated falling edge ROHCLK. receive path overhead enable (RPOHEN) signal indicates valid path overhead bytes RPOH When RPOHEN signal high, corresponding path overhead byte presented RPOH valid. When RPOHEN low, corresponding path overhead byte presented RPOH invalid. RPOHEN updated falling edge ROHCLK.
ROHFP updated falling edge ROHCLK.
ROHFP used indicate most significant (MSB) RTOH, RPOH first possible path error B3E.
ROHFP
Output
receive overhead frame pulse (ROHFP) signal provides timing receive section, line path overhead extraction.
ROHFP, RTOH, RPOH, RPOHEN, B3E, RALM updated falling edge ROHCLK.
ROHCLK nominal 20.736 clock generated gapping 25.92 clock. ROHCLK high duty cycle.
receive overhead clock (ROHCLK) signal provides timing receive section, line path overhead extraction.
Function
Receive Section/Line/Path Overhead Extraction Signals
S/UNI-2488 Telecom Standard Product Datasheet Releas
TOHCLK
Output
AJ27
TOHFP
Output
AG25
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
TOHCLK nominal 20.736MHz clock generated gapping 25.92MHz clock. TOHCLK high duty cycle. TOHFP TPOHRDY updated falling edge TOHCLK. TTOH, TTOHEN, TPOH TPOHEN sampled rising edge TOHCLK. transmit overhead frame pulse (TOHFP) signal provides timing transmit section, line path overhead insertion. TOHFP used indicate most significant (MSB) TTOH TPOH. TOHFP high when the: First byte should present TTOH. First byte should present TPOH. TOHFP sampled rising edge TOHCLK. TOHFP updated falling edge TOHCLK.
transmit overhead clock (TOHCLK) signal provides timing transmit section, line path overhead insertion.
Type
Function
Transmit Section/Line/Path Overhead Insertion Signals
updated falling edge ROHCLK.
Path BIP-8 errors detected comparing extracted path BIP-8 byte (B3) with computed path BIP-8 byte previous frame.
When BIP-8 errors treated block basis, high ROHCLK clock cycle eight path BIP-8 errors detected error path frame).
high ROHCLK clock cycle each STS48c path BIP-8 error detected eight errors path frame).
Output
interleaved parity error (B3E) signal carries path BIP-8 errors detected STS-48c SONET payload. This signal valid non-STS-48c configurations.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
TTOH sampled rising edge TOHCLK.
When TTOHEN high during most significant byte positions TTOH, sampled byte logically XORed with associated incoming byte force errors outgoing byte. logic TTOH byte allows incoming through while logic high will toggle outgoing bit. level TTOHEN during byte disables error forcing entire byte. TTOHEN should grounded used. Transport overhead only inserted into first STS-12 slice this manner. TTOHEN sampled rising edge TOHCLK. transmit path overhead (TPOH) signal contains path overhead bytes (J1, transmitted STS-48c SONET path overhead error masks applied Path overhead only inserted within first STS-12 slice this manner. path overhead byte accepted transmission when external source indicates valid byte (TPOHEN high) S/UNI-2488 indicates ready (TPOHRDY high). S/UNI-2488 will ignore byte TPOH when TPOHEN low. TPOHRDY indicate that S/UNI2488 ready byte must re-presented next opportunity. TPOH should grounded used. TPOH sampled rising edge TOHCLK.
TPOH
Input
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
AH25
When TTOHEN high during most significant byte TTOH, sampled byte inserted into corresponding transport overhead byte positions (A1, D1-D3, D4-D12, Z1/S1, Z2/M1, undefined transport overhead bytes). When TTOHEN during most significant byte TTOH, that sampled byte ignored default values inserted into these transport overhead bytes.
TTOHEN
Input
AJ26
transmit transport overhead insert enable (TTOHEN) signal controls insertion transmit transport overhead data which inserted outgoing stream.
TTOH
Input
AK27
transmit transport overhead (TTOH) signal contains transport overhead bytes (A1, D1-D3, H1-H3, D4-D12, Z1/S1, Z2/M1, undefined transport overhead) transmitted error masks applied Transport overhead only inserted into first STS-12 slice this manner. TTOH should grounded used.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
TPOHEN
Input
AK26
System Side UTOPIA POS-PHY Signals (84)
Type
POSL3_UL3B
Input
RFCLK
Input
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Accepted bytes sampled TPOH inserted into corresponding path overhead byte positions (for bytes) master STS-12 slice only. byte TPOH ignored when TPOHEN during most significant position. When byte byte position TPOH accepted, used error mask modify corresponding transmit path overhead byte, respectively. accepted error mask XORed with corresponding byte before transmitted. TPOHEN should grounded used. TPOHEN sampled rising edge TOHCLK.
Function
UTOPIA/POS-PHY interface select (POSL3_UL3B) selects between UTOPIA Level POS-PHY Level modes system side interface. When POSL3_UL3B low, UTOPIA Level interface selected. When POSL3_UL3B high, POS-PHY Level interface selected. UTOPIA receive FIFO read clock (RFCLK) signal used read Acells from receive cell FIFO. RFCLK expected cycle MHz.
TPOHEN high during most significant byte indicate valid data TPOH input. This byte will accepted transmission TPOHRDY also high. TPOHRDY low, byte rejected must represented next opportunity.
transmit path overhead insert enable (TPOHEN) signal controls insertion transmit path overhead data which inserted outgoing stream.
TPOHRDY updated falling edge TOHCLK.
TPOHRDY high during most significant byte indicate readiness accept byte TPOH input. This byte will accepted TPOHEN also high. TPOHEN low, byte invalid ignored. TPOHRDY indicate that S/UNI-2488 unable accept byte TPOH expects byte represented next opportunity.
TPOHRDY
Output
AJ25
transmit path overhead insert ready (TPOHRDY) signal indicates S/UNI-2488 ready accept byte currently TPOH.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
RFCLK expected cycle MHz. RPRTY Output
RPRTY updated rising edge RFCLK. POS-PHY receive parity (RPRTY) signal indicates parity RDAT[31:0] bus. even parity selected. RPRTY valid only when either RVAL asserted. RPRTY updated rising edge RFCLK. RDAT[31] RDAT[30] RDAT[29] RDAT[28] RDAT[27] RDAT[26] RDAT[25] RDAT[24] RDAT[23] RDAT[22] RDAT[21] RDAT[20] RDAT[19] RDAT[18] RDAT[17] RDAT[16] RDAT[15] RDAT[14] RDAT[13] RDAT[12] Output
RDAT[31:0] updated rising edge RFCLK.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
UTOPIA receive cell data (RDAT[31:0]) carries Acell octets that read from receive FIFO.
RPRTY valid only when RENB been sampled previous clock cycle.
UTOPIA receive parity (RPRTY) signal indicates parity RDAT[31:0] bus. even parity selected.
POS-PHY receive FIFO read clock (RFCLK) signal used read packet data from receive packet FIFO.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
RENB
Input
RSOC
Output
RSOP
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
UTOPIA receive read enable (RENB) signal used initiate reads from receive FIFO. system deassert RENB time unable accept more data. read performed RDAT[31:0] does change when RENB sampled high. When RENB sampled low, word RDAT[31:0] read from receive FIFO RDAT[31:0] changes next value next clock cycle. RENB sampled rising edge RFCLK. POS-PHY receive read enable (RENB) signal used initiate reads from receive FIFO. During data transfer, RVAL must monitored since will indicate data valid. system deassert RENB time unable accept more data. read performed RDAT[31:0] does change when RENB sampled high. When RENB sampled low, word RDAT[31:0] read from receive FIFO RDAT[31:0] changes next value next clock cycle. RENB sampled rising edge RFCLK. UTOPIA receive start cell (RSOC) signal marks start cell structure RDAT[31:0] bus. first word cell structure present RDAT[31:0] when RSOC high. RSOC updated rising edge RFCLK. POS-PHY receive start packet (RSOP) signal indicates start packet RDAT[31:0] bus. RSOP high first word packet RDAT[31:0]. RSOP updated rising edge RFCLK
RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0]
RDAT[31:0] updated rising edge RFCLK.
POS-PHY receive packet data (RDAT[31:0]) carries packet octets that read from receive FIFO. RDAT[31:0] signals valid when RVAL RENB asserted.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
updated rising edge RFCLK. RVAL Output
RVAL updated rising edge RFCLK. RERR Output POS-PHY receive error (RERR) signal indicates that current packet invalid error such invalid FCS, excessive length received abort. RERR only assert when REOP asserted marking last word packet. RERR only used POS-PHY mode updated rising edge RFCLK.
RMOD[1] RMOD[0]
Output
REOP
Output
POS-PHY receive packet (REOP) signal marks packet RDAT[31:0] bus. legal RSOP high same time REOP high. REOP high mark last word packet presented RDAT[31:0] bus. When REOP high, RMOD[1:0] specifies last word valid bytes data. REOP only used POS-PHY operation updated rising edge RFCLK. POS-PHY receive modulo (RMOD[1:0]) indicates size current word when configured packet mode. During packet transfer, every word RDAT[31:0] must contain four valid bytes packet data except packet where word composed valid bytes. number valid bytes this last word specified RMOD[1:0]. RMOD[1:0] "00" RMOD[1:0] "01" RMOD[1:0] "10" RMOD[1:0] "11" RDAT[31:0] valid RDAT[31:8] valid RDAT[31:16] valid RDAT[31:24] valid
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
RMOD[1:0] considered valid only when RVAL asserted. RMOD[1:0] only used POS-PHY operation updated rising edge RFCLK.
RVAL will high when there valid data RDAT[31:0] bus. RVAL will transition when FIFO does have data give. RVAL will remain until programmable minimum number bytes end-of-packet (EOP) exists receive FIFO. threshold configurable.
POS-PHY receive data valid (RVAL) signal indicates validity receive data signals. When RVAL high, receive signals RDAT[31:0], RPRTY, RSOP, REOP, RMOD[1:0], RERR valid. When RVAL low, receive signals invalid must disregarded.
Output
UTOPIA receive cell available (RCA) signal provides direct status indication when cell available receive FIFO.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
TFCLK expected cycle rate. POS-PHY transmit FIFO write clock (TFCLK) signal used write packet data into transmit packet FIFO.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
TDAT[31] TDAT[30] TDAT[29] TDAT[28] TDAT[27] TDAT[26] TDAT[25] TDAT[24] TDAT[23] TDAT[22] TDAT[21] TDAT[20] TDAT[19] TDAT[18] TDAT[17] TDAT[16] TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0]
Input
POS-PHY transmit packet data (TDAT[31:0]) carries packet octets that written transmit FIFO. TDAT[31:0] considered valid only when TENB simultaneously asserted. TDAT[31:0] sampled rising edge TFCLK.
TDAT[31:0] sampled rising edge TFCLK.
TDAT[31:0] considered valid only when TENB simultaneously asserted.
UTOPIA transmit cell data (TDAT[31:0]) carries Acell octets that written transmit FIFO.
TFCLK expected cycle rate.
TFCLK
Input
UTOPIA transmit FIFO write clock (TFCLK) signal used write Acells transmit FIFO.
only used POS-PHY operation updated rising edge RFCLK.
Output
POS-PHY receive start transfer (RSX) signal indicates start packet transfer. When high, channel number being transferred given RDAT[31:0].
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
TSOP
TENB
Input
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
TSOC sampled rising edge TFCLK.
POS-PHY transmit start packet (TSOP) signal indicates start packet TDAT[31:0] bus. TSOP required present instances proper operation. TSOP must high first word packet TDAT[31:0]. TSOP considered valid only when TENB simultaneously asserted. TSOP sampled rising edge TFCLK. UTOPIA transmit write enable (TENB) signal active input which used initiate writes transmit FIFO. When TENB sampled high, information sampled TDAT[31:0], TPRTY TSOC signals invalid. When TENB sampled low, information sampled TDAT[31:0], TPRTY TSOC signals valid written into transmit FIFO. TENB sampled rising edge TFCLK.
TSOC
Input
UTOPIA transmit start cell (TSOC) signal marks start cell structure TDAT[31:0] bus. first word cell structure present TDAT[31:0] when TSOC high. TSOC must present each cell. TSOC considered valid only when TENB simultaneously asserted.
TPRTY sampled rising edge TFCLK.
TPRTY considered valid only when TENB simultaneously asserted.
POS-PHY transmit parity (TPRTY) signal indicates parity TDAT[31:0] bus. parity error indicated status maskable interrupt. Packets with parity errors still inserted transmit stream, TPRTY input unused. even parity selected.
TPRTY sampled rising edge TFCLK.
TPRTY considered valid only when TENB simultaneously asserted.
TPRTY
Input
UTOPIA transmit parity (TPRTY) signal indicates parity TDAT[31:0] bus. parity error indicated status maskable interrupt. Cells with parity errors still inserted transmit stream, TPRTY input unused. even parity selected.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
Note that regardless what level DTPA indicate "full", transmit packet processors still have full FIFO capacity store data. When DTPA transitions high, indicates that transmit FIFO enough room store configurable number data bytes. When DTPA transitions low, indicates that transmit FIFO either full near full configured. DTPA updated rising edge TFCLK.
TEOP
Input
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
POS-PHY transmit packet (TEOP) signal marks packet TDAT[31:0] when configured packet data. TEOP signal marks last word packet TDAT[31:0] bus. TMOD[1:0] signal indicates many bytes last word. legal TSOP high same time TEOP high order support byte packets. TEOP only valid when TENB simultaneously asserted. TEOP only used POS-PHY operation sampled rising edge TFCLK.
DTPA
POS-PHY direct transmit packet available (DTPA) signal provides status indication fill status transmit FIFO.
updated rising edge TFCLK.
When high, indicates that corresponding transmit FIFO full complete cell written. indicate either that transmit FIFO full.
Output
UTOPIA transmit cell available (TCA) signal provides direct status indication when cell space available transmit FIFO.
TENB sampled rising edge TFCLK.
When TENB sampled high, information sampled TDAT[31:0], TPRTY, TSOP, TEOP, TMOD[1:0], TERR signals invalid. When TENB sampled low, information sampled TDAT[31:0], TPRTY, TSOP, TEOP, TMOD[1:0], TERR signals valid written into transmit FIFO.
TENB (continued)
Input
POS-PHY transmit write enable (TENB) signal active input which used initiate writes transmit FIFOs.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
NaAPSIFPCLK
Type
Input
Serial Data Interface (20)
Function
input frame pulse clock (APSIFPCLK) provides jitter-free reference clock used sample input frame pulse (APSIFP). 777.76 Clock Synthesis Unit Port also uses this clock reference. APSIFPCLK expected cycle 77.76 rate, must synchronous with respect REFCLK_P REFCLK_N ensure that APSIFPCLK exact divide-bytwo frequency, compared REFCLK_P REFCLK_N.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
TMOD[1:0] considered valid only when TENB simultaneously asserted. TMOD[1:0] only used POSPHY operation sampled rising edge TFCLK.
TMOD[1:0] "00" TMOD[1:0] "01" TMOD[1:0] "10" TMOD[1:0] "11"
TDAT[31:0] valid TDAT[31:8] valid TDAT[31:16] valid TDAT[31:24] valid
TMOD[1:0]
Input
POS-PHY transmit word modulo (TMOD[1:0]) indicates size current word when configured packet mode. During packet transfer, every word TDAT[31:0] must contain four valid bytes packet data except packet where word composed valid bytes. number valid bytes this last word specified TMOD[1:0]
TERR only used POS-PHY operation sampled rising edge TFCLK.
TERR only considered valid when TENB TEOP simultaneously asserted.
TERR
Input
POS-PHY transmit error (TERR) signal used indicate that current packet must aborted. Packets marked with TERR will have abort sequence appended when transmitted. TERR should only asserted during last word packet being transferred TDAT[31:0].
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
APSO_P[3] APSO_N[3] APSO_P[2] APSO_N[2]
APSO_P[4] APSO_N[4]
Analog LVDS Output
APSO_P[1] APSO_N[1]
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
APSIFP sampled rising edge APSIFPCLK. differential output (APSO_P/ APSO_N[4:1]) serial data links carry SONET/SDH OC-48 frame data mate serial format. Each differential pair carries constituent OC-12 data stream. Data APSO_P/ APSO_N[4:1] encoded 8B/10B format extended from IEEE Std. 802.3. 8B/10B character received first received last. When working mode, using APSMUX_RCFP, APSMUX_T8TE APSMUX_TRMP register bits S/UNI-2488 Master Reset, Configuration Loopback register, APSO_P/ APSO_N[4:1] signals carry transmit data protect mate. When protect mode, APSO_P/ APSO_N[4:1] signals carry receive data working mate. four differential pairs APSO_P/ APSO_N[4:1] frequency locked phase locked. APSO_P/ APSO_N[4:1] nominally 777.6 Mbps data streams.
APSIFP
Input
input frame pulse signal (APSIFP) provides system timing input serial interface. APSIFP high once every 9720 APSIFPCLK cycles, multiple thereof, indicate that frame boundary 8B/10B character been delivered differential LVDS (APSI_P/ APSI_N[4:1]).
Input Port used, APSI_P/ APSI_N[4:1] must tied ground left floating. left floating, RXLV must disabled R8TD APS1-4 Analog Control registers.
four differential pairs APSI_P/ APSI_N[4:1] frequency locked phase locked. APSI_P/ APSI_N[4:1] nominally 777.6 Mbps data streams.
APSI_P[1] APSI_N[1]
When working mode, using APSMUX_RCFP, APSMUX_T8TE APSMUX_TRMP register bits S/UNI-2488 Master Reset, Configuration Loopback register, APSI_P/ APSI_N[4:1] signals carry receive data from protect mate. When protect mode, APSI_P/ APSI_N[4:1] signals carry transmit data from working mate.
APSI_P[2] APSI_N[2]
APSI_P[3] APSI_N[3]
APSI_P[4] APSI_N[4]
Analog LVDS Input
differential APSI input (APSI_P/ APSI_N[4:1]) serial data links carry SONET/SDH OC-48 frame data from mate serial format. Each differential pair carries constituent OC-12 data stream. Data APSI_P/ APSI_N[4:1] encoded 8B/10B format extended from IEEE Std. 802.3. 8B/10B character transmitted first transmitted last.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
NaCSB
Type
Input
Input
Input
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
N1P4N 2M1M2 N4L1M 3L2K1 M4K2J 1K3J2
A[13]/TRS
Input
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
active read enable (RDB) signal during S/UNI-2488 register read accesses. S/UNI-2488 drives D[15:0] with contents addressed register while low. active write strobe (WRB) signal during S/UNI-2488 register write accesses. D[15:0] contents clocked into addressed register rising edge while low. bi-directional data bus, D[15:0], used during S/UNI-2488 read write accesses.
test register select signal (TRS) selects between normal test mode register accesses. high during test mode register accesses, during normal mode register accesses. tied low.
Note that when being used, must tied low. required (i.e. register accesses controlled using signals only), must connected inverted version RSTB input.
active chip select (CSB) signal during S/UNI2488 register accesses.
Function
Microprocessor Interface Signals (37)
APSOFP updated rising edge APSIFPCLK.
This signal must used source APSIFP.
APSOFP
Output
output frame pulse signal (APSOFP) provides system timing output serial interface. APSOFP high once every 9720 APSIFPCLK cycles, multiple thereof, indicate approximate location frame boundary 8B/10B character differential LVDS (APSO_P/ APSO_N[4:1]).
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
RSTB
Input
NaTCK
Type
JTAG Test Access Port (TAP) Signals
Function
test clock (TCK) signal provides timing test operations that carried using IEEE P1149.1 test access port. test mode select (TMS) signal controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. When S/UNI-2488 configured JTAG operation, test data input (TDI) signal carries test data into S/UNI-2488 IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. test data output (TDO) signal carries test data S/UNI-2488 IEEE P1149.1 test access port. updated falling edge TCK. tri-state output that inactive except when scanning data progress.
Input
Input
Input
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
Tristate Output
INTB tri-stated when interrupt acknowledged appropriate register access. INTB open drain output.
INTB
Output
active interrupt (INTB) signal when S/UNI-2488 enabled interrupt source active. S/UNI2488 enabled report many alarms events interrupts.
address latch enable (ALE) active-high signal latches address A[13:0] when low. When high, internal address latches transparent. allows S/UNI-2488 interface multiplexed address/data bus. input integral pull resistor.
Schmidt Input
active reset (RSTB) signal provides asynchronous S/UNI-2488 reset. RSTB Schmidt triggered input with integral pull-up resistor.
A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
Input
J3H2J4 H3G2F 1H4G3 F2E1G 4E2D1
address (A[12:0]) selects specific registers during S/UNI-2488 register accesses.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
RESK
Analog
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
C0_CSU C1_CSU
Analog
AJ20 AK20
analog C0_CSU C1_CSU pins provided external capacitor clock synthesis unit. 100nF capacitor must placed between these pins applications. C0_CSU C1_CSU pins must left floating connection). Reference Resistor Connection. (RES/RESK) off-chip 3.16kW resistor connected between positive resistor reference Kelvin ground contact RESK port LVDS reference. on-chip negative feedback path will force 0.8V VREF voltage onto RES, therefore forcing 252µA current flow through resistor. RESK electrically connected AVSS within block, should connected AVSS, either on-chip off-chip.
C0_CRU C1_CRU
Analog
AG18A
analog C0_CRU C1_CRU pins reserved external capacitor clock recovery unit. 10nF nonpolarized capacitor across pins required applications. C0_CRU C1_CRU pins must left floating connection).
ATP_2488[1:0] test ports 2488 Mbps analog circuitry. ATP_1250[1:0] test ports 777.76 LVDS analog circuitry.
ATP_2488[0] ATP_2488[1] ATP_1250[0] ATP_1250[1]
Analog
AJ18 AK18
Four analog test ports provided production testing only. These pins must tied analog ground (AVS) during normal operation.
Type
Function
Analog Miscellaneous Signals (10)
TRSTB
Schmidt Input
active test reset (TRSTB) signal provides asynchronous S/UNI-2488 test access port reset IEEE P1149.1 test access port. TRSTB Schmidt triggered input with integral pull resistor. TRSTB must asserted some point after power before device registers accessed.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
NaAVDH (25)
Type
Analog Power
AVDL(16)
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
QAVD
Analog Power
AG20 AH20
Analog Power
AG21 AH21 AJ21 AK21
analog power (AVDL) pins analog core. AVDL pins should connected through passive filtering networks well-decoupled +1.8V analog power supply. Please Operation section detailed information.
quiet power (QAVD) pins analog core. QAVD should connected well-decoupled analog +3.3V supply. These power pins should decoupled separately from analog power pins (AVDH).
AH17 AH14 AH10 AJ10 AJ14 AJ17 AJ19 AK19 AG10 AH19 AG19 AG17 AG14
analog power (AVDH) pins analog core. AVDH pins should connected through passive filtering networks well-decoupled +3.3V analog power supply. Please Operation section detailed information.
Function
9.10
Analog Power Ground (105)
S/UNI-2488 Telecom Standard Product Datasheet Releas
NaVDDI
Type
Core Power
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
AA28 AH26 AG24
core power (VDDI) pins should connected welldecoupled +1.8V digital power supply.
Function
9.11
Digital Power Ground
S/UNI-2488 Telecom Standard Product Datasheet Releas
NaVSS (124)
Type
Digital Ground
AK14 AG15 AH15 AJ15 AG16 AH16 AJ16 AK17 AK22
9.11.1
Digital Ground
Function
AG11 AH11 AJ11 AK11 AG12 AH12 AJ12 AG13 AH13 AJ13 AK30 AJ30 AH29 AA27 AA29 AA30 AB27 AB28 AB30 AC27 AC28 AC29 AD27 AD28 AD29 AD30 AE27 AE28 AE30 AF27 AF28 ground (VSS) pins should connected inductance ground plane connected both digital analog power supplies. Please Operation section detailed information.
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
VDDO
power
AG27 AH28 AJ29
power (VDDO). VDDO pins should connected well-decoupled +3.3 power supply.
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000489, Issue
S/UNI-2488 inputs bidirectionals present minimum capacitive loading operate CMOS/LVTTL logic levels except REFCLK_P REFCLK_N, RXD_P/ RXD_N, TXD_P/ TXD_N pins which operate pseudo-ECL (PECL) logic levels APSI_P/ APSI_N[4:1], APSO_P/ APSO_N[4:1] pins which operate LVDS logic levels.
Notes Description:
Interface Inputs Outputs Bidir Analog Total Serial Line Side Interface Clocks Alarms Receive Section/Line/Path Overhead Insertion Transmit Section/Line/Path Overhead Insertion System Side Utopia port Microprocassor JTAG Test Access Port Analog misc Analog power/gnd Totals
9.12
Summary
(17)
Connect
AB29 AC30 AE29 AG28 AH22 AJ22
connect
9.11.2
Connects
AK23 AJ28 AK29
AF29 AF30 AG29 AG30 AH30
Type
Function
S/UNI-2488 Telecom Standard Product Datasheet Releas
S/UNI-2488 digital outputs bidirectionals which have drive capability are: CRUCLKO CSUCLKO

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