part ATLANTA chip consisting four devices that provide highly integrat

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

part ATLANTA chip consisting four devices that provide highly integrat

Datasheet Thumbnail

Top Searches for this datasheet

LUC4AS01 ASwitch Element (ASX)
part ATLANTA chip consisting four devices that provide highly integrated, innovative, complete VLSI solution implementing Alayer core Aswitch system. chip enables construction high-performance, feature-rich, cost-effective Aswitches, scalable over wide range switching capacities. This document discusses device.
programmable, weighted, round-robin scheduler servicing delay priorities. Provides efficient unrestricted multicasting with single copy storage. Incorporates independent clocking input ports facilitate robust distributed systems designs allowing independent port card clocks arbitrary clock skew introduced across backplanes from separate port cards. Uses differential clocking provide noise immunity. Parity cell insertion/extraction detecting tracking system errors. Provides system diagnostic features, including detection reporting following error conditions: Input port parity error. Input port overrun error. Loss input port clock. error outgoing cell. Linked list fault indication. Test cell extraction. Provides several performance/traffic indicators. Supports generic Intel* Motorola compatible 16-bit microprocessor interface with interrupt. Facilitates circuit board testing with on-chip IEEE standard boundary-scan. Fabricated low-power monolithic CMOS technology, with tolerant TTLlevel compatible I/O. Available 388-pin PBGA package.
Features
Functions highly efficient, Gbits/s, shared memory, Aswitching element scalable switch fabrics Gbits/s. stand-alone mode, used switch fabric with Mbits/s rates. used building block larger fabrics ports with Mbits/s rate Gbits/s total Athroughput). three-stage mode, supports variable expansion factors (4:8, 5:8, 6:8) more compact fabric design with higher port density. Works with other ATLANTA devices provide total system solutions Aswitching. Directly interfaces with LUC4AB01 ABuffer Manager (ABM) chip support port card buffering. Directly interfaces with LUC4AC01 ACrossbar Element (ACE) chip constructing larger nonblocking, lossless, self-routing switch fabrics, organized into three-stage topology. Incorporates novel internal backpressure algorithm based separate on-chip queues fabric ports enable large scale cell buffers port cards cells port) using costeffective commonly available SRAMs. internal cell memory, fully shared across queues, supplemented port card buffers. Supports four delay priorities queue uses
Intel registered trademark Intel Corporation. Motorola registered trademark Motorola, Inc. IEEE registered trademark Institute Electrical Electronics Engineers, Inc.
LUCENT TECHNOLOGIES-PROPRIETARY pursuant Company Instructions
Section
LUC4AS01 ASwitch Element (ASX)
port rates, building block larger three stage switch fabrics OC-12 equivalent ports, Gbits/s systems). interfaces directly both ATLANTA LUC4AC01 ACrossbar Element (ACE) device (for linking switch elements) LUC4AB01 ABuffer Manager (ABM) device (for buffer management). High-performance, nonblocking, lossless, self-routing switch fabrics constructed using ATLANTA chip set.
Description
Figure shows architecture Aswitch designed with ATLANTA chip set. This document summarizes ATLANTA switch fabrics LUC4AS01 ASwitch Element (ASX). ATLANTA device provides switching function Aswitch fabric. This switch element functions complete Gbits/s switch fabric with OC-12 equivalent
INGRESS DIRECTION EGRESS DIRECTION
PORTS
SRAM
SRAM LUC4AS01 LUC4AS01 REDUNDANT BACKPLANE SWITCH FABRIC MICROPROCESSOR INTERFACE LUC4AC01 LUC4AS01 LUC4AC01 LUC4AS01
LUC4AU01
LUC4AB01
MICROPROCESSOR INTERFACE LINE CARD PHYSICAL LAYER INTERFACE (MPHY) BACKPLANE SRAM
PORTS SRAM
LUC4AS01
LUC4AC01
LUC4AS01
LUC4AU01 LUC4B01
LUC4AS01 LUC4AC01 LUC4AS01
Section
MICROPROCESSOR INTERFACE LINE CARD
MICROPROCESSOR INTERFACE REDUNDANT SWITCH FABRIC
5-4554r9
Figure Architecture ASwitch Using ATLANTA Chip
LUCENT TECHNOLOGIES-PROPRIETARY pursuant Company Instructions
Lucent Technologies Inc.
LUC4AS01 ASwitch Element (ASX)
able SRAMs. provides efficient unrestricted multicasting with single copy storage. also provides system diagnostic features. Diagnostic reports include parity errors inputs, internal memory overrun errors, loss input port clock. addition, calculated data input ASX, passed through ASX, then calculated after data switched ensure that silicon errors have been introduced. When error detected, parity error indicated data output from ASX. Test cell extraction through microprocessor interface also aids testability. block diagram brief description functionality follows.
Description (continued)
internal cell memory, fully shared across queues; external SRAM required fabric. supports four delay priorities queue uses programmable weighted round-robin algorithm scheduling delay priority service. Novel techniques incorporated congestion management. innovative Bell Labs-developed adaptive dynamic threshold algorithm permits efficient buffer sharing while preventing queue from seizing disproportionate share cell buffer. novel internal backpressure algorithm applied prevent fabric cell buffer from overflowing increase buffer sharing large-scale buffers port cards using cost-effective, commonly avail-
INGRESS PORTS
INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR BUFFER MEMORY (BMEM)
OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR
EGRESS PORTS
(DATA) (PARITY) (START CELL) (CLOCK)
QUEUE PROCESSOR (QP)
(DATA) (PARITY) (START CELL) (CLOCK)
GTSYNC SYSTEM CLOCK (GCLK) CLOCKING SYNCHRONIZATION FEEDBACK GENERATION CIRCUIT
(CB1_m, CB2_n) FIRST/THIRD STAGE BACKPRESSURE (F1T3_1, F1T3_E, F1T3CLK) RESET (GRST)
MICROPROCESSOR INTERFACE
CONFIGURATION STATUS REGISTERS CELL EXTRACTION FIFO (MPI)
TEST ACCESS PORT (JTAG)
OUTPUT ENABLE (ASXOE) TEST ACCESS PORT
5-4515aR9
Figure Block Diagram
Lucent Technologies Inc.
LUCENT TECHNOLOGIES-PROPRIETARY pursuant Company Instructions
Section
SOURCE ARBITER (ARB)
LUC4AS01 ASwitch Element (ASX)
stage (concentrator). center stage consists companion device. functionally similar ASX, without internal cell buffer handshake protocol between ensures that need store data). Conceptually, first-stage expands number paths available switching data, while third stage concentrates data from center stage. device supports 4:8, 5:8, expansion modes. expansion mode configurable, depending cost performance objectives, well type traffic expected. three-stage ASX/ACE based switch fabric support ports with Mbits/s rates. 40-port Gbits/s total Athroughput) fabric design would eight devices stage expansion mode.
Description (continued)
Overview
shown Figure data each port clocked into input processor, passed internal cell buffers, then routed appropriate output processor. queue processor, routing arbitration circuit, backpressure feedback generation circuit controls movement data into cell buffer memory. Control status communicated through 16-bit asynchronous microprocessor interface. Figure shows example ATLANTA-based switch fabric. switch fabric will switch inputs outputs. This achieved staging devices referred three-stage switch fabric. input stage called first stage (expander), output stage called third
FIRST-STAGE EXPANDER
CENTER-STAGE CROSSBAR
THIRD-STAGE CONCENTRATOR
MODULE
MODULE
MODULE
MODULE
MODULE
MODULE OUTPUT PORT CARDS
Section
INPUT FROM PORT CARDS
MODULE
MODULE
MODULE
MODULE
MODULE
MODULE
5-4523R5
Figure Example Mbits/s Switch Fabric Gbits/s throughput)
LUCENT TECHNOLOGIES-PROPRIETARY pursuant Company Instructions
Lucent Technologies Inc.
LUC4AS01 ASwitch Element (ASX) Queue Processor
queue processor controls movement data from cell buffer memory maintains buffer memory statistics. There eight queue controllers within queue processor. Incoming cells routed more queue controllers.
Description (continued)
Input Processors
input processors responsible accepting data onto device. There eight input processors, each port. inputs used regardless expansion factor. Each input port eight data bits, parity bit, start cell bit, differential clock. microprocessor must enable appropriate input ports. input processor does preliminary processing stores header, payload, internally generated CRC-8 arriving cell until written internal cell buffer. Input ports clocked independently from MHz. This independent clocking facilitates backplane based system designs with distributed port cards. input port interface designed minimize risk undetected errors. differential clock provides system noise immunity prevent errors. addition, input processor detects presence input clock reports when input clock lost. input processor also checks incoming parity errors. And, internal CRC-8 generated each Acell that transferred internal cell buffer switching. then checked before switched data transferred device. Furthermore, input processor also detects reports input port overrun errors.
Source Arbiter
source arbiter (ARB) determines which queues will serviced device output ports. operation arbiter depends whether device configured stand-alone, first stage, third stage module. Cells from different queues same queue. eight cells selected, device output port. also interprets optional egress backpressure information from port cards.
Microprocessor Interface
microprocessor interface (MPI) provides general 16-bit asynchronous interface external processor accessing configuration status registers internal memory. also supports perfunction, maskable interrupts. interface operates identically interface ALM, ABM, ACE. designed support various 16-bit microprocessors with minimal glue logic, directly interface popular Intel Motorola microprocessors.
Buffer Memory
Output Processors
output processors perform many same functions input processor. They handle postprocessing shifting data. microprocessor disable appropriate output ports.
incorporates logic support standard fivepin test access port (TAP), compatible with IEEE P1149.1 standard (JTAG), used boundary scan. contains instruction registers, data registers, control logic, instructions. controlled externally JTAG master. gives board-level test capability.
Lucent Technologies Inc.
LUCENT TECHNOLOGIES-PROPRIETARY pursuant Company Instructions
Section
contains cells internal memory. This memory shared among active system ports 40). buffer memory stores local header, Aheader, cell payload until this data shifted appropriate output port.
Test Access Port
LUC4AS01 ASwitch Element (ASX)
additional information, contact your Microelectronics Group Account Manager following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 data requests Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 299, (44) 1734 technical inquiries Europe: CENTRAL EUROPE: (49) 95086 (Munich), NORTHERN EUROPE: (44) 1344 (Bracknell UK), FRANCE: (33) (Paris), SOUTHERN EUROPE: (39) 6601 1800 (Milan) (34) 1700 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information.
Copyright 1997 Lucent Technologies Inc. Rights Reserved Printed U.S.A.
March 1997 PN96-065APrinted Recycled Paper

part ATLANTA chip consisting four devices that provide highly integrat

Top Searches for this datasheet

Other recent searches