AAL1GATOR-4/8 Proprietary Confidential Released Issue June 2002
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AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
AAL1GATOR-4/8
Proprietary Confidential Released Issue June 2002
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2000098 Issue
Data Sheet
AAdaptation Layer Segmentation Reassembly Processor-4/8
PM73124 PM73123
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Copyright 2002 PMC-Sierra, Inc. rights reserved.
Disclaimer
Patents
Granted
technology discussed this document protected more following patent grants: U.S. Patent 5,844,901
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Other relevant patent grants also exist.
PMC-Sierra registered trademark PMC-Sierra, Inc. PMC-Sierra. Other product company names mentioned herein trademarks their respective owners.
Trademarks
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Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Site: http://www.pmc-sierra.com
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PMC-Sierra 8555 Baxter Place Burnaby, Canada
Contacting PMC-Sierra
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
June 2002
Created data sheet from issue doc.
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Issue
Issue Date
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AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Disclaimer Trademarks Contacting PMC-Sierra. Table Contents. List Registers. List Figures List Tables. Features References. AMulti-service Switch
Description Description UTOPIA Interface Signals (52) Interface Signals(40) Line Interface Signals(Direct)(67) Line Interface Signals(H-MVIP)(12) Clock Generation Control Interface(14) JTAG/TEST Signals(7) General Signals(3+power/gnd) UTOPIA Interface Block (UI) AAL1 Processing Block (A1SP). AAL1 Clock Generation Control Microprocessor Interface Signals (42)
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Functional Description
Diagram
Block Diagram.
APassive Optical Networks (APON)
Application Examples.
Applications.
Revision History.
Patents
Copyright.
Legal Information.
Table Contents
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
14.2 10.1 10.2 10.3 10.4 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8
Processor Interface Block (PROCI) Interface Block (RAMI) JTAG Test Access Port. Initialization. A1SP Line Configuration Structures Transmit Structures Summary. Receive Data Structures Summary Command Registers. Interface Registers UTOPIA Interface Registers Direct Mode Registers. Interrupt Status Registers. Change Detection Configuration Registers Control Status Registers Line Interface Block (AAL1_LI)
Normal Mode Register Description
Functional Timing. 14.1 14.2 14.3 14.4 14.5 14.6 Source Utopia. Sink Utopia Processor External Clock Generation Control (CGC) Freq Select Interface. Line Interface Timing
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Absolute Maximum Ratings D.C. Characteristics A.C. Timing Characteristics.
13.5
JTAG Support.
13.4
Special Queue Configuration Modes
13.3
UTOPIA Interface Configuration.
13.2
Start-Up
13.1
Hardware Configuration
Operation
JTAG Test Port
Line Interface Registers
Memory Mapped Register Description
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9
Reset Timing SYS_CLK Timing. Microprocessor Interface Timing Characteristics Interface Utopia Interface LINE Timing. JTAG Timing. NCLK Timing External Clock Generation Control Interface
Ordering Thermal Information. Mechanical Information. Definitions Notes
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AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Register 0x80020 A1SP Queue FIFO Register (A_ADDQ_FIFO) Register 0x80030 A1SP Clock Configuration Register (A_CLK_CFG) Register 0x80120 Common Configuration Register (UI_COMN_CFG) Register 0x80122 Sink Config (UI_SNK_CFG)
Register 0x80210H Line Mode Register(LINE_MODE_REG) Register 0x81000 Master Interrupt Register (MSTR_INTR_REG) Register 0x81010 A1SP Interrupt Register (A1SP_INTR_REG) Register 0x81020 A1SP Status Register (A1SP_STAT_REG) Register 0x81040 A1SP Receive Status FIFO (A1SP_RSTAT_FIFO). Register 0x81110 A1SP Interrupt Enable Register (A1SP_EN_REG) Register 0x81150 Receive Queue Error Enable (RCV_Q_ERR_EN) Register 0x82220 A1SP Change Detection Enable Table Register 0x82300-0x823FF A1SP Change Configuration Table. Register 0x84000H Configuration Register (DLL_CFG_REG) Register 0x84002H Reset Register (DLL_SW_RST_REG) Register 0x84003H Control Status Register (DLL_STAT_REG) Register 0x81030 A1SP Change FIFO (A1SP_CASCHG_FIFO) Register 0x81100 Master Interrupt Enable Register (MSTR_INTR_EN_REG) Register 0x81140 Receive Status FIFO Enable Register (RSTAT_EN_REG).
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Register 0x80200H, .03H: Speed Line Configuration Registers(LS_Ln_CFG_REG).
Register 0x80125 Loopback (U2U_LOOP_VCI)
Register 0x80124 Slave Sink Address Config Register (UI_SNK_ADD_CFG)
Register 0x80123 Slave Source Address Config Register (UI_SRC_ADD_CFG)
Register 0x80121 Source Config (UI_SRC_CFG).
Register 0x80100 Configuration Register (RAM_CFG_REG)
Register 0x80010 A1SP Command Register (A_CMD_REG)
Register 0x80000 Reset Device Register (DEV_ID_REG)
List Registers
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Figure AAL1gator-4/8 Internal Block Diagram Figure Data Flow Buffering A1SP Block Figure A1SP Block Diagram. Figure Capture Signaling Bits (SHIFT_CAS=0). Figure Transmit Frame Transfer Controller. Figure SDF-MF Format T_DATA_BUFFER. Figure SF-SDF-MF Format T_DATA_BUFFER. Figure SDF-FR Format T_DATA_BUFFER Figure SDF-MF with Signaling Format T_DATA_BUFFER. Figure Unstructured Format T_DATA_BUFFER. Figure SDF-MF Format T_SIGNALING BUFFER Figure SDF-MF Format T_SIGNALING_BUFFER Figure SDF-MF with Signaling Format T_SIGNALING_BUFFER.
Figure Change Configuration Register Structure. Figure Frame Advance FIFO Operation. Figure Local Loopback Figure Cell Header Interpretation Figure Fast Algorithm Figure Payload Generation
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Figure Receive Cell Processing Fast Figure Robust Algorithm. Figure Cell Reception Figure SDF-MF Format R_DATA_BUFFER Figure SDF-MF Format R_DATA_BUFFER
Figure Change Interrupt Word
Figure Transmit Side SRTS Function.
Figure SDF-MF Format T_SIGNALING_BUFFER
Figure SDF-FR Format T_DATA_BUFFER.
Figure SDF-MF Format T_DATA_BUFFER
Figure Capture Signaling Bits (SHIFT_CAS=0)
Figure Block Diagram
Figure AAL1gator-4/8 APON Application
Figure AAL1gator-4/8 Integrated Access Device (IAD) Application.
List Figures
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Figure SDF-FR Format R_DATA_BUFFER. Figure SDF-MF Format R_DATA_BUFFER Figure SDF-FR Format R_DATA_BUFFER Figure SDF-MF Format R_SIG_BUFFER. Figure SDF-MF format R_SIG_BUFFER Figure SDF-MF Format R_SIG_BUFFER Figure Pointer/Structure State Machine Figure Overrun Detection Figure Output Signaling Bits (SHIFT_CAS=0) Figure Output Signaling Bits (SHIFT_CAS=0). Figure Receive Side SRTS Support. Figure SRTS Data Figure Channel Status Functional Timing Figure Adaptive Data Functional Timing Figure Freq Select Functional Timing Figure Direct Adaptive Clock Operation Figure A1SP SRAM Memory Map. Figure Transmit Data Structures Memory Figure Receive Data Structures Figure Normal Mode Registers Memory Figure Interrupt Hierarchy Figure ADDQ_FIFO Word Structure Figure Line Interface Block Architecture Figure Capture Signaling Bits Figure Capture Signaling Bits Figure Output Signaling Bits Figure Output Signaling Bits Figure SDF-MF Format T_SIGNALING BUFFER. Figure SDF-MF with Signaling Format R_SIG_BUFFER. Figure SDF-MF with Signaling Format R_DATA_BUFFER Figure Unstructured Format R_DATA_BUFFER
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Figure Control Registers Memory
Figure Memory
Figure Receive Side SRTS Support.
Figure Channel-to-Queue Table Operation.
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Figure R_CRC_SYNDROME Mask Table Legend Figure Boundary Scan Architecture Figure Input Observation Cell (IN_CELL) Figure Bidirectional Cell (IO_CELL) Figure Layout Output Enable Bidirectional Cells. Figure Pipelined Single-Cycle Deselect SSRAM Figure SRC_INTF Start Transfer Timing (Utopia AMode) Figure SRC_INTF End-of-Transfer Timing (Utopia AMode) Figure UI_SRC_INTF Start-of-Transfer Timing (Utopia Mode) Figure UI_SRC_INTF End-of-Transfer (Utopia Mode) Figure UI_SRC_INTF End-of-Transfer Timing (Utopia Mode) Figure UI_SRC_INTF Start-of-Transfer Timing (Any-PHY Mode). Figure UI_SRC_INTF End-of-Transfer Timing (Any-PHY mode) Figure SNK_INTF Start-of-Transfer Timing (Utopia AMode) Figure SNK_INTF End-of-Transfer Timing (Utopia AMode) Figure SNK_INTF Start-of-Transfer Utopia Figure SNK_INTF End-of-Transfer Utopia Figure SNK_INTF End-of-Transfer (Any-PHY Mode). Figure Microprocessor Write Access. Figure Microprocessor Read Access Figure Microprocessor Write Access with Figure Microprocessor Read Access with Figure SRTS Data Figure Channel Status Functional Timing Figure Adaptive Data Functional Timing Figure Freq Select Functional Timing Figure Receive Line Side Timing(RL_CLK 1.544 MHz) Figure Receive Line Side Timing(RL_CLK 2.048 MHz) Figure Pipelined SSRAM. Figure Controller Finite State Machine. Figure Output Cell (OUT_CELL)
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Figure SNK_INTF Start-of-Transfer (Any-PHY Mode).
Figure SNK_INTF CLAV Disable Utopia
Figure SNK_INTF Start-of-Transfer Timing (Utopia Mode)
Figure UI_SRC_INTF Start-of-Transfer Timing (Utopia Mode)
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Figure MVIP-90 Receive Functional Timing. Figure Transmit Line Side Timing(TL_CLK 1.544 MHz). Figure MVIP-90 Transmit Functional Timing. Figure Receive H-MVIP Timing, Expanded View. Figure Transmit H-MVIP Timing, Close-up View Figure Transmit H-MVIP Timing, Expanded View. Figure Transmit High-Speed Functional Timing. Figure RSTB Timing Figure SYS_CLK Timing Figure NCLK Timing Figure Microprocessor Interface Write Timing Figure External Clock Generation Control Interface Timing Figure Interface Timing Figure Sink UTOPIA Interface Timing Figure Source UTOPIA Interface Timing Figure Receive Speed Interface Timing Figure H-MVIP Ingress Data Timing Figure Receive High Speed Interface Timing Figure JTAG Port Interface Timing. Figure Receive High-Speed Functional Timing. Figure Transmit Line Side Timing(TL_CLK 2.048 MHz). Figure Receive H-MVIP Timing, Close-Up View.
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Figure Transmit High Speed Timing.
Figure H-MVIP Sink Data Frame Pulse Timing
Figure Transmit Speed Interface Timing
Figure Microprocessor Interface Read Timing
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Table CFG_ADDR PHY_ADDR Usage direction Table Minimum Partial Cell Size Permitted Connections Active Table Buffer Depth Table Frequency Select Mode Table LINE_MODE Encoding. Table AAL1gator-4/8 Memory Table A1SP Line Configuration Structures Summary. Table Transmit Structures Summary. Table R_QUEUE_TBL Format Table Command Register Memory Table UTOPIA Interface Registers Memory Map. Table CFG_ADDR PHY_ADDR Usage direction Table Line Interface Register Memory Summary. Table Direct Mode Register Memory Table Change Detection Configuration Registers Memory Table Control Status Registers Memory Map. Table Instruction Register Table Identification Register Table Boundary Scan String AAL1gator-8. Table Boundary Scan String AAL1gator-4. Table Interrupt Status Registers Memory Table CFG_ADDR PHY_ADDR Usage direction
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Table Channel Status Table Frame Difference. Table Absolute Maximum Ratings. Table AAL1GATOR-4/8 D.C. Characteristics
Table Interface Registers Memory
Table Register Memory
Table R_CRC_SYNDROME Mask Table
Table Frequency Select Mode
Table Channel Status
Table CFG_ADDR PHY_ADDR Usage direction
Table Line Interface Signal Table Selection.
List Tables
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Table RTSB Timing Table SYS_CLK Timing Table Microprocessor Interface Read Access Table External Clock Generation Control Interface. Table Interface. Table UTOPIA Source Sink Interface Table Receive Speed Interface Timing Table H-MVIP Sink Timing Table H-MVIP Source Timing. Table Transmit High Speed Interface Timing. Table JTAG Port Interface. Table AAL1GATOR-4/8 (PM73123/4) Ordering Information. Table AAL1GATOR-4/8 (PM73123/4) Thermal Information Table Transmit Speed Interface Timing Table NCLK Timing Table Microprocessor Interface Write Access.
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Table Receive High Speed Interface Timing.
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Provides AAL1 segmentation reassembly individual lines, H-MVIP lines MHz, STS-1 unstructured lines. Provides standard UTOPIA level Interface which optionally supports parity runs MHz. Only Cell Level Handshaking supported. MPHY mode, like single port port device. following modes supported: 8/16-bit Level Multi-Phy Mode (MPHY) 8/16-bit Level SPHY 8-bit Level AMaster Supports 256(A8)/128(A4) Virtual Channels (VC).
Allows nibble coincident with either first second nibble data. Provides per-VC data signaling conditioning transmit cell direction data signaling conditioning transmit line direction. Data signaling conditioning individually enabled. Includes conditioning support both directions. Transmit line conditioning options include programmable byte pattern, pseudorandom pattern data. Conditioning automatically occurs underruns.
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Cell Transmit direction, provides per-VC configuration time slots allocated, signaling support, partial cell size, data signaling conditioning, ACell header definition. Generates AAL1 sequence numbers, pointers SRTS values accordance with ITU-T I.363.1. Multicast connections supported. Cell Transmit direction provides counters for: Conditioned cells transmitted each queue Cells which were suppressed each queue Total number cells transmitted each queue
Provides transparent transmission Common Channel Signaling (CCS) Channel Associated Signaling (CAS). Provides termination signaling.
Supports (consecutive channels) (non-consecutive channels) structured data format.
Provides optional 8/16-bit Any-PHY slave interface.
Compliant with AForum's Circuit Emulation Services (CES) specification (AFVTOA-0078), ITU-T I.363.1
AAL1 Segmentation Reassembly (SAR) Processor (AAL1gator-4/8) monolithic single chip device that provides DS1, line interface access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. arbitrates access external SRAM storage configuration, user data, statistics. device provides microprocessor interface configuration, management, statistics gathering. PMC-Sierra also offers software device control package AAL1gator-4/8 device.
Features
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
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each receive queue following sticky bits maintained: Cell received Structured pointer rule error detected Cell dropped blank allocation table Cells dropped pointer search Cell dropped forced underrun Cell dropped sequence number processing algorithm Valid pointer received Pointer parity error detected SRTS resume from underrun condition SRTS underrun occurred Resume occurred from underrun condition Pointer reframe occurred Overrun condition detected Cell received while underrun
Cell Receive direction provides counters following events which include counters required AForum's CES-IS MIB: Incorrect sequence numbers queue Incorrect sequence number protection fields queue Total number received cells queue Total number dropped cells queue Total number underruns queue Total number lost cells queue Total number overruns queue Total number reframes queue Total number pointer parity errors queue Total number misinserted cells queue Total number non-data cells received Total number non-data cells dropped.
Cell Receive direction, supports Fast Sequence Number processing algorithm types connections Robust Sequence Number processing Unstructured Data Format (UDF) connections. Cells inserted/dropped maintain integrity lost misinserted cells. integrity maintained through single errored cell lost cells. integrity also optionally maintained even underrun occurs. Pointer bytes, signaling bytes taken into account. Cell insertion options include programmable single byte pattern, pseudo-random data, data
Cell Receive direction, provides per-VC configuration time slots allocated, signaling support, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. Processes AAL1 headers accordance with ITU-T I.363.1.
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
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Provides 16-bit microprocessor interface internal registers, external 128K 16(18) Pipelined Single-Cycle Deselect Synchronous SRAMs, Synchronous SRAMs.
each AAL1 block following conditions cause interrupt, each which masked. Separate entry FIFOs AAL1 block used track receive transmit status. receive queue sticky just (individual mask sticky bit) Receive queue entered underrun state Receive queue exited underrun state Receive Status FIFO overflow Transmit Frame Advance FIFO full Reception cells change occurred Line frame resync event Transmit ALayer Processor (TALP) FIFO full
Provides single maskable, open-collector interrupt with master interrupt register facilitate interrupt processing. master interrupt register indicates following conditions each which masked: Error/status condition with four AAL1 blocks parity error UTOPIA parity error Transmit UTOPIA FIFO full Transmit UTOPIA transfer error UTOPIA loopback FIFO full UTOPIA runt cell detected
Queues added making entries into add-queue FIFO minimize queue activation overhead. offset configured when queue added distribute cell build times minimize clumping.
Provides patented frame based calendar queue service algorithm with anti-clumping addqueue mechanism that produces minimal Cell Delay Variation (CDV). mode uses non-frame based scheduling optimize CDV. addition, four internal cell generation engines work parallel further insure CDV.
Provides system side loopback support. When enabled incoming matches programmable loopback VCI, cell received Receive UTOPIA interface looped back Transmit UTOPIA interface. Alternatively UTOPIA interface into remote loopback mode where incoming cells looped back out. Provides line side loopback, enabled queue basis, which loop single channel group channels which mapped single queue.
Supports AAL0 mode, selectable basis.
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
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324-pin fine-pitch plastic ball grid array (PBGA) package.
Low-power Volt CMOS technology with Volt, Volt tolerant I/O.
clock synthesizers also controlled externally provide customization SRTS adaptive algorithms. SRTS also disabled hardware input. Adaptive SRTS information output port external processing both speed high speed mode, needed. Buffer depth provided units bytes. synthesizer discrete frequencies between either +/-100 +/-200
Includes internal E1/T1 clock synthesizer each line which generate nominal E1/T1 clock controlled Synchronous Residual Time Stamp (SRTS) clock recovery method Unstructured Data Format (UDF) mode programmable weighted moving average adaptive clocking algorithm. SRTS adaptive clocking supported using external clock synthesizer clock control port.
Integrates internal T1/E1 Adaptive Clock recovery circuit T1/E1 line.
Integrates internal T1/E1 SRTS Clock recovery circuit T1/E1 line.
Provides transmit buffer which used Operations, Administration Maintenance (OAM) cells well other user-generated cells such AAL5 cells Asignaling. corresponding receive buffer exists reception cells non-AAL1 data cells.
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2000098 Issue
APassive Optical Network Equipment
Wireless Local Loop Back Haul
Computer Telephony Chassis with Ainfrastructure
Digital Cross Connect
AAccess Concentrator
Multi-service ASwitch
Applications
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
PMC-971268, "High density T1/E1 framer with integrated VT/TU mapper multiplexer" (TEMUX), 2000, Issue GO-MVIP, "MVIP-90 Standard" Release 1.1, October 1994. GO-MVIP, "H-MVIP Standard" Release 1.1a, January 1997.
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ITU-T Recommendation G.824 Control Jitter Wander within Digital Networks Which Based 1544 kbit/s Hierarchy, March 1993.
ITU-T Recommendation G.823, Control Jitter Wander within Digital Networks Which Based 2048 kbit/s Hierarchy, March 1993.
ITU-T Recommendation I.363.1, B-ISDN AAdaptation Layer (AAL) Specification, July 1995.
ITU-T Recommendation G.703, Physical/Electrical Characteristics Hierarchical Digital Interfaces, April 1991.
AForum, UTOPIA, ATM-PHY Layer Specification, Level 1.0, Foster City, USA, June 1995.
AForum, UTOPIA, ATM-PHY Layer Specification, Level 2.01, Foster City, USA, March 1994.
AForum, Circuit Emulation Service Interoperability Specification (CES-IS), 2.0, Foster City, USA, August 1996.
AForum, AUser Network Interface (UNI) Specification, 3.1, Foster City, USA, September 1994.
ANSI Recommendation T1.630, Broadband ISDN-AAdaptation Layer Constant Rate Services, Functionality Specification, 1993.
ANSI Recommendation T1.403, Network-to-Customer Installation Metallic Interface, 1995.
Applicable Recommendations Standards.
References
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
T1/E1
PM4354 COMETPM4354 QUAD COMETQUAD
PM73123(4) AAL1gator8(4)
UTOPIA Any-PHY
Figure AAL1gator-4/8 Integrated Access Device (IAD) Application.
UTOPIA
Integrated Access Device (IAD) consolidates voice, data, Internet, video wide-area network services using Aover shared T1/E1 lines. IADs also unify functions many different types equipment including CSUs, DSUs multiplexers. Figure shows AAL1gator-4/8 connected PM4354 COMET-QUADs, PM7329 S/UNI-APEX-1K800 Traffic Manager, PM7328 S/UNI-ATLAS-1K800 ALayer device PM7347 S/UNIJET.
PM7329 S/UNI-APEX1K800 PM7347 S/UNI-JET
Ethernet
APassive Optical Networks (APON)
general architecture Passive Optical Network (PON) access network consists elements: Optical Line Termination (OLT) Optical Network Unit (ONU). connected through point-to-multipoint Passive Optical Network that consists fiber, splitters other passive components. Typically, ONUs connected single OLT, depending splitting factor. OLTs typically located local exchanges ONUs street locations, buildings even homes. Figure shows AAL1gator-4/8 application supporting functions.
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Video
AInterworking Function, AAL5
PM7328 S/UNI-ATLAS1K800
AMulti-service Switch
essential function Anetworks emulate existing Time Division Multiplexing (TDM) circuits. Since most voice data services currently provided circuits, seamless interworking between Ahas become system requirement. AForum standardized internetworking function that satisfies this requirement Circuit Emulation Service (CES) Specification. AAL1gator-4/8 direct implementation that service specification silicon, including complex Nx64 channelized service support CAS.
Application Examples
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Figure AAL1gator-4/8 APON Application
UTOPIA Any-PHY UTOPIA
Ethernet Video
AInterworking Function, AAL5
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PM7328 S/UNI-ATLAS1K800
Optical Module
T1/E1
PM4354 COMETPM4354 QUAD COMETQUAD
PM73123 AAL1gator-8
PM7329 S/UNI-APEX1K800
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
AAL1gator-4/8 contains AAL1 Processor block (A1SP) which work parallel. A1SP block interfaces common UTOPIA interface side Line Interface block other side which configured support several different line protocols. A1SP block connects interface. processor Interface block which also contains external clock control interface shared blocks. AAL1gator-4 serial lines.
SYSCLK NCLK TL_CLK_OE TL_CLK[7:0] RL_CLK[7:0] CRL_CLK CTL_CLK
TATM_DATA[15:0] TATM_PAR TATM_ENB TATM_SOC TATM_CLAV TATM_CLK RPHY_ADD[4:0] RATM_DATA[15:0] RATM_PAR RATM_ENB RATM_SOC RATM_CLAV RATM_CLK TPHY_ADD[4:0]
RSTB SCAN_ENB SCAN_MODEB
Clock
Line Interface
H-MVIP
Figure AAL1gator-4/8 Internal Block Diagram
TL_DATA[7:0] TL_SYNC[7:0] TL_SIG[7:0] RL_DATA[7:0] RL_SYNC[7:0] RL_SIG[7:0] LINE_MODE
A1SP
UTOPIA Interface
Direct
JTAG
Interface
Processor Interface
External Clock Interface
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CGC_DOUT[3:0] CGC_LINE[3:0] ADAP_STB SRTS_STB CGC_VALID CGC_SER_D
TRST
RAM_ADSCB RAM_A[16:0] RAM_D[15:0] RAM_PAR[1:0] RAM_WEB[1:0] RAM_CSB RAM_OEB
A[19:0] D[15:0] ACKB INTB
Block Diagram
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2000098 Issue
AAL1 Segmentation Reassembly (SAR) Processor (AAL1gator-4/8) monolithic single chip device that provides DS1, line interface access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. arbitrates access external SRAM storage configuration, user data, statistics. device provides microprocessor interface configuration, management, statistics gathering. PMC-Sierra also offers software device control package AAL1gator-4/8 device.
Description
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Bottom View AAL1gator-4
LINE_MO
RAM_D [15] RAM_D RAM_D [12]
RAM_O RAM_D SCAN_EN RAM_D [10] RAM_D [14] CTL_CLK RAM_D [11] RAM_D [13] RAM_D RAM_D RAM_D RAM_D RAM_D
RAM_D RAM_D RAM_D
RAM_WE RAM_PA RAM_AD RAM_AD [14] [10]
AAL1gator-4/8 manufactured pin, fine pitch, plastic ball grid array (PBGA) package. (23mm mm). Note that center pins thermal ground pins should connected Ground.
TCLK SCAN_M [12] [12]
SYSCLK
Diagram
TATM_DA [14]
RAM_AD RAM_AD RAM_AD
RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD [16] [12] RAM_PA RAM_AD [15] RAM_AD RAM_AD [11]
RAM_AD RAM_WE RAM_AD RAM_C RAM_AD RAM_AD [13]
TATM_DA RPHY_AD [15] D_RSX
CRL_C
TATM_PA TATM_DA TATM_DA [13] [11] TATM_DA TATM_DA [12] [10]
TATM_C TATM_DA TATM_DA
TL_C RL_CLK TL_C RL_CLK RL_SIG TL_SYNC RL_SIG TL_C RL_SIG RL_SYNC RESERVE D_IN TL_SIG RL_CLK RL_DATA
RPHY_AD RPHY_AD RPHY_AD
TATM_DA TATM_EN TATM_SO RPHY_AD TATM_C TATM_DA TATM_DA TATM_DA TATM_DA TATM_DA TATM_DA
TL_SYNC
TL_DATA RL_SYNC
TL_SIG
TATM_DA RATM_D
TL_CLK RL_DATA TL_SIG RL_C RL_C TL_CLK RL_SYNC TL_DATA TL_SIG RL_DATA
RATM_D RATM_EN RATM_D
RATM_D RATM_D RATM_D RATM_D RATM_D TPHY_AD RATM_C RATM_SO RATM_PA TPHY_AD RATM_CL TPHY_AD
RL_DATA TL_SYNC TL_DATA
TPHY_AD RATM_D
RATM_D RATM_D RATM_D [12] [11] TPHY_AD RATM_D [13] RATM_D [14] [17]
TL_DATA TL_SYNC RL_SYNC C_LIN TRSTB
RATM_D RATM_D [10] [15] INTB [10]
RL_SIG RSTB
[19]
RESERVE C_LIN _LIN
SRTS_STB ADAP_ST _LIN C_SE
TL_CLK_O C_DO
[13]
[15]
[18]
C_DO
[10]
[14]
[13]
[11]
[11]
[15]
[14]
[16]
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RL_C
TL_C RL_SIG RL_SYNC RL_DATA TL_DATA
TL_SYNC
RAM_D [15] RAM_D RAM_D [12]
RAM_D RAM_D RAM_D
TCLK SCAN_M [12] [12]
TATM_DA [14]
Bottom View AAL1gator-8
RAM_O RAM_D SCAN_EN RAM_D [10] RAM_D [14] CTL_CLK RAM_D [11] RAM_D [13] RAM_D RAM_D RAM_D RAM_D RAM_D
RAM_WE RAM_PA RAM_AD RAM_AD [14] [10]
RAM_AD RAM_AD RAM_AD
SYSCLK
TL_SYNC RL_SYNC RL_SIG RL_DATA TL_CLK TL_SIG RL_C
TL_DATA LINE_MO TL_SIG
RAM_AD RAM_WE RAM_AD RAM_C RAM_AD RAM_AD [13]
RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD [16] [12] RAM_PA RAM_AD [15] RAM_AD RAM_AD [11]
TATM_DA RPHY_AD [15] D_RSX
TL_DATA TL_SYNC RL_CLK TL_C RL_CLK TL_C RL_CLK RL_SIG TL_SYNC RL_SIG TL_C RL_SIG RL_SYNC RESERVE D_IN TL_SIG RL_CLK RL_DATA RL_SIG
RL_SYNC
TL_CLK
CRL_C
TATM_PA TATM_DA TATM_DA [13] [11] TATM_DA TATM_DA [12] [10]
TATM_C TATM_DA TATM_DA
TL_SYNC RL_DATA TL_SIG RL_SIG TL_DATA RL_SYNC
TL_SIG
RPHY_AD RPHY_AD RPHY_AD
TATM_DA TATM_EN TATM_SO RPHY_AD TATM_C TATM_DA TATM_DA TATM_DA TATM_DA TATM_DA TATM_DA
TL_CLK RL_DATA TL_SIG RL_C RL_C TL_CLK RL_SYNC TL_DATA TL_SIG RL_DATA
RL_SYNC
TL_DATA
TL_SYNC RL_DATA TL_SIG
TATM_DA RATM_D
RATM_D RATM_EN RATM_D
RATM_D RATM_D RATM_D RATM_D RATM_D TPHY_AD RATM_C RATM_SO RATM_PA TPHY_AD RATM_CL TPHY_AD
TL_DATA
RL_DATA TL_SYNC
TPHY_AD RATM_D
RATM_D RATM_D RATM_D [12] [11] TPHY_AD RATM_D [13] RATM_D [14] [17]
RL_SIG RSTB
TRSTB
RESERVE C_LIN _LIN
SRTS_STB ADAP_ST _LIN C_SE
TL_CLK_O
RL_SYNC C_LIN
INTB
TL_DATA TL_SYNC
RATM_D RATM_D [10] [15] [10]
[19]
[13]
[15]
[18]
C_DO
[10]
[14]
[13]
C_DO
[11]
[11]
[15]
[14]
[16]
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Name
Type
Function
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TATM_SOC/RPHY_SOC /RSOP
Output
ATM: Transmit UTOPIA ALayer Start-Of-Cell active high signal asserted AAL1gator-8 when TATM_D contains first valid byte cell. PHY: Receive Any-PHY/UTOPIA Layer Start-Of-Cell active high signal asserted AAL1gator-4/8 when RPHY_D[15:0] contains first valid word cell. AAL1gator-4/8 drives this signal only when Alayer selected cell transfer. Any-PHY: This Receive Start Packet (RSOP) signal which functions just like RPHY_SOC.
TATM_CLK/RPHY_CLK
Input
ATM: Transmit UTOPIA ALayer Clock synchronization clock input TAinterface. PHY: Receive UTOPIA/Any-PHY Layer Clock synchronization clock input RPHY interface Maximum frequency MHz.
Note signals have different meanings depending whether UTOPIA Amaster mode, mode Any-PHY mode. mode controlled UTOP_MODE ANY-PHY_EN fields UI_SRC_CFG UI_SNK_CFG registers. outputs tri-state when chip reset when UI_EN disabled UI_COMN_CFG register. outputs have maximum output current (IMAX)
UTOPIA Interface Signals (52)
Description
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
TATM_PAR/ RPHY_PAR
Output
TATM_ENB/RPHY_ENB /RENB
Bidi
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TATM_D[15]/RPHY_D[15] TATM_D[14]/RPHY_D[14] TATM_D[13]/RPHY_D[13] TATM_D[12]/RPHY_D[12] TATM_D[11]/RPHY_D[11] TATM_D[10]/RPHY_D[10] TATM_D[9]/RPHY_D[9] TATM_D[8]/RPHY_D[8] TATM_D[7]/RPHY_D[7] TATM_D[6]/RPHY_D[6] TATM_D[5]/RPHY_D[5] TATM_D[4]/RPHY_D[4] TATM_D[3]/RPHY_D[3] TATM_D[2]/RPHY_D[2] TATM_D[1]/RPHY_D[1] TATM_D[0]/RPHY_D[0]
Output
ATM: Transmit UTOPIA ALayer Data Bits form byte-wide data driven layer. Least Significant (LSB). Most Significant (MSB) first received cell from serial line. Note that only lower used Amaster mode. PHY: Receive UTOPIA/Any-PHY Layer Data Bits form word-wide data driven Alayer. This only driven when Alayer selected UI_SRC_INTF cell transfer. upper byte only used 16_BIT_MODE UI_SRC_CFG register. Otherwise upper byte driven 0's. LSB. first byte first received cell from serial line.
ATM: Transmit UTOPIA ALayer Parity byte parity covering TATM_D(7:0). PHY: Receive UTOPIA/Any-PHY Layer Parity either byte parity covering RPHY_D(7:0) word parity covering RPHY_D(15:0) depending value 16_BIT_MODE. ATM: Transmit UTOPIA ALayer Enable active signal asserted AAL1gator-4/8 during cycles when TATM_D contains valid data. asserted until AAL1gator-4/8 ready send full cell. PHY: Receive UTOPIA/Any-PHY Layer Enable active signal asserted Alayer indicate RPHY_D RPHY_SOC will sampled next cycle. UTOP_MODE UI_SRC_CFG UTOPIA Level Mode then AAL1gator-4/8 will drive data only RPHY_ADD matches CFG_ADDR UI_SRC_ADD_CFG register cycle before RPHY_ENB goes low. Any-PHY: This RENB input signal, which functions same RPHY_ENB. only difference that data driven cycles after selection instead just cycle.
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
TATM_CLAV/RPHY_CLAV /RPA
Bidi
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ATM: Transmit UTOPIA ALayer Cell Available active high signal from layer device indicate that there sufficient room accept cell. PHY: Receive UTOPIA/Any-PHY Layer Cell Available active high signal asserted AAL1gator-4/8 indicate ready deliver complete cell. Utopia Level mode, this signal driven only when MPHY_ADD matches CFG_ADDR UI_SRC_ADD_CFG register previous cycle. pulldown resistor recommended. Any-PHY: This Receive Packet Available (RPA) signal which functions same RPHY_CLAV except activated cycles after matching address instead one.
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
RATM_CLK/ TPHY_CLK
Input
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ATM: Receive UTOPIA ALayer Clock synchronization clock input synchronizing RAinterface. PHY: Transmit UTOPIA/Any-PHY Layer Clock synchronization clock input synchronizing TPHY interface. Maximum frequency MHz.
RPHY_ADD[4]/RSX RPHY_ADD[3]/RCSB RPHY_ADD[2] RPHY_ADD[1] RPHY_ADD[0]
Input Input Input Input
ATM: These signals used Amode. PHY: Receive UTOPIA Layer Address (Bits which selects UTOPIA receiver. These inputs used output enable RPHY_CLAV validate activation RPHY_ENB. There internal pull-up resistors. These pins compared with CFG_ADDR[5:0] UI_SRC_CFG_ADDR register. Note that these compared both UTOPIA Level UTOPIA Level modes. UTOPIA level expected that these pins will tied low. ANY-PHY: Receive Start Transfer(RSX) active high output which indicates start Any-PHY packet which identifies location prepended address. ANY-PHY_EN UI_SRC_CFG register needs this function. Receive Chip Select (RCSB) active input which used select AAL1gator-4/8 when polling Any-PHY mode. This input used decode Any-PHY address bits greater than RPHY_ADD[2]. This input goes cycle after AnyPHY address valid. ANY-PHY_EN CS_MODE_EN UI_SRC_CFG register needs this function. Otherwise this functions RPHY_ADD[3]. RPHY_ADD[2:0] bottom three bits Any-PHY address used select device when polling. These pins compared with CFG_ADDR[2:0] UI_SRC_CFG_ADDR register. Note these pins must tied ground when used.
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
RATM_SOC/ TPHY_SOC /TSOP
Input
This signal definitions depending whether UTOPIA Amode mode. ATM: Receive UTOPIA ALayer Start-Of-Cell active high signal asserted layer when RATM_D contains first valid byte cell. PHY: Transmit UTOPIA/Any-PHY Layer Start-Of-Cell active high signal asserted Alayer when TPHY_D contains first valid byte cell. Any-PHY: This Transmit Start Packet (TSOP) signal which functions just like TPHY_SOC. This signal optional this mode. unused, low. ATM: Receive UTOPIA ALayer Data Bits form byte-wide data from layer device. LSB. MSB. This first cell, which will transmitted serial line. upper byte used Amode. PHY: Transmit UTOPIA/Any-PHY Layer Data Bits form word-wide data from Alayer device. LSB. first byte. This first cell, which will transmitted serial line. upper byte only used 16_BIT_MODE UI_SNK_CFG register. ATM: Receive UTOPIA ALayer Parity byte parity covering RATM_D(7:0) word parity covering RATM_D(15:0) depending value 16_BIT_MODE. PHY: Transmit UTOPIA/Any-PHY Layer Parity either byte parity covering TPHY_D(7:0) word parity covering TPHY_D(15:0) depending value 16_BIT_MODE.
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RATM_PAR/ TPHY_PAR
RATM_D[15]/TPHY_D[15] RATM_D[14]/TPHY_D[14] RATM_D[13]/TPHY_D[13] RATM_D[12]/TPHY_D[12] RATM_D[11]/TPHY_D[11] RATM_D[10]/TPHY_D[10] RATM_D[9]/TPHY_D[9] RATM_D[8]/TPHY_D[8] RATM_D[7]/TPHY_D[7] RATM_D[6]/TPHY_D[6] RATM_D[5]/TPHY_D[5] RATM_D[4]/TPHY_D[4] RATM_D[3]/TPHY_D[3] RATM_D[2]/TPHY_D[2] RATM_D[1]/TPHY_D[1] RATM_D[0]/TPHY_D[0]
Input
Input
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
RATM_ENB/TPHY_ENB
Bidi
ATM: Receive UTOPIA ALayer Enable active signal asserted AAL1gator-4/8 indicate RATM_D RATM_SOC will sampled next cycle. will asserted until AAL1gator-4/8 ready receive full cell. PHY: Transmit UTOPIA/Any-PHY Layer Enable active signal asserted Alayer device during cycles when TPHY_D[15:0] contain valid data. AAL1gator-4/8 will accept data only TPHY_ADD matches CFG_ADDR UI_SNK_CFG register cycle before TPHY_ENB goes Any-PHY: This TENB input signal, which functions same TPHY_ENB. ATM: Receive UTOPIA ALayer Cell Available active high signal asserted layer indicate that there cell available send. PHY: Receive UTOPIA/Any-PHY Layer Cell Available active high signal asserted AAL1gator-4/8 indicate there cell-space available. AAL1gator4/8 drives this signal only when TPHY_ADD matches CFG_ADDR UI_SNK_CFG register previous cycle. pulldown resistor recommended. Any-PHY: This Transmit Packet Available (TPA) signal which functions same TPHY_CLAV except activated cycles after matching address instead one.
RATM_CLAV/TPHY_CLAV
Bidi
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Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
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TPHY_ADD[4]/TSX TPHY_ADD[3]/TCSB TPHY_ADD[2] TPHY_ADD[1] TPHY_ADD[0]
Input
ATM: These signals used Amode. PHY: Transmit UTOPIA Layer Address (Bits which selects UTOPIA transmitter. These inputs used output enable TPHY_CLAV validate activation TPHY_ENB. There internal pull-up resistors. These pins compared with CFG_ADDR[5:0] UI_SNK_CFG_ADDR register. Note that these compared both UTOPIA Level UTOPIA Level modes. UTOPIA level expected that these pins will tied low. ANY-PHY: Transmit Start Transfer(TSX) active high input which indicates start AnyPHY packet which identifies location prepended address. ANY-PHY_EN UI_SNK_CFG register needs this function. Transmit Chip Select (TCSB) active input which used select AAL1gator-4/8 when polling Any-PHY mode. This input used decode Any-PHY address bits greater than TPHY_ADD[2]. This input goes cycle after AnyPHY address valid. ANY-PHY_EN CS_MODE_EN UI_SNK_CFG register needs this function. Otherwise this functions TPHY_ADD[3]. TPHY_ADD[2:0] bottom three bits Any-PHY address used select device when polling. These pins compared with CFG_ADDR[2:0] UI_SNK_CFG_ADDR register. Note these pins must tied ground when used.
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Name
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
Type
AB11 AA10 AB10 AA12
Function
Input
Input
AB13
Input
AA13
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address latch enable signal (ALE) latches A[19:0] signals during address phase transaction. When high, address latches transparent. When low, address latches hold address provided A[19:0]. internal pull-up resistor. write strobe signal (WRB) qualifies write accesses AAL1gator-4/8 device. When low, D[15:0] contents clocked into addressed register rising edge WRB. Note that CSB, low, chip outputs tristated. Therefore should never active same time during functional operation.
address signals (A[19:0]) provide address allow AAL1gator-4/8 device interface external micro-processor.
bi-directional data signals (D[15:0]) provide data allow AAL1gator-4/8 device interface external micro-processor. Both read write transactions supported. microprocessor interface used configure monitor AAL1gator-4/8 device. Maximum output current (IMAX)
Microprocessor Interface Signals (42)
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Input
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INTB
OpenDrain Output
ACKB
OpenDrain Output
AA14
ACKB active signal which indicates when processor read data valid when processor write operation completed. When inactive this signal tristated. ACKB open drain output should pulled high externally with fast resistor. Maximum output current (IMAX) interrupt signal (INTB) active signal indicating that enabled MSTR_INTR_REG register set. When INTB low, interrupt active enabled. When INTB tristate, there interrupt pending disabled. INTB open drain output should pulled high externally with fast resistor. Maximum output current (IMAX)
Input
chip select signal (CSB) qualifies read/write accesses AAL1gator-4/8 device. signal must during read write accesses. When high, microprocessor interface signals ignored AAL1gator-4/8 device. required (register accesses controlled only RDB) then should connected inverted version RSTB signal. Note that CSB, low, chip outputs tristated.
read strobe signal (RDB) qualifies read accesses AAL1gator-4/8 device. When low, AAL1gator-4/8 device drives D[15:0] with contents addressed register falling edge RDB. Note that CSB, low, chip outputs tristated. Therefore should never active same time during functional operation.
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Name
RAM_D[15] RAM_D[14] RAM_D[13] RAM_D[12] RAM_D[11] RAM_D[10] RAM_D[9] RAM_D[8] RAM_D[7] RAM_D[6] RAM_D[5] RAM_D[4] RAM_D[3] RAM_D[2] RAM_D[1] RAM_D[0] RAM_A[16] RAM_A[15] RAM_A[14] RAM_A[13] RAM_A[12] RAM_A[11] RAM_A[10] RAM_A[9] RAM_A[8] RAM_A[7] RAM_A[6] RAM_A[5] RAM_A[4] RAM_A[3] RAM_A[2] RAM_A[1] RAM_A[0] RAM_OEB
Type
Function
Output
RAM_CSB
RAM_WEB[0]
RAM_WEB[1]
Output
Output
Output Output
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Output Enable active signal that enables SRAM drive data. Maximum output current (IMAX) Write Enable active signal high-byte write. Maximum output current (IMAX) Write Enable Zero active signal low-byte write. Maximum output current (IMAX) Chip Select active chip-select signal external memory. Maximum output current (IMAX)
address signals (RAM_A[16:0]) provide address allow AAL1gator-4/8 device address external 128Kx16(18) RAM. Maximum output current (IMAX)
bi-directional data signals (RAM_D[15:0]) provide data allow AAL1gator-4/8 device access external 128Kx16(18) RAM. Maximum output current (IMAX)
Interface Signals(40)
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
RAM_ADSCB/RAM_ R/WB
Output
NOTE: different modes line interface redefined. Direct mode there separate bi-directional lines which support lines Mbps each with aggregate bandwidth Mbps.Or line into highspeed mode support data rates Mbps. H-MVIP mode there one/two Mbps lines which compatible with H-MVIP specification. Table defines which signal tables need used each possible mode. Select mode line interface that will used refer tables listed. Table shows pins shared between different modes.
Table Line Interface Signal Table Selection
Name
LINE_MODE
Line Interface Signals(Direct)(67)
Type
Input
H-MVIP
Direct
Line Mode
Line Interface Table
Direct H-MVIP
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Function
Determines mode operation line interface: 0)Direct Mode 1)H-MVIP Mode
RAM_PAR[1] RAM_PAR[0]
Parity bi-directional signal that indicates parity upper lower byte RAM_D[15:0]. Maximum output current (IMAX)
This signal different meanings depending upon type SSRAM that AAL1gator-4/8 programmed interface Pipelined Single-Cycle Deselect SSRAM: Address Status Control active output external memory used cause external address loaded into RAM. Pipelined SSRAM: indicates direction transfer. Maximum output current (IMAX)
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
TL_SYNC[7] TL_SYNC[6] TL_SYNC[5] TL_SYNC[4] TL_SYNC[3] TL_SYNC[2] TL_SYNC[1] TL_SYNC[0]
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TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0]
Output
TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3] TL_DATA[2] TL_DATA[1] TL_DATA[0]
Output
Transmit Line Serial Data carry received data corresponding framer devices. Maximum output current (IMAX) TL_DATA[7:4] exist AAL1gator-4.
Transmit Line Signal signaling outputs corresponding framer devices SDF-MF mode. This default function this pin. Maximum output current (IMAX) TL_SIG[7:4] exist AAL1gator-4.
Transmit Line Synchronization transmit frame synchronization indicators used SDF-MF SDF-FR modes. Depending value MF_SYNC_MODE LI_CFG_REG register line, these signals either indicate frame boundary multi-frame boundary. Depending value GEN_SYNC LIN_STR_MODE register that line, sync signal either received from corresponding framer device generated internally Default mode this signal frame sync input. When MVIP_EN LS_Ln_CFG_REG then TL_SYNC[0] pin; common frame sync. Maximum output current (IMAX) TL_SYNC[7:4] exist AAL1gator-4.
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
TL_CLK[7]/TSM[7] TL_CLK[6]/TSM[6] TL_CLK[5]/TSM[5] TL_CLK[4]/TSM[4] TL_CLK[3]/TSM[3] TL_CLK[2]/TSM[2] TL_CLK[1]/TSM[1] TL_CLK[0]/TSM[0]
Transmit Line Channel Clock clock lines sixteen lines. They clock data from AAL1gator-4/8 corresponding framer devices. Depending value TL_CLK_OE CLK_SOURCE_TX field LIN_STR_MODE memory register, these pins either outputs inputs. TLCLK_OUTPUT_EN high, these pins outputs clock sourced internally power This later changed CLK_SOURCE_TX field. Note that CLK_SOURCE_TX "000" then this output, even driving clock. clock will only driven mode either internal clock synthesizer being used clock being looped. CLK_SOURCE_TX "001", "010, "011", "100", "101") Note that UDF_HS=1 HS_LIN_REG, TL_CLK[7:1] should tied high. Transmit Signaling Mirror copy TL_SIG output. Direct mode, CLK_SOURCE_TX="111" then signaling output this pin. This option used with devices that share same clock signaling. this mode CTL_CLK used line clock. CTL_CLK used, then TL_CLK[7:0] output pins drive valid clock signals should ignored. Maximum output current (IMAX) TL_CLK[7:5] exist AAL1gator-4. TL_CLK4 only used test clock AAL1gator-4 should left unconnected. There internal pullup this pin.
CTL_CLK
Input
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RL_SYNC[7] RL_SYNC[6] RL_SYNC[5] RL_SYNC[4] RL_SYNC[3] RL_SYNC[2] RL_SYNC[1] RL_SYNC[0]
Input
Common Transmit Line Clock transmit line clock which shared across lines. Whether this clock used given line dependent value CLK_SOURCE_TX LINE_STR_MODE memory register that line. Receive Line Synchronization receive frame synchronization indicators used SDF-MF SDF-FR modes. Depending value MF_SYNC_MODE LI_CFG_REG register line, these signals either indicate frame boundary multi-frame boundary. ground unused. RL_SYNC[7:4] exist AAL1gator-4.
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
RL_DATA[7] RL_DATA[6] RL_DATA[5] RL_DATA[4] RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0] RL_SIG[7] RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0] RL_CLK[7] RL_CLK[6] RL_CLK[5] RL_CLK[4] RL_CLK[3] RL_CLK[2] RL_CLK[1] RL_CLK[0] CRL_CLK
Input
AB22 AA22
Input
Line Interface Signals(H-MVIP)(12)
LINE_MODE
Name
Type
Input
Input
Function
Determines mode operation line interface: 0)Direct Mode 1)H-MVIP Mode Frame Sync active frame synchronization input signal used indicate start frame. Transmit Line Serial Data carry received data corresponding framer devices. H_MVIP backplane. AAL1gator-4 only line supported. Maximum output current (IMAX)
Input
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TL_DATA[1] TL_DATA[0]
Output
Input
Receive Line Clock clock received from corresponding framer device used clock RL_DATA, RL_SIG, RL_SYNC. RL_CLK[7:5] exist AAL1gator-4. RL_CLK4 only used test clock AAL1gator-4 should left unconnected. There internal pullup this pin.
Common Receive Line Clock receive line clock which shared across lines. Whether this clock used given line dependent value CLK_SOURCE_RX LIN_STR_MODE memory register that line. When MVIP_EN LS_Ln_CFG_REG then this input; common 4.096 clock.
Receive Line Signaling carries data from corresponding framer devices. Signaling sampled during last frame multi-frame insertion into AAL1 cells. change detection used, signaling must static entire multiframe signaling sampled multiple points during multi-frame. RL_SIG[7:4] exist AAL1gator-4.
Receive Line Serial Data carries receive data from corresponding framer devices. RL_DATA[7:4] exist AAL1gator-4.
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
TL_SIG[1] TL_SIG[0]
Output
Input
TL_SYNC[7] TL_SYNC[6] TL_SYNC[5] TL_SYNC[4] TL_SYNC[3]
Direct
H-MVIP
Line Interface Summary
following table shows modes same time shows pins redefined different modes.
8.5.1
Summary Line Interface Signals
AAL1gator-8
Clock clock used generating sampling F0B. This common clock used both receive transmit direction.
TL_SYNC[2] TL_SYNC[1] TL_SYNC[0]
TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3]
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RL_SIG[1] RL_SIG[0]
Input
Receive Line Signaling carries data from corresponding framer devices. H-MVIP does support signaling directly, these signals used transport signaling needed. Signaling needs valid entire AAL1gator-4 only line supported.
RL_DATA[1] RL_DATA[0]
Input
AB22
Receive Line Serial Data carries receive data from corresponding framer devices HMVIP backplane. AAL1gator-4 only line supported.
AAL1gator-4
C16B
Input
Clock clock used transfer data across H-MVIP bus. clock runs twice fast data rate. This common clock used both receive transmit direction.
Transmit Line Signal signaling outputs corresponding framer devices SDF-MF mode. H-MVIP does support signaling directly, these signals used transport signaling needed. AAL1gator-4 only line supported. Maximum output current (IMAX)
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Direct
TL_DATA[2] TL_DATA[1] TL_DATA[0] TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0] TL_CLK[7] TL_CLK[6] TL_CLK[5] TL_CLK[4] TL_CLK[3] TL_CLK[2] TL_CLK[1] TL_CLK[0] CTL_CLK RL_SYNC[7] RL_SYNC[6] RL_SYNC[5] RL_SYNC[4] RL_SYNC[3] RL_SYNC[2] RL_SYNC[1] RL_SYNC[0] RL_DATA[7] RL_DATA[6] RL_DATA[4] RL_DATA[5]
H-MVIP
TL_SIG[1] (AAL1gator-8 Only) TL_SIG[0]
C16B
RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0] RL_SIG[7]
RL_DATA[1] (AAL1gator-8 Only) RL_DATA[0]
AB22
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AB22
TL_DATA[0]
TL_DATA[1] (AAL1gator-8 Only)
AAL1gator-8
AAL1gator-4
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Direct
RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0] RL_CLK[7] RL_CLK[6] RL_CLK[5] RL_CLK[4] RL_CLK[3] RL_CLK[2] RL_CLK[1] RL_CLK[0] CRL_CLK
H-MVIP
RL_SIG[1] (AAL1gator-8 Only) RL_SIG[0] AA22
SRTS_STBH
CGC_LINE[3] CGC_LINE[2] CGC_LINE[1] CGC_LINE[0]
Output
CGC_DOUT[3] CGC_DOUT[2] CGC_DOUT[1] CGC_DOUT[0]
Output
AB16 AB14 AA15 AB19 AA18 AB18
Name
Type
Clock Generation Control Interface(14)
Function
External Clock Generation Control Data Bits form SRTS correction code when SRTS_STBH asserted; otherwise CGC_DOUT[3:0] bits form channel status frame difference when ADAP_STBH asserted. Line Bits form line CGC_DOUT corresponds when SRTS_STBH asserted; otherwise CGC_LINE[3:0] bits form adaptive state machine index when ADAP_STBH asserted. SRTS Strobe indicates that SRTS value present CGC_DOUT[3:0]. CGC_LINE[3:0] indicates line SRTS code controls. Adaptive Strobe indicates that channel status byte difference being played CGC_DOUT[3:0]. nibbles identified values CGC_LINE[3:0]. Network Clock Anetwork-derived clock used SRTS. this signal tied low, SRTS disabled. Internally this clock divided down lower frequency. resulting clock should 2.43 E1mode, 38.88 mode 77.76 mode.
Output
AA20
ADAP_STBH
Output
AA19
NCLK/ SRTS_DISB
Input
AA16
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AA22
AAL1gator-8
AAL1gator-4
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TL_CLK_OE
Input
CGC_SER_D
Input
AA17
CGC_VALID
Input
TCLK
Input
Name
Type
Input Internal Pull-up Output Input Internal Pull-up Input Internal Pull-up Schmitt Trigger Input Internal Pull-up
Input Internal Pull-up
SCAN_ENB
TRSTB
SCAN_MODEB
RESERVED_OUT RESERVED_IN
AB20
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JTAG/TEST Signals(7)
Function
test clock signal provides timing test operations carried using JTAG test access port. test mode select signal controls test operations that carried using JTAG test access port. Maintain tied high when using JTAG logic. test data input signal JTAG serial input data
test data output signal JTAG serial output data. active signal which, SCAN mode, used shift data. This signal should tied high normal operation. When tied enable SCAN mode. This signal should tied high normal operation. active test reset signal asynchronous reset JTAG circuitry. JTAG logic will used, option connect TRSTB RSTB input, keep tied high while RSTB high; this maintains JTAG logic reset during normal operation. JTAG logic will used, option described above, simply ground TRSTB. used, leave unconnected used, ground.
External Clock Generation Control Valid signal active high input indicating that data CGC_SER_D valid. This signal must transition from high first valid data CGC_SER_D must stay high through whole clock control word.
External Clock Generation Control Serial Data input used allow external clock control circuitry pass frequency information into internal clock synthesizer.
Transmit Line Clock Output Enable controls whether TL_CLK lines inputs outputs between time hardware reset when CLK_SOURCE_TX bits read. high, TL_CLK pins outputs. low, TL_CLK pins inputs. There internal pull-down resistor, TL_CLK pins inputs connected. value this input overwritten CLK_SOURCE_TX bits LIN_STR_MODE memory register.
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Name
RSTB
Type
Schmitt Trigger Input Internal Pull-up Input
AA21
Function
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VDD2.5 (PCH)
Power
AA11
Power (VDD2.5). VDD2.5 pins should connected well decoupled +2.5V power supply. These pins power core device.
VDD3.3 (PPH, PQH)
Power
AB17
Power (VDD3.3). VDD3.3 pins should connected well decoupled +3.3V power supply. These pins power output ports device. pins "quiet" power pads.
SYS_CLK
System Clock. maximum frequency MHz. This clock used clock majority logic inside chip also determines speed memory interface external clock control interface. This clock also used clock synthesis. When clock synthesis enabled this clock must 38.88 MHz.
Reset active asynchronous hardware reset. When RSTB forced low, AAL1gator's internal registers reset their default states.
General Signals(3+power/gnd)
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
(PPL, PQL, PCL)
Ground
Connects
AAL1gator-4/8 inputs bi-directionals present minimum capacitive loading tolerant.
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AAL1gator-4/8 UTOPIA/Any-PHY outputs bi-directional pins have drive capability. drive capability. other outputs bi-directional pins have drive capability. AAL1gator-4/8 outputs tristated under control IEEE P1149.1 test access port, even those which tristate under normal operation. outputs bi-directionals tolerant when tristated. clock inputs (except TL_CLK) Schmitt triggered. Inputs RPHY_ADD[4]/RSX, RL_DATA[7:0], RPHY_ADDR[3:0], TPHY_ADDR[4:0], RL_CLK[7:0], RL_SYNC[3:1], TL_CLK[7:0], RATM_DATA[15:0], RATM_PAR, RATM_CLK, RATM_SOC, TATM_CLK, D[15:0], RAM_PAR[1:0], WRB, CSB, RDB, NCLK, CRL_CLK, CTL_CLK, SCAN_ENB, SCAN_MODEB, CGC_SER_D, CGC_VALID, RSTB, ALE, TL_CLK_OE, TMS, TCLK, TRSTB have internal pull-up resistors. Power VDD3.3 pins should applied before power VDD2.5 pins applied. Similarly, power VDD2.5 pins should removed before power VDD3.3 pins removed.
Notes Description:
Unconnect
Thermal Grounds
Ground
J9-J14 K9K14 L9-L14 M9-M14 N9N14 P9-P14
AB12 AB15 AB21
Thermal grounds heat dissapation. Connect ground plane.
These unbonded pins. connect.
Ground (VSS). pins should connected GND. pins ground pins ports. pins "quiet" ground pins ports. pins core ground pins. grounds should connected together.
Name
Type
Function
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
JTAG
following UTOPIA modes supported.
Any-PHY
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sink direction, uses 8-cell deep FIFO buffering cells they wait sent A1SP block. addition, A1SP contains 8-cell deep FIFO. source direction, uses 4-cell deep FIFOs holding cells before they sent onto UTOPIA bus. Also, A1SP contains 8-cell deep FIFO. data flow showing FIFOs shown Figure
UTOPIA Level
UTOPIA Level
UTOPIA Level Master (8-bit only)
manages responds control signals UTOPIA passes cells from UTOPIA A1SP block. Both 8-bit 16-bit UTOPIA interfaces with optional single parity supported. Each direction configured independently address configuration register.
UTOPIA Interface Block (UI)
Line Interface Block (LINEI)
Interface Block (RAMI)
Processor Interface Block (PROCI)
AAL1 Processing Block (A1SP)
UTOPIA Interface Block (UTOPIAI)
AAL1gator-4/8 divided into following major blocks, which explained this section:
Functional Description
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Figure Data Flow Buffering A1SP Block
A1SP
TUFIFO cells)
Cell FIFO
Cell FIFO
RUFIFO cells)
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block consists functions: Data Source Interface (SRC_INTF), Data Sink Interface(SNK_INTF), 8-cell FIFO (FF8CELL), 4-cell FIFO (FF4CELL), 3-cell FIFO (FF3CELL), UMUX, UI_REG. Figure block diagram AAL1_UI block.
UI_EN UI_COMN_CFG register enables both source side sink side UTOPIA interface. This resets disabled state that chip resets with UTOPIA outputs tristated. Once modes have been configured interface enabled, then outputs will drive their correct values.
UTOPIA UTOPIA loopback, there 3-cell FIFO Block. Line-side Lineside loopback done A1SP Block.
UTOPIA Level mode, AAL1gator-4/8 responds UTOPIA single port device.
RXA1SP cell FIFO)
TXA1SP cell FIFO)
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Figure Block Diagram
SRC_INTF FF4CELL
UMUX
Signals to/from A1SP block Signals to/from A1SP block
UTOPIA Interface (UI) Block
FF3CELL
SNK_INTF
RXUTOPIA SIGNALS
UTOPIA Interface FIFO Input Logic
FF8CELL
TXUTOPIA SIGNALS
UTOPIA Interface FIFO Output Logic
DEMUX
UI_REG
UTOPIA Source Interface (SRC_INTF) SRC_INTF block (shown Figure conveys cells received from UMUX block UTOPIA interface. Depending value UTOP_MODE field UI_SRC_CFG register, UTOPIA interface will either UTOPIA master (controls write enable signal) UTOPIA device (controls cell available signal). device, SRC_INTF either UTOPIA Level device, where only device UTOPIA bus, UTOPIA Level device where other devices coexist UTOPIA bus. master device, SRC_INTF only function UTOPIA Level device. 16_BIT_MODE UI_SRC_CFG register then bits UTOPIA data used. 16_BIT_MODE must UTOPIA master mode.
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9.1.1
DEMUX FIFO Output Logic
Prioritization FIFO Input Logic
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AAL1gator-4/8 tolerate temporary de-assertions TATM_CLAV/RPHY_ENB), assumed that enough UTOPIA bandwidth present accept cells that AAL1gator4/8 produce timely manner. Once 4-Cell FIFO fills cells will begin filling 8-cell FIFO A1SP block. Anytime UTOPIA FIFO fills T_UTOP_FULL interrupt will active MSTR_INTR_REG enabled. This FIFO fill during normal operation usually indication error. However, A1SP FIFO should normally fill. does fill indicates there some congestion, which impacting UTOPIA interface TALP_FIFO_FULL will active A1SP_INTR_REG. When TALP FIFO fills, then TALP longer able build cells data will start building transmit buffer frame_advance_fifo will fill. this continues that FR_ADV_FIFO_FULL goes active then data been lost transmit queues need reset. T_UTOP_FULL indicator used determine when UTOPIA Interface clears. also desirable disable UI_EN that stored cells flushed.
Parity driven TATM_PAR(RPHY_PAR) whenever TATM_D(RPHY_D[15:0]) driven. EVEN_PAR will determine whether even parity parity generated. Since parity required AForum, EVEN_PAR intended used error checking only.
RPHY_ADD[4:0] input used only UTOPIA mode. cycle following where RPHY_ADD[4:0] matches CFG_ADDR(4:0) UI_SRC_ADD_CFG register, Block will drive RPHY_CLAV. Otherwise RPHY_CLAV tri-stated. addition, during previous cycle RPHY_ENB high current cycle, then device selected SRC_INTF begins transmitting cell next cycle. Note that UTOPIA Level there polling, RPHY_ADD[4:0] must tied low.
UTOPIA Level mode, RPHY_CLAV activated whenever complete cell available sent. remains active until last byte been read last available complete cell. cell sent cycle after RPHY_ENB goes low. RPHY_ENB goes high during cell transfer, data sent each cycle following where RPHY_ENB high.
mode, SRC_INTF block sources RPHY_D[15:0], RPHY_PAR, RPHY_SOC, RPHY_CLAV, while receiving RPHY_ENB. indication generated coincident with first word (8-bit 16-bit) each cell that transmitted RPHY_D[15:0]. mode, RPHY_D[15:0], RPHY_PAR, RATM_SOC signals driven only when valid data being sent; otherwise they tristated.
master mode, SRC_INTF block sources TATM_D, TATM_PAR, TATM_SOC, TATM_ENB while receiving TATM_CLAV. Start-Of-Cell (SOC) indication generated coincident with first word (only 8-bit mode supported) each cell that transmitted TATM_D. TATM_D, TATM_PAR TATM_SOC driven times. TATM_ENB signal indicates which clock cycles contain valid data UTOPIA bus. device will assert TATM_ENB signal until full cell send target device activated TATM_CLAV. TATM_CLAV signal indicates whether target device able accept cells not. Only cell level handshaking supported. target device unable accept additional cells must deactivate TATM_CLAV later than byte current cell. additional cells will sent until TATM_CLAV activated.
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Any-PHY Mode
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Table shows CFG_ADDR field used different modes.
Because large number possible ports, source direction, device addresses used polling device selection, instead port addresses. (Each device control many ports) When device selected send cell, device prepends port address front cell. Since, this direction AAL1gator-4/8 only single port, device address port address same. However, AAL1gator-4/8 only limited number address pins. accommodate systems, which using different port density AnyPHY devices, RCSB signal available handle additional external decoding that required. Any-PHY mode, devices respond with RPHY_CLAV cycles after their address instead cycle required UTOPIA mode. However, timing RCSB matches UTOPIA timing that full cycle external decoding available.
During cycle that prepend address active bus, pulses high.
Any-PHY mode in-band addressing used allow more than possible addresses available UTOPIA mode. extra word prepended front each cell that transmitted. prepended word indicates port address sending cell. SRC_INTF uses CFG_ADDR(15:0) UI_SRC_ADD_CFG register address prepend. 16_BIT_MODE then only lower bits used.
ANY-PHY_EN UI_SRC_CFG register then SRC_INTF operates single port Any-PHY slave device. Any-PHY mode RPHY_ADDR(4) becomes depending value CS_MODE_EN, RPHY_ADDR(3) become RCSB signal instead.
SRC_INTF circuit controls when cell transmitted from internal cell FIFO. Since UTOPIA transmit cells higher speeds than TALP, since expected applications shared UTOPIA environment, cell transmission from SRC_INTF commences only when there full cell worth data available transmit. cell then transmitted interface UTOPIA TATM_CLK rate, accordance with TATM_FULLB/RPHY_ENB) input. maximum supported clock rate MHz.
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Table CFG_ADDR PHY_ADDR Usage direction Polling MODE UTOPIA-2 Single-Addr Any-PHY with Any-PHY without
Notes:
Selection CFG_ADDR
[4:0]=device [2:0]=device
[4:0]=device [2:0]=device
[4:0]=device [2:0]=device
PHY_ADDR Pins
PHY_ADDR Pins
Any-PHY mode, CS_MODE_EN='1' then must program CFG_ADDR[4:3] "00". Any-PHY mode, CS_MODE_EN='0' then must program CFG_ADDR[4]="0".
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master mode, SNK_INTF block receives RATM_D, RATM_PAR, RATM_SOC, RATM_CLAV while driving RATM_ENB. Once enabled this mode, and, RATM_CLAV input signal asserted, SNK_INTF block waits RATM_SOC signal from layer. Once RATM_SOC signal arrives, cell accepted soon possible. Start-Of-Cell (SOC) indication received coincident with first word (only 8bit mode supported) each cell that received RATM_D. cell FIFO allows interface accept data maximum rate. FIFO fills, RATM_ENB signal will asserted again until device ready accept entire cell. RATM_ENB signal depends only cell space independent state RATM_CLAV signal. RATM_CLAV signal indicates whether target device cell send not. Only cell level handshaking supported. mode, SNK_INTF block receives TPHY_D[15:0], TPHY_SOC, TPHY_ENB while driving TPHY_CLAV. cell available (TPHY_CLAV) signal indicates when device ready receive complete cell. UTOPIA Level mode, TPHY_CLAV always driven.
16_BIT_MODE UI_SNK_CFG register then bits UTOPIA data used. 16_BIT_MODE must UTOPIA master mode.
SNK_INTF block receives cells from UTOPIA interface sends them UMUX interface. Depending value UTOP_MODE field UI_SNK_CFG register, UTOPIA interface acts either UTOPIA master (controls read enable signal) UTOPIA device (controls cell available signal). device SNK_INTF either UTOPIA Level device, where only device UTOPIA bus, UTOPIA Level device where other devices coexist UTOPIA bus. master device SNK_INTF only function UTOPIA Level device.
9.1.2
UTOPIA Sink Interface (SNK_INTF)
Any-PHY mode, direction AAL1gator-4/8 will prepend cell with CFG_ADDR[15:0]. 8-bit mode cell will prepended with CFG_ADDR[7:0]
CFG_ADDR prepended
[3:0]=device
[3:0]=device
[3:0]=device
CFG_ADDR prepended
CFG_AD
[4:0]=devi [2:0]=devi [3:0]=devi
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sink direction, port addresses used polling device selection, instead device addresses. However AAL1gator-4/8 only limited number address pins. accommodate systems, which using different port density Any-PHY devices, TCSB signal available handle additional external decoding that required. AnyPHY mode, devices respond with TPHY_CLAV cycles after their address instead cycle required UTOPIA mode. However timing TCSB matches UTOPIA timing that full cycle external decoding available. Table shows CFG_ADDR field used different modes.
During cycle that prepend address active bus, input pulses high.
Any-PHY mode in-band addressing used allow more than possible addresses available UTOPIA mode. extra word prepended front each cell that transmitted. prepended word indicates port address receive cell. SNK_INTF uses CFG_ADDR(15:2) UI_SNK_ADD_CFG register match with address prepend. 16_BIT_MODE then CFG_ADDR(7:2) used. both cases, polling should only done with PHY_ADDR[1:0] equal "00".
ANY-PHY_EN UI_SNK_CFG register then SNK_INTF operates multi port Any-PHY slave device. Any-PHY mode TPHY_ADDR[4] becomes depending value CS_MODE_EN, TPHY_ADDR(3) become TCSB signal instead.
Any-PHY Mode
Parity always checked parity error will cause interrupt UTOP_PAR_ERR_EN MSTR_INTR_EN_REG. FORCE_EVEN_PARITY will determine whether even parity parity checked. Since parity required AForum, FORCE_EVEN_PARITY intended used error checking only. error detected UTOP_PAR_ERR MSTR_INTR_REG set, corresponding enable MSTR_INTR_EN_REG then INTB will active. cell received with parity will still processed normal.
SNK_INTF block waits SOC. When signal arrives, counter started, bytes received. occurs within cell, counter reinitializes. This means that corrupted cell will dropped second good cell will received. SNK_INTF block stores cell receive FIFO. receive FIFO becomes full, stops receiving cells. bytes written FIFO with RATM_CLK. RATM_CLK input AAL1gator-4/8. maximum supported clock rate MHz.
UTOPIA Level mode, SNK_INTF responds single address device. TPHY_CLAV driven cycle following ones which TPHY_ADDR(4:0) matches CFG_ADDR(4:0) UI_SNK_ADD_CFG register. Otherwise TPHY_CLAV tri-stated. addition address match, during previous cycle TPHY_ENB high current cycle, then device selected SRC_INTF begins accepting cell that being received. Note that UTOPIA Level there polling, TPHY_ADD[4:0] must tied low.
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Table CFG_ADDR PHY_ADDR Usage direction Polling MODE UTOPIA-2 Single-Addr Any-PHY with PHY_ADDR Pins
[4:0]=device [2]=device [1:0]="00"
Selection CFG_ADDR
[4:0]=device [2]=device
[4:0]=device
PHY_ADDR Pins
[15:2]=device [1:0]="00"
Notes:
9.1.3
UTOPIA Block (UMUX)
UMUX also supports forms UTOPIA UTOPIA loopback; global loopback, where cells looped, based loopback, where only specific used loopback cells. global loopback cells received UTOPIA block sent back onto UTOPIA bus. Global loopback enabled setting U2U_LOOP UI_COMN_CFG register. based loopback mode, cell received with that matches loopback sent back onto UTOPIA bus. based loopback enabled setting VCI_U2U_LOOP UI_COMN_CFG register. loopback programmable writing U2U_LOOP_VCI register. 3-cell FIFO used loopback.
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sink direction, UMUX waits until SNK_INTF FIFO cell send. Once SNK_INTF FIFO cell send, UMUX polls A1SP associated with cell availability. Once A1SP room cell, UMUX reads cell SNK_INTF FIFO places A1SP FIFO.
SRC_INTF FIFO room cell, UMUX polls A1SP block Loopback FIFO determine cell. cell read from selected A1SP block Loopback FIFO transferred into SRC_INTF FIFO. highest priority source does have cell, other source examined. A1SP block 8-cell FIFO. Loopback FIFO cells.
source direction, UMUX polls A1SP block Loopback FIFO using least recently serviced algorithm determine cell availability. this algorithm, once particular source serviced, lowest priority sources.
UMUX serves bridge between A1SP block SNK_INTF SRC_INTF blocks.
Any-PHY mode upper bits prepended address compared with CFG_ADDR[15:2]. bottom bits must "00". 8-bit mode CFG_ADDR[7:2] used instead.
Any-PHY mode, CS_MODE_EN='1' then must program CFG_ADDR[4:3] "00". Else CS_MODE_EN='0' then must program CFG_ADDR[4]="0".
Any-PHY without
[3:2]=device [1:0]="00"
[3:2]=device
[15:2]=device [1:0]="00" PHY_ADDR used. Addr prepended.
PHY_ADDR used. Addr prepended.
CFG_AD
[4:0]=devi [15:2]=dev [15:2]=dev
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Transmit Frame Transfer Controller (TFTC) block Cell Service Decision (CSD) block Transmit Adaptation Layer Processor (TALP) block TALP FIFO (TFIFO) block Local Loopback Block (LOC_LPBK) block Receive Frame Transfer Controller (RFTC) block Receive Adaptation Layer Processor (RALP) block RALP FIFO (RFIFO) block
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Figure shows block diagram AAL1gator-4/8 sequence events used segment reassemble data.
A1SP block main AAL1 processing block. block processes E1/T1 lines. remainder this section refers AAL1gator-8 A1SP block with links, cases AAL1gator-4 there lines A1SP block. This block following major components.
AAL1 Processing Block (A1SP)
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Figure A1SP Block Diagram
Input from Block
Transmit Frame Transfer Controller (TFTC)
Transmit Adaptation Layer Processor (TALP)
TALP FIFO Block (TFIFO)
Cell Service Decision (CSD)
Output Block
External Memory
Local Loopback Block (LOC_LPBK)
Internal
TALP generates cell from data signaling buffers writes cell into TALP FIFO.
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TFIFO block buffers cells which will transmitted UTOPIA Interface block. local loopback enabled cell looped RALP. RFIFO block buffers cells received from UTOPIA Interface block.
commands TALP generate cell from available data each ready queues identified step
checks frame-based table queues having sufficient data generate cell. each queue with enough data generate cell, schedules next cell generation occurrence table.
When TFTC finishes writing complete frame into memory, notifies frame completion writing line frame number into FIFO.
TFTC stores line data into memory bits time.
Microprocessor Control
Output Block
Receive Frame Transfer Controller (RFTC)
Receive Adaptation Layer Processor (RALP)
RALP FIFO Block (RFIFO)
Input from Block
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
RALP performs pointer searches, checks overrun underrun conditions, detects mismatches, checks cells, extracts line data from cells, places data into receive buffer.
Note lines using change detection mode, must static entire multiframe structure AAL1gator will sample other points within multiframe. special case mode exists that permits signaling with framing. Normally multiframe consists frames timeslots, where signaling changes multiframe boundaries. When E1_WITH_T1_SIG LIN_STR_MODE line mode, TFTC will multiframe consisting frames timeslots. this mode, AAL1gator-4/8 reads signaling 24th frame multiframe.
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TFTC monitors frame sync signals will realign when edge seen these signals that does correspond where expects occur. necessary provide edge beginning every frame multiframe. AAL1gator-4/8 reads signaling during last frame every multiframe. mode, AAL1gator-4/8 reads signaling 24th frame multiframe. mode, AAL1gator-4/8 reads signaling 16th frame multiframe.
TFTC accepts deframed data from Line Interface Block. structured data, TFTC uses synchronization supplied Line Interface Block perform serial-to-parallel conversion incoming data then places this data into multiframe buffer order which arrives.
Transmit Frame Transfer Controller (TFTC)
9.2.1
AAL1 Transmit Side (TxA1SP)
SDF-MF (Structured Data Format- Multi-Frame). Channelized data with signaling. (Multi-Frame based structure).
SDF-FR (Structured Data Format- Frame). Channelized data without signaling. (Frame based structure).
UDF-HS (Unstructured Data Format- High Speed). Unstructured stream line speeds under Mbps. (Only line supported A1SP).
UDF-ML (Unstructured Data Format- Multi-Line). Unstructured stream line speeds Mbps. (supports lines A1SP) under Mbps).
Four types data supported A1SP.
RFTC plays receiver buffer data onto lines.
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Figure Capture Signaling Bits (SHIFT_CAS=0)
ABCD RL_SIG XXXX ABCD XXXX Channel XXXX ABCD Channel
Channel
XXXX indicates signaling ignored
Channel
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Unstructured data received without regard byte alignment data within frame placed frame buffer order which arrives. Figure shows basic components TFTC.
AAL1gator-4/8 treats timeslots identically. Although data streams contain timeslots channel data timeslots control (timeslots 16), data signaling timeslots stored memory sent received cells.
Note:
XXXX indicates signaling ignored
ABCD RL_SIG XXXX ABCD XXXX Channel XXXX ABCD Channel
(timeslots)
RL_SER
Line Signals During Last Frame Mult iframe
Figure Capture Signaling Bits (SHIFT_CAS=0)
ABCD ABCD ABCD XXXX Channel XXXX Channel XXXX Channel
RL_SER (timeslots)
Line Signals During Last Frame Multiframe
AAL1gator-4/8 reads signaling nibble each channel when reads last nibble each channel's data unless SHIFT_CAS LIN_STR_MODE register set. SHIFT_CAS then AAL1gator-4/8 reads signaling nibble each channel when reads first nibble each channel's data. Figure example frame. Figure example frame.
ABCD ABCD ABCD XXXX Channel XXXX Channel XXXX Channel
AAL1GATOR-4/8 Telecom Standard Product Data Sheet Release
Figure Transmit Frame Transfer Controller
Line Line Line
ATTN0
Interface
Line Line
Line Receive Line Interface
ATTN7 DATA7
Line-to-Memory Interface
Channel Pair
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Figure shows format transmit data buffer ESF-formatted data lines that SDF-MF mode.
TFTC accommodates Super Frame (SF) mode treating like Extended Super Frame (ESF) format. TFTC ignores every other frame pulse captures signaling data only last frame multiframes. formatting data signaling buffers highly dependent operating mode. Refer section 7.6.6 "RESERVED (Transmit Signaling Buffer)" page more information transmit signaling buffer.
channel clock also informs line-to-memory interface that data bytes available from line. When bytes available, line attention signal sent line encoder block. However, because channel clock asynchronous input line-to-memory interface, passed through synchronizer before supplied line encoder. Since there eight potential lines each them provides channel clock, they synchronized before being submitted line encoder.
receive line interface primarily serial-to-parallel converter. Serial data, which derived from RL_DATA signal from Block, supplied shift register. shift register clock RL_CLK input from external framer. When data been properly shifted transferred 2-byte holding register internally derived channel clock. This clock derived from line clock framing information.
Interface
Data
Receive Line Interface
Line Encoder
DATA0
Line Number
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Figure SDF-MF Format T_DATA_BUFFER
DS0s
Figure SF-SDF-MF Format T_DATA_BUFFER
Frame Buffer Number
Figure shows format transmit data buffer SF-formatted data lines that SDF-MF mode.
DS0s
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Figure shows format transmit data buffer data lines that SDFFR mode.
Frame Buffer umber
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Figure SDF-FR Format T_DATA_BUFFER
Frame Buffer Number DS0s
Frame
Frame Frame
Frame
Frame Frame
Frame Frame Frame
Frame Buffer Number
Figure SDF-MF Format T_DATA_BUFFER
DS0s
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Figure shows format transmit data buffer data lines that SDFMF mode.
Frame
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Figure SDF-MF with Signaling Format T_DATA_BUFFER
DS0s
Frame Buffer Number
Figure SDF-FR Format T_DATA_BUFFER
Frame Buffer Number
Figure shows format transmit data buffer data lines that SDFFR mode.
DS0s Frame Frame Frame Frame
Figure shows format transmit data buffer lines that UDF-ML mode.
Proprietary Confidential PMC-Sierra, Inc., customers' internal use. Document No.: PMC-2000098 Issue
Figure shows format transmit data buffer data using signaling, lines that SDF-MF mode
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Figure Unstructured Format T_DATA_BUFFER
Data Bits 256-Bit Internal Frame 256-Bit Internal Frame
Figure SDF-MF Format T_SIGNALING_BUFFER
Channel ABCD Channel ABCD
Byte Address
Channel ABCD Channel Used
Figure Figure Figure Figure show contents transmit signaling buffer different signaling modes. cases upper nibble each byte "0000".
256-Bit Internal Frame
Channel Used
Multiframe
Figure SDF-MF Format T_SIGNALING BUFFER
Channel ABCD
Byte Address
Channel ABAB
Channel ABAB
Channel ABAB
Channel ABAB
Channel Used
Multiframe/2
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Channel Used
rame Buffer Number
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Figure SDF-MF Format T_SIGNALING_BUFFER
Byte Address Multiframe
Channel ABCD Channel ABCD
Figure SDF-MF with Signaling Format T_SIGNALING_BUFFER
Channel ABCD
Channel ABCD
Multiframe
Byte Address
Channel ABCD
Transmit Conditioning
having independent control over whether signaling data conditioned, possible substitute signaling which carried bits across Anetwork while still passing data received line. This useful applications that receiving signaling with data. HS_UDF mode HS_TX_COND needs HS_LIN_REG register. When this cells with ones pattern will generated. CMD_REG_ATTN needs written after HS_TX_COND this function take affect.
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T_COND_DATA structure allows conditional data defined per-DS0 basis T_COND_SIG structure allows conditioned signaling defined per-DS0 basis. TX_COND T_QUEUE_TBL allows cell building logic (described Section Transmit Adaptation Layer Processor (TALP) page directed build cells from conditioned data signaling. control whether conditioned data, conditioned signaling, both used, TX_COND_MODE TX_CONFIG register appropriate value. TX_COND TX_COND_MODE bits per-queue basis.
Channel ABCD
Channel ABCD
Channel ABCD
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Transmit Signaling Freezing
SRTS Transmit Side
Figure Transmit Side SRTS Function
Serve Clock Freq SRTS Code Bits
transmit side supports SRTS only unstructured data formats per-line basis. SRTS support requires input reference clock, NCLK. input reference frequency defined 155.52/2n MHz, where chosen such that reference clock frequency greater than frequency being transmitted, less than twice frequency being transmitted RL_CLK NCLK RL_CLK). implementation, input reference clock frequency must 2.43 MHz. transmit side accept reference clock speed 77.76 MHz, which required applications. Figure page shows process implemented each line enabled SRTS, regardless reference frequency. resulting 4-bit SRTS code then inserted into each numbered cells that line. There four cells each cell sequence, each carries different SRTS bit. line does supply SRTS, then bits 3008 divider number data bits eight cells 47). divider aligned first cell generation after reset resynchronization cell generation process.
Divide 3008
Signaling freezing required function when transporting CAS. This function holds signaling unchanged when incoming line fails. PMC-Sierra framers provide this function. framer used that does support signaling freezing, this function must provided externally.
Most signals ones pattern, cells with this pattern generated setting T_COND_DATA "FF"x T_COND_SIG "F"x. mode this done setting HS_TX_COND `1'. However signal framed "1010" pattern. This signal generated setting HS_GEN_DS3_AIS HS_LIN_REG register. CMD_REG_ATTN needs written after HS_GEN_DS3_AIS HS_TX_COND this function take affect.
Reset
Bits fere Freq (For 2.43 MHz. MHz.)
Cell eneration
Resync
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4-Bit Latch
4-Bit Counter
Under certain alarm conditions such Loss Signal (LOS), Alarm Indication Signal (AIS) needs transmitted downstream. This means that cells need generated which carry pattern. AAL1gator-4/8 does alarm processing dependent external framer this functionality. framer would notify processor alarm conditions then processor would switch particular queue from normal mode conditioned mode setting TX_COND T_QUEUE_TBL.
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Change Detection change detection enabled word written Interrupt FIFO every time value nibble changes then remains stable additional multiframe. CASCHG_FIFO_EMPB long this FIFO contains unread entries, which will result maskable interrupt. structure word contained FIFO shown Figure first eight bits indicate channel, which encountered change value CAS. next four bits indicate value final four bits indicate value. refers incoming interface (RL_SIG), refers incoming Acells UTOPIA Cell Sink interface. values de-bounced internally time, additional debounce must done external chip.
Line
Channel
Figure Change Interrupt Word
Figure Change Configuration Register Structure
processor will also able mask portions therefore receive interrupts only when particular bits change. Figure shows structure AUTO_CONFIG_n field Change Configuration Table.
MASK
Reserved
Reserved
MASK
Cell Service Decision (CSD) Circuit circuit determines which cells sent when. determines this implementing Transmit Calendar tables. When TALP builds cell, circuit performs complex calculation using credits determine frame which next cell from that queue should sent. circuit schedules cell only when cell built TALP. SUPPRESS_TRANSMISSION TX_CONFIG word set, then cell scheduled, however, cell transmitted.
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Once TFTC writes complete frame into external memory, writes line number frame number this frame into FR_ADVANCE_FIFO. circuit reads lineframe number pair from FR_ADVANCE_FIFO uses index into Transmit Calendar. Transmit Calendar composed eight-bit tables, line. Each table consists entries, frame buffer. Each entry consists bits, queue. each indexed entry Transmit Calendar, will schedule frame which next cell built corresponding queue, notify TALP that enough data available build cell that queue. circuit processes queues from Transmit Calendar entry starting with lowest queue number proceeding highest. processing steps follows: circuit obtains QUE_CREDITS, subtracts average number credits cell from average number credits, AVG_SUB_VALU, number credits that will spent sending current cell. structured lines, average number credits cell 7/8. unstructured lines, average number credits cell Next, circuit computes frame location next service subtracting remaining credits from divides result number channels, NUM_CHAN, dedicated that queue. number channels calculated based upon channels allocated queue. NUM_CHAN equal number channels allocated queue. then adds this frame differential present frame location determine frame number next frame which TALP build cell. circuit then sets corresponding entry Transmit Calendar writes QUEUE_CREDITS. circuit then adds credits back credit total frame increment number. number credits equal frame differential computed earlier, multiplied number channels that queue. Once queue identified requiring service, identity written NEXT_SERV location.
Figure shows assigns credits determine which frames cells should sent.
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After servicing queues that frame, circuit advances next active line located line queue. there active lines, circuit returns idle state wait next line request service.
circuit obtains next queue that frame repeats steps through circuit continues this process until there more active queues that frame.
following steps well Figure page describe circuit schedules cells TALP build.
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Figure Frame Advance FIFO Operation
Frame Boundaries
FR_ADVANCE_FIFO
TFTC RL_DATA(0 RL_FSYNC(0) TFTC sees frame advance records this FR_ADVANCE_FIFO
reads frame advances determines cells sent
NEXT_ SERV
RL_DATA(1 RL_FSYNC(1)
following example calculations circuit performs. This example assumes structured line with four channels allocated queue. TFTC writes Line Frame FR_ADVANCE_FIFO. circuit determines queue which cell ready finding Transmit Calendar. this example, queue number 100. circuit reads number credits queue number 100. number credits always greater than because ready service. this example, QUE_CREDITS 59.375. circuit subtracts AVG_SUB_VALU, average number credits spent cell. (Remember: structured lines, average number credits cell 46-7/8. unstructured lines, average number credits cell 47.) Credits 59.375 46.875 Credits 12.5
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frame differential next service computed from number credits needed exceed NUM_CHAN, number channels allocated frame. 12.5 34.5 34.5 8.625
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Round 8.625 frame differential Therefore, next cell will sent nine frames ahead current cell.
circuit computes number credits those nine frames adds result total.
Frame differential three-eighths multiframe, remainder
calculates signaling credit adjustment multiplying frame differential expressed eighths multiframe number signaling bytes structure. Number signaling bytes structure channels bytes channel bytes multiframe Signaling adjustment three eighths 0.75 bytes
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writes remainder this division into FRAME_REMAINDER location next calculation this queue.
Frame differential eighths multiframe) (frame differential FRAME_REMAINDER)
Frame differential eighths multiframe) (frame differential FRAME_REMAINDER)
performing this calculation, also uses FRAME_REMAINDER value from QUE_CREDITS location T_QUEUE_TBL. This example assumes that FRAME_REMAINDER from previous calculation this queue.
converts frame differential from units frames units one-eighth multiframes.
calculation determines number signaling bytes structure, then generates average number signaling bytes inserted into cells frame, finally multiplies this average number frame differential adjust QUE_CREDITS.
queue line SDF-MF mode, makes signaling adjustment QUE_CREDITS before writing this value memory. queue SDF-MF mode, signaling adjustment made QUE_CREDITS calculated Step written memory.)
QUE_CREDITS 12.5 48.5
credits
Next frame present frame number
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UDF-ML/LOW_CDV set: other configurations:
Actual cell build time UTOPIA contention cell generation
However, signaling were added single queue, extra byte that occurs every bytes (assuming mode) requires compensation. this case, cell will sent every frames. Therefore, there will scheduler. Note that lines there LOW_CDV which LIN_STR_MODE memory register which will cause cells scheduled every bytes instead frame based. This eliminates caused scheduler. This mode only used UDF-ML mode when BYTES_PER_CELL High Speed mode cells always scheduled every bytes which assumes that partial cells never used mode.
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example, single queue with signaling using full cells, will need build cell every frames. Therefore, cell will scheduled every frames, scheduler will CDV. Also mode cells sent every time bytes received added.
scheduler resolution other words, works frame-based clock determine whether cell should sent during current frame. Therefore, ideal rate cell transmission multiple there will CDV. scheduler will never more than CDV.
Contention with other cells scheduled same time
Cell scheduling
following items affect transmit CDV:
SDF-FR Partial cell configurations with bytes_per_cell/num_chan integer:
ideal minimum transmit queue configurations follows. each case, frame rate assumed 125us.
Transmit
Unstructured lines different procedure. case unstructured lines, cell will sent every time bytes received. This assumes that partial cells used mode.
QUEUE_CREDITS 48.5 0.75 49.25 bytes
Then adds signaling credit adjustment total writes result memory, preparation next service this queue.
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When cell transmission requested, sent first available opportunity. Transmit cells have higher priority than cells scheduled circuit. Because this, care should taken ensure that cells overwhelm transmitter such extent that data cells starved adequate opportunities. rate cells must limited AAL1gator-4/8 maintain maximum data rate.
Cell Generation
Transmit Adaptation Layer Processor (TALP)
Since cells have higher priority than data cells transmission cells should distributed. cell assuming 38.88 SYS_CLK under worst case processor load.
there backpressure UTOPIA bus, cells will able sent which also causes CDV.
actual build time cell depends microprocessor activity contention with other internal state machines AAL1gator-4/8 memory bus. Therefore there will some minor that added cell basis, based current microprocessor/memory traffic. This usually less than very noticeable.
configurations that will require sending cell every frames where integer divisor (for (for T1), cells will always scheduled same frame unless offset field differently each cell.
Only cell built time. Thus multiple queues scheduled send cells during same frame, additional delay will incurred. queues activated deactivated that number queues scheduled ahead specific queue same frame changes, resulting change delay translates CDV. scheduling multiple cells same time known clumping. takes approximately build cell normally take under worst case traffic processor activity (Note this assumes 38.88 SYS_CLK). Therefore, each cell that waited could delay. When multiple queues scheduled send cells same time, cells will built sequential order, starting with going 256. Therefore, system that will adding dropping queues, higher number queues will experience more than lower number queues, depending many queues active time, scheduled within same frame. AAL1gator-4/8 minimizes effects clumping offsetting schedule point each line 1/8th frame. Also when queues added, offset field supplied which will force multiple cells same line scheduled different times. Queue FIFO section Processor Interface section more details.
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send cell, microprocessor writes cells into dedicated cell buffers located external memory. When cell assembled buffer, microprocessor must appropriate Command register TALP sends cell soon possible, then clears appropriate attention indicate requested cell been sent. requests both cells active time command register read AAL1gator-4/8, cell will always sent because assigned higher priority. Therefore, control order cell transmission, microprocessor should only attention time wait until cleared before setting other attention bit. cells optionally have 48-byte payload CRC-10 protected. This accomplished circuit that monitors cell sent TUTOPIA computes fly. then substitutes resultant CRC, preceded last bytes cell. generation enabled setting Word T_OAM_CELL.
Payload Construction
first byte payload provided lookup into T_QUEUE_TBL. This first byte consists bit, 3-bit sequence number, 4-bit sequence number protection field. depending SRTS pointer requirements. sequence number incremented every time cell sent same VPI/VCI. queue been configured AAL0 mode, this step done additional data byte loaded instead. line structured modes, structure pointer needed even-numbered cells. TALP inserts structure pointers according following rules: Only pointer inserted each 8-cell sequence.
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Payload construction most complex task TALP circuit performs. AAL1 requirements define much process, which follows:
entire header fixed queue. Headers maintained memory, queue. These headers include Header Error Check (HEC) character fifth byte. queue should deactivated during header replacement prevent cells from being constructed with incorrect header values. queue paused setting SUPPRESS_TRANSMISSION TX_CONFIG register. Emissions still scheduled, just transmissions suppressed. cells that suppressed, T_SUPPRESSED_CELL_CNT incremented.
Header Construction
TALP receives request send CSD-scheduled data cell there cell requests pending, will soon free. will look predefined Aheader from T_QUEUE_TBL (refer section 7.6.8 "T_QUEUE_TBL" page 122). will then obtain sequence number that queue from memory, structure pointer necessary. After these bytes written TUTOPIA interface, TALP will then data signaling frame buffers, locate data bytes correct channels, write them correct order UTOPIA interface. This cell building process described more detail following section.
Data Cell Generation
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last data byte last frame multiframe been set.
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Figure shows example payload generation process.
When signaling information sent, data obtained from signaling locations multiframe, with help channel allocation table (T_CHAN_ALLOC). This process proceeds byte-by-byte until following occurs: cell complete. signaling nibbles channels assigned queue have been sent.
cell complete.
structure used signaling determined mode line value E1_WITH_T1_SIG. Normally signaling structure will follow mode line. However, line mode E1_WITH_T1_SIG set, then signaling structure used. This means that single DS0, signaling inserted after data bytes instead after data bytes. data sent from data queue, this process continues byte-by-byte while updating pointers counters until following occurs:
TALP fills rest cell payload with data and/or signaling information. T_CHAN_ALLOC table transmit queue table determines which channels dedicated which queue. set, channel represented that assigned that queue. TALP successively writes data from marked channels into UTOPIA interface. LOOPBACK_ENABLE TX_CONFIG register then cell written into separate FIFO looped back RALP. queue-based parameter, BYTES_PER_CELL, decides when enough payload bytes have been obtained. this number fewer than then remaining bytes cell loaded with P_FILL_CHAR. This implies that because presence structure pointer, number fill bytes will constant structured data queues.
This algorithm supplies constant number structure pointers and, therefore, data bytes, regardless structure size. pointer inserted seventh byte location cell. force TALP build structure consisting single with signaling nibble pointer, T_CHAN_UNSTRUCT QUEUE_CONFIG word T_QUEUE_TBL.
dummy pointer value inserted cell number start-of-structure endof-structure occurs within 8-cell sequence.
pointer value inserted when structure coincides with 93-octet block AAL-user information.
pointer value inserted when structure starts byte directly after pointer itself.
pointer inserted first possible even-numbered cell every 8-cell sequence.
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Figure Payload Generation
writes bytes pairs into T_DATA_BUFFER RL_SER builds (segments) cell from T_DATA_BUFFER. this case from DS0s
T_DATA_BUFF
SYS_CLK 38.88 MHz.
Peak Cell Rates (PCRs) Structured Cell Formats
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Peak Cell Rates (PCRs) Unstructured Cell Formats 4,107 cells second (assuming bytes each AAL1 cell). 5,447 cells second (assuming bytes each AAL1 cell).
structured connection without CAS, cells second connection where (assuming completely filled cells). structured connection with CAS, cells second connection where (assuming completely filled cells). Each AAL1 cell either bytes, depending upon whether cell contains structure pointer.
numbers line,
Full cells used,
purposes discussion, following information assumed:
Peak Cell Rates (PCRs)
AAL0 mode cell build process takes bytes line data does AAL1 overhead bytes.
rames
Channel
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91,405 cells second (assuming bytes each AAL1 cell).
MODE SDF-FR SDF-MF SDF-FR SDF-MF
SYS_CLK=38.88
Table Minimum Partial Cell Size Permitted Connections Active SYS_CLK
Local Loopback Block(LOC_LPBK) AAL1gator-4/8 supports local loopback cells. Local loopback when cell generated TALP looped back RALP instead being sent UTOPIA TALP FIFO.
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UTOPIAI polls A1SP blocks determine A1SP cells available it's TALP_FIFO. TUTOPIA FIFO room cell, A1SP block selected, cell read from A1SP's TALP FIFO, moved into TUTOPIA FIFO.
This block contains cell FIFO which buffers cells going UTOPIA Interface block.
Transmit FIFO (TALP_FIFO)
Partial Cells used minimize amount delay required assemble cell. However, amount overhead required same amount data increases when partial cells used. This overhead increases number data bytes cell decreases. following table shows minimum partial cell sizes that supported different modes operation connections active device. smaller partial cell size desired, either some time slots/links must used only subset connections must that partial cell size. case total device should exceed 100,000 cells second with 38.88 SYSCLK 110,000 cells second with SYSCLK.
Peak Cell Rates Partial Cells
1,000 cells second A1SP cells. This rate cells calculated basis four cells second Transmitting receiving cells this rate consumes microprocessor accesses.
eight lines A1SP same rate, totaling Mbps throughput A1SP, then aggregate A1SP 53,191 cells second multiple-line unstructured data format (assuming bytes each AAL1 cell). lines same rate, aggregate A1SP 46,542.
118,980 cells second (assuming bytes each AAL1 cell).
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